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path: root/include/dt-bindings/clock/imx6qdl-clock.h
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2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Enrico Weigelt <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-12-10clk: imx6q: add DCICx clocks gateAnson Huang1-1/+3
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6q: add mmdc0 ipg clockAnson Huang1-1/+2
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-01clk: imx6: add EPIT clock supportColin Didier1-1/+3
Add EPIT clock support to the i.MX6Q clocking infrastructure. Signed-off-by: Colin Didier <[email protected]> Signed-off-by: Clément Peron <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-09-20clk: imx6: fix i.MX6DL clock tree to reflect realityLucas Stach1-1/+3
The current clock tree only implements the minimal set of differences between the i.MX6Q and the i.MX6DL, but that doesn't really reflect reality. Apply the following fixes to match the RM: - DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by GPU3D_CORE - GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF - GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Acked-by: Shawn Guo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-02-14clk: imx: Add clock support for imx6qpBai Ping1-1/+15
most of the clock tree structures on i.MX6 Quad Plus are same as on i.MX6Q. there still some differences between these two SOCs. compared to the i.XM6Q, the differents of clocks on i.MX6QP is mainly on: 1. New clock gate added to support the PRE and PRG modules 2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and CAN clock roots. 3. MMDC channel 1 clock gate is now controllable. 4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP 5. EMI clock root divider fix 6. other updates fo CSCMRx, CSCDRx and CS2CDR registers. detailed infomation, please refer to the i.MX6QP RM. Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-10-12clk: imx6: Add SPDIF_GCLK clock in clock treeShengjiu Wang1-1/+2
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-08-10ARM: clk-imx6q: Add CAAM clock supportVictoria Milhoan1-1/+4
Add CAAM clock support to the i.MX6 clocking infrastructure. Signed-off-by: Victoria Milhoan <[email protected]> Tested-by: Horia Geantă <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2015-03-02ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gateLiu Ying1-1/+2
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by: Liu Ying <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-03-02ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gateLiu Ying1-1/+2
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and MIPI core configuration clock. In order to gate/ungate the two MIPI DSI host controller relevant clocks, this patch adds the mipi_core_cfg clock as a shared clock gate. Suggested-by: Philipp Zabel <[email protected]> Signed-off-by: Liu Ying <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-03-02ARM: imx6q: clk: Add the video_27m clockLiu Ying1-1/+2
This patch supports the video_27m clock which is a fixed factor clock of the pll3_pfd1_540m clock. Signed-off-by: Liu Ying <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-10-25ARM: i.MX6: Fix "emi" clock name typoSteve Longerbeam1-4/+4
Fix a typo error, the "emi" names refer to the eim clocks. The change fixes typo in EIM and EIM_SLOW pre-output dividers and selectors clock names. Notably EIM_SLOW clock itself is named correctly. Signed-off-by: Steve Longerbeam <[email protected]> [[email protected]: ported to v3.17] Signed-off-by: Vladimir Zapolskiy <[email protected]> Cc: Sascha Hauer <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add gpt_3m clk for i.mx6qdlAnson Huang1-1/+2
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6q: add BYPASS support for PLL clocksShawn Guo1-1/+26
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang1-1/+3
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ESAIShengjiu Wang1-3/+4
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-07-18ARM: imx6qdl: switch to use macro for clock IDShawn Guo1-0/+224
Instead of using enum for clock ID, let's switch imx6qdl clock driver to use macro. In this case, device tree can reuse these macros to improve readability. Signed-off-by: Shawn Guo <[email protected]>
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