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The AST2500 has an explicit gate for the RMII RCLK for each of the two
MACs.
Signed-off-by: Andrew Jeffery <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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The SDCLK was named SDCLKCLK, and no one has used this yet.
Fix it.
Signed-off-by: Lei YU <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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* clk-imx6sx:
clk: imx6sl: correct ocram_podf clock type
clk: imx6sx: disable unnecessary clocks during clock initialization
clk: imx6sx: add missing lvds2 clock to the clock tree
* clk-imx7d-enet:
ARM: dts: imx7: correct enet ipg clock
clk: imx7d: correct enet clock CCGR registers
clk: imx7d: correct enet phy ref clock gates
* clk-aspeed-24:
clk: aspeed: Add 24MHz fixed clock
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Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.
Signed-off-by: Lei YU <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <[email protected]>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The ast2500 has an additional reset register that contains resets not
present in the ast2400. This enables support for this register, and adds
the one reset line that is controlled by it.
Reviewed-by: Andrew Jeffery <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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These will be used by the clock driver and device trees.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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