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2024-06-03spi: pxa2xx: Print DMA burst size only when DMA is enabledAndy Shevchenko1-1/+2
Print DMA burst size only when DMA is enabled to avoid making a false impression that DMA is enabled when it may be not. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03spi: pxa2xx: Utilise temporary variable for struct deviceAndy Shevchenko1-10/+11
We have a temporary variable to keep a pointer to struct device. Utilise it where it makes sense. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03spi: pxa2xx: Remove hard coded number of chip select pinsAndy Shevchenko1-4/+0
Remove hard coded number of chip select pins for Intel Braswell. This comes via property. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03spi: pxa2xx: Remove no more needed driver dataAndy Shevchenko1-6/+6
Since the ACPI enumerated devices provide a property with SSP type, there is no more necessity to bear the copy of them in the ID table. Drop the driver data in ACPI ID table. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03spi: pxa2xx: Reorganize the SSP type retrievalAndy Shevchenko1-14/+11
The old Intel platforms, such as Intel Braswell, also provide the property of SSP type. Reorganize the pxa2xx_spi_init_pdata() to take that into account. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03spi: pxa2xx: Wrap pxa_ssp_request() to be device managed resourceAndy Shevchenko1-18/+32
In the error path or remove path the reference counter in PXA SSP driver may be dropped before the other resources, that were allocated after bumbing the reference counter. This breaks reversed order of freeing and might have an undesired side effects. Prevent this from happening by wrapping pxa_ssp_request() to be device managed resource. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2024-06-03gpiolib: make gpiochip_set_desc_names() return voidBartosz Golaszewski1-8/+4
gpiochip_set_desc_names() cannot fail so drop its return value. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-06-03phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEsdevi priya1-0/+309
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <[email protected]> Co-developed-by: Anusha Rao <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: devi priya <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom-qmp: Add missing register definitions for PCS V5devi priya1-0/+14
Add missing register offsets for PCS V5 registers. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: devi priya <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom-qmp: Add missing offsets for Qserdes PLL registers.devi priya1-0/+3
Add missing register offsets for Qserdes PLL. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: devi priya <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsetsAbel Vesa2-29/+162
Currently, none of the X1E80100 supported boards upstream have enabled DP. As for USB, the reason it is not broken when it's obvious that the offsets are wrong is because the only difference with respect to USB is the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to work, the DP serdes tables need to be added as they have different values for V6 N4 when compared to V6 ones, even though they use the same V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as well. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <[email protected]> Signed-off-by: Kuogee Hsieh <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom-qmp: pcs: Add missing v6 N4 register offsetsAbel Vesa1-0/+32
The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS register offsets, which are different. Add the offsets so the mentioned platform can be fixed later on. Add the new PCS offsets in a dedicated header file. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <[email protected]> Signed-off-by: Kuogee Hsieh <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom-qmp: qserdes-txrx: Add missing registers offsetsAbel Vesa1-0/+13
Currently, the x1e80100 uses pure V6 register offsets for DP part of the combo PHY. This hasn't been an issue because external DP is not yet enabled on any of the boards yet. But in order to enabled it, all these new V6 N4 register offsets are needed. So add them. Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets") Co-developed-by: Kuogee Hsieh <[email protected]> Signed-off-by: Kuogee Hsieh <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: miphy28lp: remove unused struct 'miphy_initval'Dr. David Alan Gilbert1-5/+0
'miphy_initval' is unused since the original commit 2c14e9be0c60 ("phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY"). Remove it. Signed-off-by: Dr. David Alan Gilbert <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: starfive: remove unused struct 'regval'Dr. David Alan Gilbert1-5/+0
'regval' is unused since the original commit f8aa660841bc ("phy: starfive: Add mipi dphy rx support"). Remove it. Signed-off-by: Dr. David Alan Gilbert <[email protected]> Reviewed-by: Changhuang Liang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: qcom-qmp-usb: Add sc8180x USB UNIPHYBjorn Andersson1-0/+3
The SC8180X platform has two UNIPHY blocks, add support for these in the QMP driver. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: add suspend and resume supportThomas Richard1-0/+57
Add suspend and resume support. The already_configured flag is cleared during the suspend stage to force the PHY initialization during the resume stage. Co-developed-by: Théo Lebrun <[email protected]> Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: remove noop_ops phy operationsThomas Richard1-17/+13
Even if a PHY is already configured, the PHY operations are needed during resume stage, as the PHY is in reset state. The noop_ops PHY operations is removed to always have PHY operations. The already_configured flag is checked at the begening of init, configure and poweron operations to keep the already_configured behaviour. Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: add already_configured to struct cdns_torrent_phyThomas Richard1-5/+5
Add already_configured to struct cdns_torrent_phy, so it can be used at differents stages. Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: register resets even if the phy is already configuredThomas Richard1-5/+5
Resets are needed during suspend and resume stages. So they shall be registered during the probe even the phy is already initialized. The function cdns_torrent_reset is renamed cdns_torrent_of_get_reset() to make it clear. Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: extract calls to clk_get from cdns_torrent_clkThomas Richard1-16/+21
Extract calls to clk_get from cdns_torrent_clk into a separate function. It needs to call cdns_torrent_clk at resume without looking up the clock. Co-developed-by: Théo Lebrun <[email protected]> Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: ti: phy-j721e-wiz: add resume supportThomas Richard1-0/+29
Add resume support. It has been tested on J7200 SR1.0 and SR2.0. Co-developed-by: Théo Lebrun <[email protected]> Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: ti: phy-j721e-wiz: split wiz_clock_init() functionThomas Richard1-29/+37
The wiz_clock_init() function mixes probe and hardware configuration. Rename the wiz_clock_init() to wiz_clock_probe() and move the hardware configuration part in a new function named wiz_clock_init(). This hardware configuration sequence must be called during the resume stage of the driver. Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: ti: phy-j721e-wiz: use dev_err_probe() instead of dev_err()Thomas Richard1-25/+21
Use dev_err_probe() instead of dev_err() in wiz_clock_init() to simplify the code and standardize the error output. Signed-off-by: Thomas Richard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03phy: cadence-torrent: Add SGMII + QSGMII multilink configuration for 100MHz ↵Swapnil Jakhade1-4/+60
refclk Add register sequences for SGMII + QSGMII multilink configuration for 100MHz refclk. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03wifi: ath12k: add hw_link_id in ath12k_pdevKarthikeyan Periyasamy3-1/+3
Currently, hw_link_id is sent in WMI service ready event but it is not parsed anywhere. But, in future, for multi-link operation, this parameter would be needed by many WMI commands such as WMI beacon template (WMI_BCN_TMPL_CMDID), WMI vdev start for Multi-link virtual AP interfaces (WMI_VDEV_START_REQUEST_CMDID), WMI peer assoc command (WMI_PEER_ASSOC_CMDID) for Multi-link peer and so on. Hence, add changes to parse and store the hw_link_id received in WMI service ready event in ath12k_pdev structure. Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <[email protected]> Signed-off-by: Harshitha Prem <[email protected]> Acked-by: Jeff Johnson <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://msgid.link/[email protected]
2024-06-03wifi: ath12k: add panic handlerBaochen Qiang4-0/+49
Currently for ath12k PCI devices, firmware could be running in one of several execution environments, e.g., PBL, SBL and mission mode etc. Among which PBL is the only stage where PCIe link negotiation could happen. So normally firmware runs in PBL in order to be enumerated during system reboot. However it might not work in kernel crash scenario: ath12k target is not found after warm reboot from kernel crash. This is because when kernel crashes, ath12k host does nothing to firmware. And during warm reboot, WLAN power is sustained. So firmware is likely to keep running in mission mode throughout the bootup process. As a result PCIe link is not established and thus target not enumerated. So add a handler in panic notification list for ath12k. When kernel crashes, this handler gets called and tries to reset target to PBL state. Then PCIe link negotiation could happen and target gets enumerated. This change applies to all PCI devices including WCN7850 and QCN9274. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0-03427-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.15378.4 Signed-off-by: Baochen Qiang <[email protected]> Acked-by: Jeff Johnson <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://msgid.link/[email protected]
2024-06-03gpio: tqmx86: fix broken IRQ_TYPE_EDGE_BOTH interrupt typeMatthias Schiffer1-4/+42
The TQMx86 GPIO controller only supports falling and rising edge triggers, but not both. Fix this by implementing a software both-edge mode that toggles the edge type after every interrupt. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Co-developed-by: Gregor Herburger <[email protected]> Signed-off-by: Gregor Herburger <[email protected]> Signed-off-by: Matthias Schiffer <[email protected]> Link: https://lore.kernel.org/r/515324f0491c4d44f4ef49f170354aca002d81ef.1717063994.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-06-03gpio: tqmx86: store IRQ trigger type and unmask status separatelyMatthias Schiffer1-20/+28
irq_set_type() should not implicitly unmask the IRQ. All accesses to the interrupt configuration register are moved to a new helper tqmx86_gpio_irq_config(). We also introduce the new rule that accessing irq_type must happen while locked, which will become significant for fixing EDGE_BOTH handling. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer <[email protected]> Link: https://lore.kernel.org/r/6aa4f207f77cb58ef64ffb947e91949b0f753ccd.1717063994.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-06-03gpio: tqmx86: introduce shadow register for GPIO output valueMatthias Schiffer1-7/+11
The TQMx86 GPIO controller uses the same register address for input and output data. Reading the register will always return current inputs rather than the previously set outputs (regardless of the current direction setting). Therefore, using a RMW pattern does not make sense when setting output values. Instead, the previously set output register value needs to be stored as a shadow register. As there is no reliable way to get the current output values from the hardware, also initialize all channels to 0, to ensure that stored and actual output values match. This should usually not have any effect in practise, as the TQMx86 UEFI sets all outputs to 0 during boot. Also prepare for extension of the driver to more than 8 GPIOs by using DECLARE_BITMAP. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/d0555933becd45fa92a85675d26e4d59343ddc01.1717063994.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-06-03gpio: tqmx86: fix typo in Kconfig labelGregor Herburger1-1/+1
Fix description for GPIO_TQMX86 from QTMX86 to TQMx86. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Gregor Herburger <[email protected]> Signed-off-by: Matthias Schiffer <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/e0e38c9944ad6d281d9a662a45d289b88edc808e.1717063994.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-06-03soundwire: intel_ace2.x: add AC timing extensions for PantherLakePierre-Louis Bossart3-0/+40
The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL register to better control clocks/delays. These bitfields were reserved/zero in the ACE2.x IP, to simplify the integration the new bifields are added unconditionally. The behavior will only be impacted when the firmware exposes DSD properties to set non-zero values. Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Péter Ujfalusi <[email protected]> Reviewed-by: Ranjani Sridharan <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03soundwire: bus: add stream refcountPierre-Louis Bossart1-0/+5
The notion of stream is by construction based on a multi-bus capability, to allow for aggregation of Peripheral devices or functions located on different segments. We currently count how many master_rt contexts are used by a stream, but we don't have the dual refcount of how many streams are allocated on a given bus. This refcount will be useful to check if BTP/BRA streams can be allocated. Note that the stream_refcount is modified in sdw_master_rt_alloc() and sdw_master_rt_free() which are both called with the bus_lock mutex held, so there's no need for refcount_ primitives for additional protection. Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03soundwire: debugfs: add interface to read/write commandsPierre-Louis Bossart1-0/+150
We have an existing debugfs files to read standard registers (DP0/SCP/DPn). This patch provides a more generic interface to ANY set of read/write contiguous registers in a peripheral device. In follow-up patches, this interface will be extended to use BRA transfers. The sequence is to use the following files added under the existing debugsfs directory for each peripheral device: command (write 0, read 1) num_bytes start_address firmware_file (only for writes) read_buffer (only for reads) Example for a read command - this checks the 6 bytes used for enumeration. cd /sys/kernel/debug/soundwire/master-0-0/sdw\:0\:025d\:0711\:01/ echo 1 > command echo 6 > num_bytes echo 0x50 > start_address echo 1 > go cat read_buffer address 0x50 val 0x30 address 0x51 val 0x02 address 0x52 val 0x5d address 0x53 val 0x07 address 0x54 val 0x11 address 0x55 val 0x01 Example with a 2-byte firmware file written in DP0 address 0x22 od -x /lib/firmware/test_firmware 0000000 0a37 0000002 cd /sys/kernel/debug/soundwire/master-0-0/sdw\:0\:025d\:0711\:01/ echo 0 > command echo 2 > num_bytes echo 0x22 > start_address echo "test_firmware" > firmware_file echo 1 > go cd /sys/kernel/debug/soundwire/master-0-0/sdw\:0\:025d\:0711\:01/ echo 1 > command echo 2 > num_bytes echo 0x22 > start_address echo 1 > go cat read_buffer address 0x22 val 0x37 address 0x23 val 0x0a Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03net: dsa: ocelot: unexport felix_phylink_mac_ops and felix_switch_opsVladimir Oltean2-7/+2
Now that the common felix_register_switch() from the umbrella driver is the only entity that accesses these data structures, we can remove them from the list of the exported symbols. Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Sai Krishna <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: common probing codeVladimir Oltean5-111/+63
Russell King suggested that felix_vsc9959, seville_vsc9953 and ocelot_ext have a large portion of duplicated init code, which could be made common [1]. [1]: https://lore.kernel.org/all/[email protected]/ Here, we take the following common steps: - "felix" and "ds" structure allocation - "felix", "ocelot" and "ds" basic structure initialization - dsa_register_switch() call and we make a common function out of them. For every driver except felix_vsc9959, this is also the entire probing procedure. For felix_vsc9959, we also need to do some PCI-specific stuff, which can easily be reordered to be done before, and unwound on failure. We also have to convert the bus-specific platform_set_drvdata() and pci_set_drvdata() calls into dev_set_drvdata(). But this should have no impact on the behavior. Suggested-by: "Russell King (Oracle)" <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Tested-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: use ds->num_tx_queues = OCELOT_NUM_TC for all modelsVladimir Oltean4-6/+5
Russell King points out that seville_vsc9953 populates felix->info->num_tx_queues = 8, but this doesn't make it all the way into ds->num_tx_queues (which is how the user interface netdev queues get allocated) [1]. [1]: https://lore.kernel.org/all/20240415160150.yejcazpjqvn7vhxu@skbuf/ When num_tx_queues=0 for seville, this is implicitly converted to 1 by dsa_user_create(), and this is good enough for basic operation for a switch port. The tc qdisc offload layer works with netdev TX queues, so for QoS offload we need to pretend we have multiple TX queues. The VSC9953, like ocelot_ext, doesn't export QoS offload, so it doesn't really matter. But we can definitely set num_tx_queues=8 for all switches. The felix->info->num_tx_queues construct itself seems unnecessary. It was introduced by commit de143c0e274b ("net: dsa: felix: Configure Time-Aware Scheduler via taprio offload") at a time when vsc9959 (LS1028A) was the only switch supported by the driver. 8 traffic classes, and 1 queue per traffic class, is a common architectural feature of all switches in the family. So they could all just set OCELOT_NUM_TC and be fine. Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Colin Foster <[email protected]> Tested-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: move devm_request_threaded_irq() to felix_setup()Vladimir Oltean3-21/+33
The current placement of devm_request_threaded_irq() is inconvenient. It is between the allocation of the "felix" structure and dsa_register_switch(), both of which we'd like to refactor into a function that's common for all switches. But the IRQ is specific to felix_vsc9959. A closer inspection of the felix_irq_handler() code suggests that it does things that depend on the data structures having been fully initialized. For example, ocelot_get_txtstamp() takes &port->tx_skbs.lock, which has only been initialized in ocelot_init_port() which has not run yet. It is not one of those IRQF_SHARED IRQs, so CONFIG_DEBUG_SHIRQ_FIXME shouldn't apply here, and thus, it doesn't really matter, because in practice, the IRQ will not be triggered so early. Nonetheless, it is a good practice for the driver to be prepared for it to fire as soon as it is requested. Create a new felix->info method for running custom code for vsc9959 from within felix_setup(), and move the request_irq() call there. The ocelot_ext should have an IRQ as well, so this should be a step in the right direction for that model (VSC7512) as well. Some minor changes are made while moving the code. Casts from void * aren't necessary, so drop them, and rename felix_irq_handler() to the more specific vsc9959_irq_handler(). Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: consistently use devres in felix_pci_probe()Vladimir Oltean1-25/+15
Russell King suggested that felix_vsc9959, seville_vsc9953 and ocelot_ext have a large portion of duplicated init and teardown code, which could be made common [1]. The teardown code could even be simplified away if we made use of devres, something which is used here and there in the felix driver, just not very consistently. [1] https://lore.kernel.org/all/[email protected]/ Prepare the ground in the felix_vsc9959 driver, by allocating the data structures using devres and deleting the kfree() calls. This also deletes the "Failed to allocate ..." message, since memory allocation errors are extremely loud anyway, and it's hard to miss them. Suggested-by: "Russell King (Oracle)" <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: delete open coded status = "disabled" parsingVladimir Oltean1-5/+0
Since commit 6fffbc7ae137 ("PCI: Honor firmware's device disabled status"), PCI device drivers with OF bindings no longer need this check. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: use devres in seville_probe()Vladimir Oltean1-31/+13
Russell King suggested that felix_vsc9959, seville_vsc9953 and ocelot_ext have a large portion of duplicated init and teardown code, which could be made common [1]. The teardown code could even be simplified away if we made use of devres, something which is used here and there in the felix driver, just not very consistently. [1] https://lore.kernel.org/all/[email protected]/ Prepare the ground in the seville_vsc9953 driver, by allocating the data structures using devres and deleting the kfree() calls. This also deletes the "Failed to allocate ..." message, since memory allocation errors are extremely loud anyway, and it's hard to miss them. Suggested-by: "Russell King (Oracle)" <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03net: dsa: ocelot: use devres in ocelot_ext_probe()Vladimir Oltean1-19/+5
Russell King suggested that felix_vsc9959, seville_vsc9953 and ocelot_ext have a large portion of duplicated init and teardown code, which could be made common [1]. The teardown code could even be simplified away if we made use of devres, something which is used here and there in the felix driver, just not very consistently. [1] https://lore.kernel.org/all/[email protected]/ Prepare the ground in the ocelot_ext driver, by allocating the data structures using devres and deleting the kfree() calls. This also deletes the "Failed to allocate ..." message, since memory allocation errors are extremely loud anyway, and it's hard to miss them. Suggested-by: "Russell King (Oracle)" <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Colin Foster <[email protected]> Tested-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-06-03soundwire: fix usages of device_get_named_child_node()Pierre-Louis Bossart3-7/+32
The documentation for device_get_named_child_node() mentions this important point: " The caller is responsible for calling fwnode_handle_put() on the returned fwnode pointer. " Add fwnode_handle_put() to avoid leaked references. Signed-off-by: Pierre-Louis Bossart <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-06-03spi: Merge up fixesMark Brown110-559/+942
We need these to get the i.MX8 boards working in CI again.
2024-06-03regmap: Merge up fixesMark Brown110-566/+971
We need these to get the i.MX8 boards working in CI again.
2024-06-03irqchip/sifive-plic: Chain to parent IRQ after handlers are readySamuel Holland1-17/+17
Now that the PLIC uses a platform driver, the driver is probed later in the boot process, where interrupts from peripherals might already be pending. As a result, plic_handle_irq() may be called as early as the call to irq_set_chained_handler() completes. But this call happens before the per-context handler is completely set up, so there is a window where plic_handle_irq() can see incomplete per-context state and crash. Avoid this by delaying the call to irq_set_chained_handler() until all handlers from all PLICs are initialized. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Reported-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Anup Patel <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Closes: https://lore.kernel.org/r/CAMuHMdVYFFR7K5SbHBLY-JHhb7YpgGMS_hnRWm8H0KD-wBo+4A@mail.gmail.com/
2024-06-03platform/x86: thinkpad_acpi: Use 2-argument strscpy()Andy Shevchenko1-4/+2
Use 2-argument strscpy(), which is not only shorter but also provides an additional check that destination buffer is an array. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: think-lmi: Use 2-argument strscpy()Andy Shevchenko1-2/+2
Use 2-argument strscpy(), which is not only shorter but also provides an additional check that destination buffer is an array. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: serial-multi-instantiate: Use 2-argument strscpy()Andy Shevchenko1-2/+2
Use 2-argument strscpy(), which is not only shorter but also provides an additional check that destination buffer is an array. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel: chtwc_int33fe: Use 2-argument strscpy()Andy Shevchenko1-3/+3
Use 2-argument strscpy(), which is not only shorter but also provides an additional check that destination buffer is an array. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>