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2024-06-21clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clkPeng Fan1-2/+2
The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocksOliver F. Brown1-4/+20
The MIPI Pixel and PHY Reference can use the bypass clock as a source. The MIPI bypass clock is the Pixel clock from the Display controller via the pixel link. Using the pixel clock for the PHY reference allows the MIPI bit clock match the pixel rate exactly. The MIPI pixel clock is currently set to be source from the bypass clock in the SCFW. This patch allows the pixel clock parent to be set by the kernel in the event that the SCFW default clock parent may change in the future. Signed-off-by: Oliver F. Brown <[email protected]> Signed-off-by: Robert Chiras <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8qxp: Add LVDS bypass clocksPeng Fan1-9/+8
For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks with imx_clk_scu2 as the parent needs to explicitly set. In order to make sure MIPI DSI works well after suspend/resume, the LVDS pixel and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same MSLICE. They all share the same clock parent. So, setting the parent source or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for either clock initialization order. For MIPI case, LVDS must be initialized first. Signed-off-by: Ranjani Vaidyanathan <[email protected]> Signed-off-by: Oliver F. Brown <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical oneJacky Bai1-1/+1
The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8mn: add sai7_ipg_clk clock settingsAdrian Alonso1-0/+1
Add IMX8MN_CLK_SAI7_IPG clock entry. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Adrian Alonso <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7DPeng Fan1-1/+1
Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to propagate rate changes from LCDIF pixel clock to video PLL to provide more accurate clock rate for LCDIF pixel clock. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7DPeng Fan1-2/+2
For i.MX7D DRAM related mux clock, the clock source change should ONLY be done done in low level asm code without accessing DRAM, and then calling clk API to sync the HW clock status with clk tree, it should never touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock parent will be disabled when DRAM is active, and system will hang. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8mp: fix clock tree update of TF-A managed clocksZhipeng Wang1-2/+2
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c) commit 926bf91248dd ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Another reason to this patch is that powersave image BT music requires dram to be 400MTS, so clk_set_parent(dram_alt_src, sys1_pll_800m); is required. Without this patch, it will not succeed. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Zhipeng Wang <[email protected]> Reviewed-by: Ahmad Fatoum <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: fracn-gppll: fix fractional part of PLL getting lostPengfei Li1-0/+4
Fractional part of PLL gets lost after re-enabling the PLL. the MFN can NOT be automatically loaded when doing frac PLL enable/disable, So when re-enable PLL, configure mfn explicitly. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Pengfei Li <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: composite-7ulp: Check the PCC present bitYe Li1-0/+7
When some module is disabled by fuse, its PCC PR bit is default 0 and PCC is not operational. Any write to this PCC will cause SError. Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: composite-93: keep root clock on when mcore enabledJacky Bai1-7/+8
Previously we assumed that the root clock slice is enabled by default when kernel boot up. But the bootloader may disable the clocks before jump into kernel. The gate ops should be registered rather than NULL to make sure the disabled clock can be enabled when kernel boot up. Refine the code to skip disable the clock if mcore booted. Fixes: a740d7350ff7 ("clk: imx: imx93: add mcore_booted module paratemter") Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Peng Fan <[email protected]> Tested-by: Chancel Liu <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: composite-8m: Enable gate clk with mcore_bootedPeng Fan1-11/+42
Bootloader might disable some CCM ROOT Slices. So if mcore_booted set with display CCM ROOT disabled by Bootloader, kernel display BLK CTRL driver imx8m_blk_ctrl_driver_init may hang the system because the BUS clk is disabled. Add back gate ops, but with disable doing nothing, then the CCM ROOT will be enabled when used. Fixes: bb7e897b002a ("clk: imx8m: check mcore_booted before register clk") Reviewed-by: Ye Li <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx6ul: fix default parent for enet*_ref_selSebastien Laveze1-2/+2
The clk_set_parent for "enet1_ref_sel" and "enet2_ref_sel" are incorrect, therefore the original requirements to have "enet_clk_ref" as output sourced by iMX ENET PLL as a default config is not met. Only "enet[1,2]_ref_125m" "enet[1,2]_ref_pad" are possible parents for "enet1_ref_sel" and "enet2_ref_sel". This was observed as a regression using a custom device tree which was expecting this default config. This can be fixed at the device tree level but having a default config matching the original behavior (before refclock mux) will avoid breaking existing configs. Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") Link: https://lore.kernel.org/lkml/20230306020226.GC143566@dragon/T/ Signed-off-by: Sebastien Laveze <[email protected]> Reviewed-by: Oleksij Rempel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpllShengjiu Wang1-2/+11
According to Reference Manual of i.MX8MP The parent clock of "earc_phy" is "sai_pll_out_div2", The parent clock of "audpll" is "osc_24m". Add CLK_GATE_PARENT() macro for usage of specifying parent clock. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocksShengjiu Wang1-4/+6
Add CLK_SET_RATE_PARENT flags that when the device driver sets the child clock rate, parent clock frequency can be refined accordingly. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issueLuo Jie1-1/+1
The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Luo Jie <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21soc: qcom: icc-bwmon: Fix refcount imbalance seen during bwmon_removeSibi Sankar1-1/+3
The following warning is seen during bwmon_remove due to refcount imbalance, fix this by releasing the OPPs after use. Logs: WARNING: at drivers/opp/core.c:1640 _opp_table_kref_release+0x150/0x158 Hardware name: Qualcomm Technologies, Inc. X1E80100 CRD (DT) ... Call trace: _opp_table_kref_release+0x150/0x158 dev_pm_opp_remove_table+0x100/0x1b4 devm_pm_opp_of_table_release+0x10/0x1c devm_action_release+0x14/0x20 devres_release_all+0xa4/0x104 device_unbind_cleanup+0x18/0x60 device_release_driver_internal+0x1ec/0x228 driver_detach+0x50/0x98 bus_remove_driver+0x6c/0xbc driver_unregister+0x30/0x60 platform_driver_unregister+0x14/0x20 bwmon_driver_exit+0x18/0x524 [icc_bwmon] __arm64_sys_delete_module+0x184/0x264 invoke_syscall+0x48/0x118 el0_svc_common.constprop.0+0xc8/0xe8 do_el0_svc+0x20/0x2c el0_svc+0x34/0xdc el0t_64_sync_handler+0x13c/0x158 el0t_64_sync+0x190/0x194 --[ end trace 0000000000000000 ]--- Fixes: 0276f69f13e2 ("soc: qcom: icc-bwmon: Set default thresholds dynamically") Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by: Sibi Sankar <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21clk: qcom: select right config in CLK_QCM2290_GPUCC definitionLukas Bulwahn1-1/+1
Commit 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by: Lukas Bulwahn <[email protected]> Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21clk: qcom: Remove QCOM_RPMCC symbolElliot Berman1-5/+0
This symbol is selected by a couple drivers, but isn't used by anyone and hasn't been for years now. Drop it. No functional change intended. Signed-off-by: Elliot Berman <[email protected]> Reviewed-by: Mike Tipton <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21Merge branch '[email protected]' into ↵Bjorn Andersson4-8/+50
drivers-for-6.11 Merge SMEM and SCM patches related to GPU features through a topic branch to make it possible to share these with the msm-next DRM tree.
2024-06-21soc: qcom: smem: Add a feature code getterKonrad Dybcio1-0/+33
Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely identifying the specific SKU and the precise speed bin (in the general meaning of this word, anyway): a pair of values called Product Code and Feature Code. Based on this information, we can deduce the available frequencies for things such as Adreno. In the case of Adreno specifically, Pcode is useless for non-prototype SoCs. Introduce a getter for the feature code and export it. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21soc: qcom: Move some socinfo defines to the headerKonrad Dybcio1-8/+0
In preparation for parsing the chip "feature code" (FC) and "product code" (PC) (essentially the parameters that let us conclusively characterize the sillicon we're running on, including various speed bins), move the socinfo version defines to the public header. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21firmware: qcom: scm: Add gpu_init_regs callConnor Abbott2-0/+17
This will used by drm/msm to initialize GPU registers that Qualcomm's firmware doesn't make writeable to the kernel. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-06-21clk: imx: clk-audiomix: Add reset controllerShengjiu Wang2-0/+64
Audiomix block control can be a reset controller for Enhanced Audio Return Channel (EARC), which is one of modules in this audiomix subsystem. The reset controller is supported by the auxiliary device framework. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Marco Felsch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21Merge tag 'drm-intel-next-2024-06-19' of ↵Dave Airlie172-4661/+7943
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next drm/i915 feature pull for v6.11: Features and functionality: - Battlemage (BMG) Xe2 HPD display enabling (Balasubramani, Clint, Gustavo, José, Matt, Anusha, Lucas, Ravi, Radhakrishna, Nirmoy, Ankit, Matthew) - Panel Replay enabling (Jouni, Animesh) - DP AUX-less ALPM (Advanced Link Power Management) and LOBF (Link off between frames) enabling (Animesh, Jouni) - Enable link training failure fallback for DP MST links (Imre) - CMRR (Content Match Refresh Rate) enabling (Mitul) - Allow the first async flip to change modifier (Ville) - Enable eDP AUX based HDR backlight (Suraj) - Increase ADL-S/ADL-P/DG2+ max TMDS bitrate to 6 Gbps (Ville) Refactoring and cleanups: - Stop using implicit dev_priv local variable in macros (Jani) - Expand and clean up VBT table definitions (Ville) - PSR/ALPM refactoring (Jouni, Animesh) - Plane fb refactoring (Ville) - Rawclk, FSB, and mem frequency refactoring (Jani) - GVT register macro usage cleanups (Jani, Ville) - Plane, cursor, wm and ddb register macro and usage cleanups (Ville) - Pipe CRC register macro cleanups (Ville) - PCI ID macro cleanups and refactoring to match xe style (Jani) - Move drm-intel repo to gitlab.freedesktop.org (Ryszard) - Identify all platforms/subplatforms in display probe (Jani) - Move Intel drm headers under include/drm/intel (Jani) - Drop local redundant W=1 warnings in favour of drm subsystem warnigs (Jani) - Include cleanups; include what you use (Jani) - Convert overlay and DMC error state printing to drm_printer (Jani) - Joiner renames (Stan) - DSB interface cleanups (Ville) - Improve workaround for disabling FBC when VT-d is active (Vinod) - State checker refactoring and cleanups for color, planes and cdclk (Ville) - Cleanups around scanline arithmetic (Ville) - Use drm_crtc_vblank_crtc() instead of open coding (Ville) - DSC cleanups (Ville) Fixes: - Improve VBT array bounds check (Luca) - LNL PSR fixes (Jouni) - Audio workaround, disable min hblank fix (Uma) - Stop selecting ACPI_BUTTON config (Jani) - Add MTL Cx0 PHY config compare (Mika) - Fix MTL C20 PHY port clock verification (Mika) - Fix static analyzer warning for uapi.event access (Luca) - HDCP fixes and workarounds (Suraj) - Fix DP MST DSC input BPP computation (Imre) - Fix assert on pending async-put power domain work (Imre) - Fix documentation build for DMC wakelocks (Luca) - Disable DSC on eDP when indicated by VBT (Ville) DRM Core changes: - Various DPCD register additions for panel replay and ALPM (Jouni) - Add target_rr_divider to adaptive sync SDP (Mitul) Xe driver changes: - Remove unused xe->enabled_irq_mask and xe->sb_lock members (Jani) - i915 display compat header cleanups (Jani) - Remove redundant copy of intel_fbdev_fb.h (Ville) - Add process name to devcoredump (José) - Add xe_gt_err_once() (Matthew) - Implement transient flush for BMG/Xe3 (Nirmoy) Merges: - Backmerges to sync with xe, drm-misc and upstream (Rodrigo, Jani) Signed-off-by: Dave Airlie <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20cpufreq/amd-pstate: fix setting policy current frequency valueMeng Li1-5/+12
When scaling min/max freq values were being setted, the value of policy->cur need to update. Signed-off-by: Meng Li <[email protected]> Acked-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: auto-load pstate driver by defaultPerry Yuan1-7/+17
If the `amd-pstate` driver is not loaded automatically by default, it is because the kernel command line parameter has not been added. To resolve this issue, it is necessary to call the `amd_pstate_set_driver()` function to enable the desired mode (passive/active/guided) before registering the driver instance. This ensures that the driver is loaded correctly without relying on the kernel command line parameter. When there is no parameter added to command line, Kernel config will provide the default mode to load. Meanwhile, user can add driver mode in command line which will override the kernel config default option. Reported-by: Andrei Amuraritei <[email protected]> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218705 Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/83301c4cea4f92fb19e14b23f2bac7facfd8bdbb.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: enable shared memory type CPPC by defaultPerry Yuan1-12/+1
The amd-pstate-epp driver has been implemented and resolves the performance drop issue seen in passive mode for shared memory type CPPC systems. Users who enable the active mode driver will not experience a performance drop compared to the passive mode driver. Therefore, the EPP driver should be loaded by default for shared memory type CPPC system to get better performance. Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/c705507cf3ee790e544251cfd897ed11e8e57712.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: switch boot_cpu_has() to cpu_feature_enabled()Perry Yuan1-12/+12
replace the usage of the deprecated boot_cpu_has() function with the modern cpu_feature_enabled() function. The switch to cpu_feature_enabled() ensures compatibility with the latest CPU feature detection mechanisms and improves code maintainability. Acked-by: Mario Limonciello <[email protected]> Suggested-by: Borislav Petkov (AMD) <[email protected]> Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Link: https://lore.kernel.org/r/f1567593ac5e1d38343067e9c681a8c4b0707038.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: add debug message while CPPC is supported and disabled ↵Perry Yuan1-0/+26
by SBIOS If CPPC feature is supported by the CPU however the CPUID flag bit is not set by SBIOS, the `amd_pstate` will be failed to load while system booting. So adding one more debug message to inform user to check the SBIOS setting, The change also can help maintainers to debug why amd_pstate driver failed to be loaded at system booting if the processor support CPPC. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218686 Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Acked-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/42c953616ac121bd1e5c329e83d015a02e6b32c7.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: show CPPC debug message if CPPC is not supportedPerry Yuan1-0/+19
Add CPU ID checking in case the driver attempt to load on systems where CPPC functionality is unavailable. And the warning message will not be shown if CPPC is not supported. It will also print debug message if the CPU has no CPPC support that helps to debug the driver loading failure issue. Reported-by: Paul Menzel <[email protected]> Closes: https://lore.kernel.org/linux-pm/CYYPR12MB8655D32EA18574C9497E888A9C122@CYYPR12MB8655.namprd12.prod.outlook.com/T/#t Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Acked-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/437dbd581a4119465581330081d9b1e289482ba2.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: remove unused variable nominal_freqPerry Yuan1-4/+2
removed the unused variable `nominal_freq` for build warning. This variable was defined and assigned a value in the previous code, but it was not used in the subsequent code. Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Reported-by: kernel test robot <[email protected]> Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Gautham R. Shenoy <[email protected]> Acked-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/b7ef41557f71d40d098393ddb27f0fe1f23648ae.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: optimize the initial frequency values verificationPerry Yuan1-17/+18
To enhance the debugging capability of the driver loading failure for broken CPPC ACPI tables, it can optimize the expression by moving the verification of `min_freq`, `nominal_freq`, and other dependency values to the `amd_pstate_init_freq()` function where they are initialized. If any of these values are incorrect, the `amd-pstate` driver will not be registered. By ensuring that these values are correct before they are used, it will facilitate the debugging process when encountering driver loading failures due to faulty CPPC ACPI tables from BIOS Signed-off-by: Perry Yuan <[email protected]> Acked-by: Gautham R. Shenoy <[email protected]> Acked-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/f9793f8451c1832e34cc9dc35f89c653b39cfe38.1718811234.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20cpufreq: amd-pstate: Allow users to write 'default' EPP stringMario Limonciello2-5/+4
The EPP string for 'default' represents what the firmware had configured as the default EPP value but once a user changes EPP to another string they can't reset it back to 'default'. Cache the firmware EPP value and allow the user to write 'default' using this value. Reported-by: Artem S. Tashkinov <[email protected]> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931#c61 Reviewed-by: Perry Yuan <[email protected]> Signed-off-by: Mario Limonciello <[email protected]>
2024-06-20net: dsa: microchip: fix initial port flush problemTristram Ha1-4/+2
The very first flush in any port will flush all learned addresses in all ports. This can be observed by unplugging the cable from one port while additional ports are connected and dumping the fdb entries. This problem is caused by the initially wrong value programmed to the REG_SW_LUE_CTRL_1 register. Setting SW_FLUSH_STP_TABLE and SW_FLUSH_MSTP_TABLE bits does not have an immediate effect. It is when ksz9477_flush_dyn_mac_table() is called then the SW_FLUSH_STP_TABLE bit takes effect and flushes all learned entries. After that call both bits are reset and so the next port flush will not cause such problem again. Fixes: b987e98e50ab ("dsa: add DSA switch driver for Microchip KSZ9477") Signed-off-by: Tristram Ha <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-20wifi: mt76: un-embedd netdev from mt76_devBreno Leitao12-21/+49
Embedding net_device into structures prohibits the usage of flexible arrays in the net_device structure. For more details, see the discussion at [1]. Un-embed the net_devices from struct mt76_dev by converting them into pointers, and allocating them dynamically. Use the leverage alloc_netdev_dummy() to allocate the net_device object at mt76_dma_init(). The free of the device occurs at mt76_dma_cleanup(). Link: https://lore.kernel.org/all/[email protected]/ [1] Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Breno Leitao <[email protected]> Acked-by: Kalle Valo <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-20net: stmmac: unexport stmmac_pltfr_init/exit()Bartosz Golaszewski2-11/+4
These functions are only used within the compilation unit they're defined in so there's no reason to export them. Signed-off-by: Bartosz Golaszewski <[email protected]> Reviewed-by: Simon Horman <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-20nfc: Drop explicit initialization of struct i2c_device_id::driver_data to 0Uwe Kleine-König8-8/+8
These drivers don't use the driver_data member of struct i2c_device_id, so don't explicitly initialize this member. This prepares putting driver_data in an anonymous union which requires either no initialization or named designators. But it's also a nice cleanup on its own. Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-21Merge tag 'drm-xe-fixes-2024-06-20' of ↵Dave Airlie1-2/+2
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Fix for invalid register access Signed-off-by: Dave Airlie <[email protected]> From: Thomas Hellstrom <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ZnPiE4ROqBowa1nS@fedora
2024-06-21Merge tag 'amd-drm-fixes-6.10-2024-06-19' of ↵Dave Airlie16-120/+192
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.10-2024-06-19: amdgpu: - Fix display idle optimization race - Fix GPUVM TLB flush locking scope - IPS fix - GFX 9.4.3 harvesting fix - Runtime pm fix for shared buffers - DCN 3.5.x fixes - USB4 fix - RISC-V clang fix - Silence UBSAN warnings - MES11 fix - PSP 14.0.x fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-21Merge tag 'drm-misc-next-2024-06-20' of ↵Dave Airlie68-716/+1105
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.11: UAPI Changes: - New monochrome TV mode variant Cross-subsystem Changes: - dma heaps: Change slightly the allocation hook prototype Core Changes: Driver Changes: - ivpu: various improvements over firmware handling, clocks, power management, scheduling and logging. - mgag200: Add BMC output, enable polling - panfrost: Enable MT8188 support - tidss: drm_panic support - zynqmp_dp: IRQ cleanups, debugfs DP compliance testing API - bridge: - sii902x: state validation improvements - panel: - edp: Drop legacy panel compatibles - simple-bridge: Switch to devm_drm_bridge_add Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240620-heretic-honored-macaque-b40f8a@houat
2024-06-21Merge tag 'drm-misc-next-2024-06-13' of ↵Dave Airlie134-4081/+2062
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.11: UAPI Changes: Cross-subsystem Changes: Core Changes: - Sprinkle MODULE_DESCRIPTIONS everywhere they are missing - bridge: Remove drm_bridge_chain_mode_fixup - ci: Require a more recent version of mesa, improve farm estup and test generation - mipi-dbi: Remove mipi_dbi_machine_little_endian, make SPI bits per word configurable, support RGB888, and allow pixel formats to be specified in the DT. - mm: Remove drm_mm_replace_node - panic: Allow to dump kmsg to the screen - print: Add a drm prefix to warn level messages too, remove ___drm_dbg, consolidate prefix handling Driver Changes: - sun4i: Rework the blender setup for DE2 - bridges: - bridge-connector: Plumb in the new HDMI helpers - samsung-dsim: Fix timings calculation - tc358767: Plenty of small fixes - panels: - More cleanup of prepare / enable state tracking in drivers - New panel: PrimeView PM070WL4, Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240613-cicada-of-infinite-unity-0955ca@houat
2024-06-21Merge tag 'drm-misc-next-2024-06-06' of ↵Dave Airlie16-552/+1159
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.10: UAPI Changes: Cross-subsystem Changes: - dma-buf: Warn when reserving 0 fence slots, internal API enhancements for heaps Core Changes: Driver Changes: - atmel-hlcdc: Support XLCDC in sam9x7 - msm: Validate registers XML description against schema in CI - v3d: Fix build warning - bridges: - analogix_dp: Various improvements - panels: - New panel: WL-355608-A8 Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240606-vivid-amphibian-jackrabbit-40b1d1@houat
2024-06-21Merge tag 'drm-misc-next-2024-05-30' of ↵Dave Airlie230-7329/+13861
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.11: UAPI Changes: - Deprecate DRM date and return a 0 date in DRM_IOCTL_VERSION Core Changes: - connector: Create a set of helpers to help with HDMI support - fbdev: Create memory manager optimized fbdev emulation - panic: Allow to select fonts, improve drm_fb_dma_get_scanout_buffer Driver Changes: - Remove driver owner assignments - Allow more drivers to compile with COMPILE_TEST - Conversions to drm_edid - ivpu: hardware scheduler support, profiling support, improvements to the platform support layer - mgag200: general reworks and improvements - nouveau: Add NVreg_RegistryDwords command line option - rockchip: Conversion to the hdmi helpers - sun4i: Conversion to the hdmi helpers - vc4: Conversion to the hdmi helpers - v3d: Perf counters improvements - zynqmp: IRQ and debugfs improvements - bridge: - Remove redundant checks on bridge->encoder - panels: - Switch panels from register table initialization to proper code - Now that the panel code tracks the panel state, remove every ad-hoc implementation in the panel drivers - New panels: Lincoln Tech Sol LCD185-101CT, Microtips Technology 13-101HIEBCAF0-C, Microtips Technology MF-103HIEB0GA0, BOE nv110wum-l60, IVO t109nw41 Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240530-hilarious-flat-magpie-5fa186@houat
2024-06-21i2c: ocores: set IACK bit after core is enabledGrygorii Tertychnyi1-1/+1
Setting IACK bit when core is disabled does not clear the "Interrupt Flag" bit in the status register, and the interrupt remains pending. Sometimes it causes failure for the very first message transfer, that is usually a device probe. Hence, set IACK bit after core is enabled to clear pending interrupt. Fixes: 18f98b1e3147 ("[PATCH] i2c: New bus driver for the OpenCores I2C controller") Signed-off-by: Grygorii Tertychnyi <[email protected]> Acked-by: Peter Korsgaard <[email protected]> Cc: [email protected] Signed-off-by: Andi Shyti <[email protected]>
2024-06-20drm/xe: Simplify locking in new_vmaMatthew Brost1-23/+18
Rather than acquiring and dropping the VM / BO dma-resv around xe_vma_create and do the same thing upon adding preempt fences or an error, hold these locks through the entire new_vma() function. v2: - Rebase (CI) Cc: Fei Yang <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Jagmeet Randhawa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20drm/xe: Invert runnable_state / pending enable check and assertMatthew Brost1-2/+2
Rather than checking for pending enable and asserting runnable_state == 1 in sched done handler, invert these. This is more robust code taking action based on the G2H message and asserting KMD tracking state is correct. Suggested-by: John Harrison <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20Input: ims-pcu - switch to using cleanup functionsDmitry Torokhov1-73/+62
Start using __free() and guard() primitives to simplify the code and error handling. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Torokhov <[email protected]>
2024-06-20Input: ims-pcu - use driver core to instantiate device attributesDmitry Torokhov1-25/+28
Instead of manually creating driver-specific device attributes set struct usb_driver->dev_groups pointer to have the driver core do it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Torokhov <[email protected]>
2024-06-20nvme: Atomic write supportAlan Adamson1-0/+52
Add support to set block layer request_queue atomic write limits. The limits will be derived from either the namespace or controller atomic parameters. NVMe atomic-related parameters are grouped into "normal" and "power-fail" (or PF) class of parameter. For atomic write support, only PF parameters are of interest. The "normal" parameters are concerned with racing reads and writes (which also applies to PF). See NVM Command Set Specification Revision 1.0d section 2.1.4 for reference. Whether to use per namespace or controller atomic parameters is decided by NSFEAT bit 1 - see Figure 97: Identify – Identify Namespace Data Structure, NVM Command Set. NVMe namespaces may define an atomic boundary, whereby no atomic guarantees are provided for a write which straddles this per-lba space boundary. The block layer merging policy is such that no merges may occur in which the resultant request would straddle such a boundary. Unlike SCSI, NVMe specifies no granularity or alignment rules, apart from atomic boundary rule. In addition, again unlike SCSI, there is no dedicated atomic write command - a write which adheres to the atomic size limit and boundary is implicitly atomic. If NSFEAT bit 1 is set, the following parameters are of interest: - NAWUPF (Namespace Atomic Write Unit Power Fail) - NABSPF (Namespace Atomic Boundary Size Power Fail) - NABO (Namespace Atomic Boundary Offset) and we set request_queue limits as follows: - atomic_write_unit_max = rounddown_pow_of_two(NAWUPF) - atomic_write_max_bytes = NAWUPF - atomic_write_boundary = NABSPF If in the unlikely scenario that NABO is non-zero, then atomic writes will not be supported at all as dealing with this adds extra complexity. This policy may change in future. In all cases, atomic_write_unit_min is set to the logical block size. If NSFEAT bit 1 is unset, the following parameter is of interest: - AWUPF (Atomic Write Unit Power Fail) and we set request_queue limits as follows: - atomic_write_unit_max = rounddown_pow_of_two(AWUPF) - atomic_write_max_bytes = AWUPF - atomic_write_boundary = 0 A new function, nvme_valid_atomic_write(), is also called from submission path to verify that a request has been submitted to the driver will actually be executed atomically. As mentioned, there is no dedicated NVMe atomic write command (which may error for a command which exceeds the controller atomic write limits). Note on NABSPF: There seems to be some vagueness in the spec as to whether NABSPF applies for NSFEAT bit 1 being unset. Figure 97 does not explicitly mention NABSPF and how it is affected by bit 1. However Figure 4 does tell to check Figure 97 for info about per-namespace parameters, which NABSPF is, so it is implied. However currently nvme_update_disk_info() does check namespace parameter NABO regardless of this bit. Signed-off-by: Alan Adamson <[email protected]> Reviewed-by: Keith Busch <[email protected]> Reviewed-by: Martin K. Petersen <[email protected]> jpg: total rewrite Signed-off-by: John Garry <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jens Axboe <[email protected]>
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