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2023-12-06drm/amd/display: Add writeback enable field (wb_enabled)Alex Hung2-0/+9
[WHAT] Add a new field to keep track whether a crtc is previously writeback-enabled. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix writeback_info is not removedAlex Hung1-3/+4
[WHY] Counter j was not updated to present the num of writeback_info when writeback pipes are removed. [HOW] update j (num of writeback info) under the correct condition. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Validate hw_points_num before using itAlex Hung1-0/+3
[WHAT] hw_points_num is 0 before ogam LUT is programmed; however, function "dwb3_program_ogam_pwl" assumes hw_points_num is always greater than 0, i.e. substracting it by 1 as an array index. [HOW] Check hw_points_num is not equal to 0 before using it. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix writeback_info never got updatedAlex Hung1-9/+4
[WHY] wb_enabled field is set to false before it is used, and the following code will never be executed. [HOW] Setting wb_enable to false after all removal work is completed. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Add writeback enable/disable in dcAlex Hung2-0/+37
[WHAT] The enable and disable writeback calls need to be included in the coressponding functions in dc_stream. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Hande writeback request from userspaceAlex Hung2-0/+162
[WHAT] Handle writeback requests and fill in the required information for DWB programming and setup. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Create fake sink and stream for writeback connectorHarry Wentland1-11/+22
[WHAT] Writeback connectors don't have a physical sink but DC still needs a sink to function. Create a fake sink and stream for writeback connectors Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Create amdgpu_dm_wb_connectorHarry Wentland4-8/+24
[WHY] We need to track the dc_link and it would get confusing if re-using the amdgpu_dm_connector. [HOW] Creating new amdgpu_dm_wb_connector. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Check writeback connectors in create_validate_stream_for_sinkAlex Hung1-1/+4
[WHY & HOW] This is to check connector type to avoid unhandled null pointer for writeback connectors. Tested-by: Daniel Wheeler <[email protected]> Fixes: 60e034f28600 ("drm/amd/display: Revert "drm/amd/display: Use drm_connector in create_validate_stream_for_sink"") Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Use drm_connector in create_stream_for_sinkHarry Wentland1-28/+37
[WHAT] We need to use this function for both amdgpu_dm_connectors and drm_writeback_connectors. Modify it to operate on a drm_connector as a common base. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Return drm_connector from find_first_crtc_matching_connectorHarry Wentland3-5/+9
[WHY] We will be dealing with two types of connector: amdgpu_dm_connector and drm_writeback_connector. [HOW] We want to find both and then cast to the appriopriate type afterwards. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Skip writeback connector when we get amdgpu_dm_connectorHarry Wentland3-11/+76
[WHY] Writeback connectors are based on a different object: drm_writeback_connector, and are therefore different from amdgpu_dm_connector. We need to be careful to ensure code designed for amdgpu_dm_connector doesn't inadvertently try to operate on a drm_writeback_connector. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Initialize writeback connectorAlex Hung4-2/+265
[WHAT] Create a drm_writeback_connector when connector signal equals SIGNAL_TYPE_VIRTUAL. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Create one virtual connector in DCHarry Wentland2-3/+11
[WHAT] Prepare a virtual connector for writeback. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Skip entire amdgpu_dm build if !CONFIG_DRM_AMD_DCHarry Wentland1-5/+8
[WHY] Previously this only excluded build for a few amdgpu_dm binaries which makes no sense. [HOW] Wrap the entire Makefile in "ifneq ($(CONFIG_DRM_AMD_DC),)" Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Avoid virtual stream encoder if not explicitly requestedAlex Hung1-1/+4
Virtual stream encoder should not be a free match for thunderbolt or usbc, and thus should be avoided. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: add support for DTO genarated dscclkWenjing Liu3-1/+55
Current implementation will choose to use refclk as dscclk. This is not recommended by hardware team as refclk is a fixed value which could cause unnecessary power consumption or it could be not enough for large DSC timings. So we are adding new interfaces so we could switch to use dynamically generated DSCCLK by DTO. So DSCCLK is programmable based on current pixel clock and dispclk. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix Replay Desync Error IRQ handlerDennis Chan1-6/+6
In previous case, Replay didn't identify the IRQ type, This commit fixes the issues for the interrupt. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Robin Chen <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dennis Chan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Add dml2 copy functionsDillon Varone3-12/+36
Add function to handle deep copying dml2 context. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: add MPC MCM 1D LUT clock gating programmingYihan Zhu2-2/+3
Missing clock gating programming blocks memory power on from boot up. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Add monitor patch for specific eDPIvan Lipski1-0/+6
[WHY] Some eDP panels's ext caps don't write initial value cause the value of dpcd_addr(0x317) is random. It means that sometimes the eDP will clarify it is OLED, miniLED...etc cause the backlight control interface is incorrect. [HOW] Add a new panel patch to remove sink ext caps(HDR,OLED...etc) Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix disable_otg_wa logicNicholas Susanto1-8/+0
[Why] When switching to another HDMI mode, we are unnecesarilly disabling/enabling FIFO causing both HPO and DIG registers to be set at the same time when only HPO is supposed to be set. This can lead to a system hang the next time we change refresh rates as there are cases when we don't disable OTG/FIFO but FIFO is enabled when it isn't supposed to be. [How] Removing the enable/disable FIFO entirely. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: keep domain24 power on if eDP not existCharlene Liu1-2/+20
This is w/a: we need to keep domain 24 power up in driver side, and let dmubfw handle it for S0i3. For last display unplugged, if OTG in PG, no interrupt call back coming. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Added delay to DPM logRelja Vojvodic1-10/+16
HW registers were being read to quickly, causing incorrect values to be logged after a clock frequency was changed Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Pass debug watermarks through to DCN35 DML2Nicholas Kazlauskas1-0/+19
[Why] The DC debug options currently do not function for dynamically adjusting our watermarks. [How] Hook them up before passing them to DML2. Also make sure we're using dc->bb_overrides since dc->debug isn't populated during dc_construct. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Michael Strauss <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: revert removing otg toggle w/a back when no active displayCharlene Liu2-9/+7
w/a use case: - dual display, compliance, toggling between the displays - switching between 120Hz 420 -> 144Hz 444 and vice versa - switching between 144Hz -> 60Hz TMDS or vice versa It'd typically involve TMDS in some capacity since that's the only link signal we leave the OTG running but DIO/PHY off you can hit this in cases where you have multiple displays as well it syncs with the first active OTG, so if you had OTG[0] mapped and FIFO off you'd hit it even if OTG[1] was mapped and had FIFO Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Update BIOS FW info table revisionChris Park1-0/+1
[Why] BIOS FW info version 3.5 is introduced to support new ASICs, but it's content is currently same as 3.4. [How] Include minor version 5 in parsing to enable support. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Skip DPIA-specific DP LL automation flag for non-DPIA linksGeorge Shen3-5/+13
[Why] The is_automated flag logic only applies to USB4 DPIA links during DP LL compliance test automation. The flag should not be set for non-DPIA cases. [How] Add check for DPIA link endpoint type before setting the flag. Also, rename is_automated to skip_fallback_on_link_loss for clarity. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix null pointerJohnson Chen1-0/+2
Add guard for NULL pointer access Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Johnson Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Use channel_width = 2 for vram table 3.0Alvin Lee1-1/+7
VBIOS has suggested to use channel_width=2 for any ASIC that uses vram info 3.0. This is because channel_width in the vram table no longer represents the memory width Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Samson Tam <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Fix MST PBN/X.Y value calculationsIlya Bakoulin1-5/+8
Changing PBN calculation to be more in line with spec. We don't need to inflate PBN_NATIVE value by the 1.006 margin, since that is already taken care of in the get_pbn_per_slot function. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: insert drv-pmfw log + rollback to new contextCharlene Liu2-23/+47
Rollback to new context for active display: this was previous tested sequence. Avoid to do OTG master toggle is no active display at all, this w/a was for fifo err. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Increase scratch buffer sizeJosip Pavic1-1/+1
[Why] Larger data blocks are expected to be transferred between driver and FW in the future. [How] Embiggen the scratch buffer to a cromulent size. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Josip Pavic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Change dither policy for 10bpc to roundKrunoslav Kovac1-1/+3
We use spatial dither by default for all output bpc (6/8/10). While it makes some sense for FP16, for ARGB2101010 surfaces it makes little sense as even if we skip color pipeline to preserve bit accuracy, spatial dither adds random noise so a few percent pixels are 1 bit off. This commit chages the 10bpc out dither policy to rounding. Also, in Polaris/Vega times, policy used to be round for 10bpc out; it looks like it got inadvertently changed for Navi. Difference is only detectable with capture cards. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Krunoslav Kovac <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Pass pwrseq inst for backlight and ABMLewis Huang14-53/+119
[Why] OTG inst and pwrseq inst mapping is not align therefore we cannot use otg_inst as pwrseq inst to get DCIO register. [How] 1. Pass the correct pwrseq instance to dmub when set abm pipe. 2. LVTMA control index change from panel_inst to pwrseq_inst. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Phil Hsieh <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Add missing dcn35 RCO registersDaniel Miess3-2/+143
[Why] Some registers needed for root clock gating in dcn35 are not defined in the dccg header. [How] Add the needed registers and temporarily disable some register writes that are now taking place successfully until the registers can be properly enabled. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amdkfd: Use partial migrations/mapping for GPU/CPU page faults in SVMXiaogang Chen4-159/+176
This patch implements partial migration/mapping for gpu/cpu page faults in SVM according to migration granularity(default 2MB). A svm range may include pages from both system ram and vram of one gpu now. These chagnes are expected to improve migration performance and reduce mmu callback and TLB flush workloads. Signed-off-by: Xiaogang Chen <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Only enumerate top local sink as DP2 outputMichael Strauss1-0/+9
[WHY] Many DCN generations only have two HPO link encoders and therefore only support driving a max of two DP2 PHYs. DP2 MST hubs currently can not pass 3x display validation as each downstream sink is enumerated as separate DP2 output. [HOW] Count MST hubs once by treating only 1st remote sink in topology as an encoder. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Add ODM check during pipe split/merge validationRelja Vojvodic3-0/+31
[why] When querying DML for a vlevel after pipes have been split or merged the ODM policy would revert to a default policy, which could cause the query to use the incorrect ODM status. In this case ODM 2to1 was validated, but the last DML query would assume no ODM and return the incorrect vlevel. [how] Added ODM check to apply the correct ODM policy before querying DML. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: initialize all the dpm level's stutter latencyCharlene Liu1-1/+3
Fix issue when override level bigger than default. Levels 5, 6, and 7 had zero stutter latency, this is because override level being initialized after stutter latency inits. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Syed Hassan <[email protected]> Reviewed-by: Allen Pan <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Optimize fast validation casesAlvin Lee2-12/+19
Optimize fast validation cases to only validate the highest voltage level. This works because during fast validation we only care if the mode can be supported or not (at any vlevel). Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/amdgpu: Move vcn4 fw_shared init to a single functionBokun Zhang1-19/+26
- Move VCN4's fw_shared initialization to a separated function. This way, the function can be reused at different locations. Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amdgpu: disable MCBP by defaultJiadong Zhu1-4/+0
Disable MCBP(mid command buffer preemption) by default as old Mesa hangs with it. We shall not enable the feature that breaks old usermode driver. Fixes: 50a7c8765ca6 ("drm/amdgpu: enable mcbp by default on gfx9") Signed-off-by: Jiadong Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-12-05Merge tag 'amd-drm-next-6.8-2023-12-01' of ↵Dave Airlie220-1524/+3364
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.8-2023-12-01: amdgpu: - Add new 64 bit sequence number infrastructure. This will ultimately be used for user queue synchronization. - GPUVM updates - Misc code cleanups - RAS updates - DCN 3.5 updates - Rework PCIe link speed handling - Document GPU reset types - DMUB fixes - eDP fixes - NBIO 7.9 updates - NBIO 7.11 updates - SubVP updates - DCN 3.1.4 fixes - ABM fixes - AGP aperture fix - DCN 3.1.5 fix - Fix some potential error path memory leaks - Enable PCIe PMEs - Add XGMI, PCIe state dumping for aqua vanjaram - GFX11 golden register updates - Misc display fixes amdkfd: - Migrate TLB flushing logic to amdgpu - Trap handler fixes - Fix restore workers handling on suspend and reset - Fix possible memory leak in pqm_uninit() radeon: - Fix some possible overflows in command buffer checking - Check for errors in ring_lock From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2023-11-30drm/amd/display: Fix NULL pointer dereference at hibernateMario Limonciello1-2/+2
During hibernate sequence the source context might not have a clk_mgr. So don't use it to look for DML2 support. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2980 Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/radeon: check return value of radeon_ring_lock()Nikita Zhandarovich1-0/+4
In the unlikely event of radeon_ring_lock() failing, its errno return value should be processed. This patch checks said return value and prints a debug message in case of an error. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 48c0c902e2e6 ("drm/radeon/kms: add support for CP setup on SI") Signed-off-by: Nikita Zhandarovich <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/radeon/r100: Fix integer overflow issues in r100_cs_track_check()Nikita Zhandarovich1-2/+2
It may be possible, albeit unlikely, to encounter integer overflow during the multiplication of several unsigned int variables, the result being assigned to a variable 'size' of wider type. Prevent this potential behaviour by converting one of the multiples to unsigned long. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 0242f74d29df ("drm/radeon: clean up CS functions in r100.c") Signed-off-by: Nikita Zhandarovich <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg()Nikita Zhandarovich1-2/+2
While improbable, there may be a chance of hitting integer overflow when the result of radeon_get_ib_value() gets shifted left. Avoid it by casting one of the operands to larger data type (u64). Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes") Signed-off-by: Nikita Zhandarovich <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/amdgpu: enable mca debug mode on APU by defaultYang Wang1-1/+2
enable MCA debug mode on APU device by default. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/amdgpu: distinguish rlc fw for different SKULikun Gao1-1/+6
For some SKU, rlc firmware should use different one compared with the normal rlc firmware. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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