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2021-04-20drm/amdkfd: add svm_bo reference for eviction fenceAlex Sierra3-5/+10
[why] As part of the SVM functionality, the eviction mechanism used for SVM_BOs is different. This mechanism uses one eviction fence per prange, instead of one fence per kfd_process. [how] A svm_bo reference to amdgpu_amdkfd_fence to allow differentiate between SVM_BO or regular BO evictions. This also include modifications to set the reference at the fence creation call. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: SVM API call to restore page tablesAlex Sierra1-5/+15
Use SVM API to restore page tables when retry fault and compute context are enabled. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: page table restore through svm APIFelix Kuehling2-0/+61
Page table restore implementation in SVM API. This is called from the fault handler at amdgpu_vm. To update page tables through the page fault retry IH. Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: enable 48-bit IH timestamp counterAlex Sierra1-0/+1
By default this timestamp is 32 bit counter. It gets overflowed in around 10 minutes. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: invalidate tables on page retry faultFelix Kuehling3-17/+70
GPU page tables are invalidated by unmapping prange directly at the mmu notifier, when page fault retry is enabled through amdgpu_noretry global parameter. The restore page table is performed at the page fault handler. If xnack is on, we update GPU mappings after migration to avoid unnecessary GPUVM faults. Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: HMM migrate vram to ramFelix Kuehling4-13/+429
If CPU page fault happens, HMM pgmap_ops callback migrate_to_ram start migrate memory from vram to ram in steps: 1. migrate_vma_pages get vram pages, and notify HMM to invalidate the pages, HMM interval notifier callback evict process queues 2. Allocate system memory pages 3. Use svm copy memory to migrate data from vram to ram 4. migrate_vma_pages copy pages structure from vram pages to ram pages 5. Return VM_FAULT_SIGBUS if migration failed, to notify application 6. migrate_vma_finalize put vram pages, page_free callback free vram pages and vram nodes 7. Restore work wait for migration is finished, then update GPU page table mapping to system memory, and resume process queues Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: HMM migrate ram to vramFelix Kuehling4-13/+502
Register svm range with same address and size but perferred_location is changed from CPU to GPU or from GPU to CPU, trigger migration the svm range from ram to vram or from vram to ram. If svm range prefetch location is GPU with flags KFD_IOCTL_SVM_FLAG_HOST_ACCESS, validate the svm range on ram first, then migrate it from ram to vram. After migrating to vram is done, CPU access will have cpu page fault, page fault handler migrate it back to ram and resume cpu access. Migration steps: 1. migrate_vma_pages get svm range ram pages, notify the interval is invalidated and unmap from CPU page table, HMM interval notifier callback evict process queues 2. Allocate new pages in vram using TTM 3. Use svm copy memory to sdma copy data from ram to vram 4. migrate_vma_pages copy ram pages structure to vram pages structure 5. migrate_vma_finalize put ram pages to free ram pages and memory 6. Restore work wait for migration is finished, then update GPUs page table mapping to new vram pages, resume process queues If migrate_vma_setup failed to collect all ram pages of range, retry 3 times until success to start migration. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: copy memory through gart tablePhilip Yang2-0/+177
Use sdma linear copy to migrate data between ram and vram. The sdma linear copy command uses kernel buffer function queue to access system memory through gart table. Use reserved gart table window 0 to map system page address, and vram page address is direct mapping. Use the same kernel buffer function to fill in gart table mapping, so this is serialized with memory copy by sdma job submit. We only need wait for the last memory copy sdma fence for larger buffer migration. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: support xgmi same hive mappingPhilip Yang1-19/+75
amdgpu_gmc_get_vm_pte use bo_va->is_xgmi same hive information to set pte flags to update GPU mapping. Add local structure variable bo_va, and update bo_va.is_xgmi, pass it to mapping->bo_va while mapping to GPU. Assuming xgmi pstate is hi after boot. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: validate vram svm range from TTMFelix Kuehling2-7/+309
If svm range perfetch location is not zero, use TTM to alloc amdgpu_bo vram nodes to validate svm range, then map vram nodes to GPUs. Use offset to sub allocate from the same amdgpu_bo to handle overlap vram range while adding new range or unmapping range. svm_bo has ref count to trace the shared ranges. If all ranges of shared amdgpu_bo are migrated to ram, ref count becomes 0, then amdgpu_bo is released, all ranges svm_bo is set to NULL. To migrate range from ram back to vram, allocate the same amdgpu_bo with previous offset if the range has svm_bo. If prange migrate to VRAM, no CPU mapping exist, then process exit will not have unmap callback for this prange to free prange and svm bo. Free outstanding pranges from svms list before process is freed in svm_range_list_fini. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: set memory limit to avoid OOM with HMM enabledPhilip Yang3-0/+14
HMM migration alloc sizeof(struct page) on system memory for each VRAM page, it is 1GB system memory reserved for 64GB VRAM. To avoid application OOM, increase system memory used size based on VRAM size of all GPUs, then application alloc memory will fail if system memory usage reach the limit. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: register HMM device private zonePhilip Yang6-1/+164
Register vram memory as MEMORY_DEVICE_PRIVATE type resource, to allocate vram backing pages for page migration. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: add ioctl to configure and query xnack retriesAlex Sierra1-0/+28
Xnack retries are used for page fault recovery. Some AMD chip families support continuously retry while page table entries are invalid. The driver must handle the page fault interrupt and fill in a valid entry for the GPU to continue. This ioctl allows to enable/disable XNACK retries per KFD process. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: add xnack enabled flag to kfd_processAlex Sierra3-2/+68
XNACK mode controls the SQ RETRY_DISABLE setting that determines, whether recoverable page faults can be supported on GFXv9 hardware. Only on Aldebaran we can support different processes running with different XNACK modes. On older chips all processes must use the same RETRY_DISABLE setting. However, processes not relying on recoverable page faults can work with RETRY enabled. This means XNACK off is always available as a fallback so we can use the same mode on all GPUs in a process. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: Enable retry faults unconditionally on AldebaranFelix Kuehling3-5/+12
This is needed to allow per-process XNACK mode selection in the SQ when booting with XNACK off by default. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Tested-by: Alex Sierra <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: svm range eviction and restoreFelix Kuehling4-0/+140
HMM interval notifier callback notify CPU page table will be updated, stop process queues if the updated address belongs to svm range registered in process svms objects tree. Scheduled restore work to update GPU page table using new pages address in the updated svm range. The restore worker flushes any deferred work to make sure it restores an up-to-date svm_range_list. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: map svm range to GPUsFelix Kuehling4-10/+478
Use amdgpu_vm_bo_update_mapping to update GPU page table to map or unmap svm range system memory pages address to GPUs. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: export vm update mapping interfacePhilip Yang2-9/+20
It will be used by kfd to map svm range to GPU, because svm range does not have amdgpu_bo and bo_va, cannot use amdgpu_bo_update interface, use amdgpu vm update interface directly. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: deregister svm rangePhilip Yang3-1/+311
When application explicitly call unmap or unmap from mmput when application exit, driver will receive MMU_NOTIFY_UNMAP event to remove svm range from process svms object tree and list first, unmap from GPUs (in the following patch). Split the svm ranges to handle partial unmapping of svm ranges. To avoid deadlocks, updating MMU notifiers, range lists and interval trees is done in a deferred worker. New child ranges are attached to their parent range's child_list until the worker can update the svm_range_list. svm_range_set_attr flushes deferred work and takes the mmap_write_lock to guarantee that it has an up-to-date svm_range_list. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: validate svm range system memoryPhilip Yang2-1/+133
Use HMM to get system memory pages address, which will be used to map to GPUs or migrate to vram. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: support larger svm range allocationPhilip Yang1-1/+4
For larger range allocation, if hmm_range_fault return -EBUSY, set retry timeout based on 1 second for every 512MB, this is safe timeout value. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: add common HMM get pages functionPhilip Yang3-66/+100
Move the HMM get pages function from amdgpu_ttm and to amdgpu_mn. This common function will be used by new svm APIs. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: add svm ioctl GET_ATTR opPhilip Yang1-0/+164
Get the intersection of attributes over all memory in the given range Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: register svm rangePhilip Yang6-1/+850
svm range structure stores the range start address, size, attributes, flags, prefetch location and gpu bitmap which indicates which GPU this range maps to. Same virtual address is shared by CPU and GPUs. Process has svm range list which uses both interval tree and list to store all svm ranges registered by the process. Interval tree is used by GPU vm fault handler and CPU page fault handler to get svm range structure from the specific address. List is used to scan all ranges in eviction restore work. No overlap range interval [start, last] exist in svms object interval tree. If process registers new range which has overlap with old range, the old range split into 2 ranges depending on the overlap happens at head or tail part of old range. Apply attributes preferred location, prefetch location, mapping flags, migration granularity to svm range, store mapping gpu index into bitmap. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: add svm ioctl APIPhilip Yang4-0/+19
Add svm (shared virtual memory) ioctl data structure and API definition. The svm ioctl API is designed to be extensible in the future. All operations are provided by a single IOCTL to preserve ioctl number space. The arguments structure ends with a variable size array of attributes that can be used to set or get one or multiple attributes. Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: helper to convert gpu id and idxAlex Sierra2-0/+21
svm range uses gpu bitmap to store which GPU svm range maps to. Application pass driver gpu id to specify GPU, the helper is needed to convert gpu id to gpu bitmap idx. Access through kfd_process_device pointers array from kfd_process. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: Remove verify_access shortcut for KFD BOsFelix Kuehling1-7/+0
This shortcut is no longer needed with access managed properly by KFD. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: Allow access for mmapping KFD BOsFelix Kuehling4-8/+30
DRM render node file handles are used for CPU mapping of BOs using mmap by the Thunk. It uses the DRM render node of the GPU where the BO was allocated. DRM allows mmap access automatically when it creates a GEM handle for a BO. KFD BOs don't have GEM handles, so KFD needs to manage access manually. Use drm_vma_node_allow to allow user mode to mmap BOs allocated with kfd_ioctl_alloc_memory_of_gpu through the DRM render node that was used in the kfd_ioctl_acquire_vm call for the same GPU. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdkfd: Use drm_priv to pass VM from KFD to amdgpuFelix Kuehling6-55/+67
amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu needs the drm_priv to allow mmap to access the BO through the corresponding file descriptor. The VM can also be extracted from drm_priv, so drm_priv can replace the vm parameter in the kfd2kgd interface. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu/gmc9: remove dummy read workaround for newer chipsAlex Deucher1-2/+4
Aldebaran has a hw fix so no longer requires the workaround. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: Add mem sync flag for IB allocated by SAJinzhou Su1-0/+2
The buffer of SA bo will be used by many cases. So it's better to invalidate the cache of indirect buffer allocated by SA before commit the IB. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: Fix SDMA RAS error reporting on AldebaranMukul Joshi1-7/+28
Fix the following issues with SDMA RAS error reporting: 1. Read the EDC_COUNTER2 register also to fetch error counts for all sub-blocks in SDMA. 2. SDMA RAS on Aldebaran suports single-bit uncorrectable errors only. So, report error count in UE count instead of CE count. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-By: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: Reset RAS error count and status regsMukul Joshi1-0/+6
Reset the RAS error count and error status registers after reading to prevent over reporting error counts on Aldebaran. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-By: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"Oak Zeng4-40/+10
This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: 3.2.132Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: [FW Promotion] Release 0.0.62Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: add helper for enabling mst stream featuresBing Guo3-11/+44
[Why] Some MST devices uses different method to enable mst specific stream features. [How] Add dm_helpers_mst_enable_stream features. This can be modified later when we are ready to implement those features. Signed-off-by: Bing Guo <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Report Proper Quantization Range in AVI InfoframeDillon Varone1-14/+19
[Why?] When a monitor does not set both QS and QY bits, DC does not set Q0, Q1, QY0 and QY1 bits in AVI infoframe. Setting RGB bits should be separate from setting YCC bits. [How?] Separate logic for setting RGB and YCC quantization range bits in the AVI infoframe. Signed-off-by: Dillon Varone <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Fix call to pass bpp in 16ths of a bitDillon Varone1-2/+2
[Why & How?] Call to dc_dsc_compute_bandwidth_range should have min and max bpp in 16ths of a bit. Multiply min and max bpp from policy. Signed-off-by: Dillon Varone <[email protected]> Reviewed-by: Eryk Brol <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Fixed typo in function name.David Galiffi1-2/+2
[How & Why] Changed "prsent" to "present". Signed-off-by: David Galiffi <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Always poll for rxstatus in authenticateNicholas Kazlauskas2-4/+0
[Why] Requirement from the spec - we shouldn't be potentially exiting out early based on encryption status. [How] Drop the calls from HDCP1 and HDCP2 execution that exit out early based on link encryption status. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Add link rate optimization logs for ILRMichael Strauss3-2/+12
[Why&How] Add logs to verify ILR optimization behaviour on boot Signed-off-by: Michael Strauss <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Unconditionally clear training pattern set after ltWesley Chalmers1-5/+4
[WHY] While Link Training is being performed, and the LTTPRs are in Non-LTTPR or LTTPR Transparent mode, any DPCD registers besides those used for Link Training are not to be accessed. The spec defines the link training registers as DP_TRAINING_PATTERN_SET (102h) to DP_TRAINING_LANE3_SET (106h), and DP_LANE0_1_STATUS (202h) to DP_ADJUST_REQUEST_LANE2_3 (207h). [HOW] Move the current write to DPCD Address DP_LINK_TRAINING_PATTERN_SET out of its conditional block. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Fix FreeSync when RGB MPO in useAric Cyr2-1/+4
[WHY] We should skip programming manual trigger on non-primary planes when MPO is enabled. [HOW] Implement an explicit mechanism for skipping manual trigger programming for planes that shouldn't cause the frame to end. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Acked-by: Krunoslav Kovac <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: treat memory as a single-channel for asymmetric memory v2Hugo Hu2-2/+48
Previous change had been reverted since it caused hang. Remake change to avoid defect. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Fixes: b8720ed0b87d32 ("drm/amd/display: System black screen hangs on driver load") Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: removed unused function dc_link_reallocate_mst_payload.Robin Singh2-45/+0
[Why] Found that dc_link_reallocate_mst_payload is not used anymore in any of the use case scenario. [How] removed dc_link_reallocate_mst_payload function definition and declaration. Signed-off-by: Robin Singh <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: disable seamless boot for external DPAnthony Wang1-4/+3
[Why] Primary feature use case is with eDP panels. [How] Fail seamless boot validation if display is not an eDP panel. Signed-off-by: Anthony Wang <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: add handling for hdcp2 rx id list validationDingchen (David) Zhang1-0/+2
[why] the current implementation of hdcp2 rx id list validation does not have handler/checker for invalid message status, e.g. HMAC, the V parameter calculated from PSP not matching the V prime from Rx. [how] return a generic FAILURE for any message status not SUCCESS or REVOKED. Signed-off-by: Dingchen (David) Zhang <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: update hdcp display using correct CP type.Dingchen (David) Zhang1-1/+7
[why] currently we enforce to update hdcp display using TYPE0, but there is case that connector CP type prop be TYPE1 instead of type0. [how] using the drm prop of CP type of the connector as input argument. Signed-off-by: Dingchen (David) Zhang <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amd/display: Add DSC check to seamless boot validationAnthony Wang1-0/+4
[Why & How] We want to immediately fail seamless boot validation if DSC is active, as VBIOS currently does not support DSC timings. Add a check for the relevant flag in dc_validate_seamless_boot_timing. Signed-off-by: Anthony Wang <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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