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2023-03-13drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functionsVinod Polimera1-4/+6
Use atomic variants for encoder callback functions such that certain states like self-refresh can be accessed as part of enable/disable sequence. Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524738/ Link: https://lore.kernel.org/r/1677774797-31063-12-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/dp: use the eDP bridge ops to validate eDP modesVinod Polimera2-9/+33
The eDP and DP interfaces shared the bridge operations and the eDP specific changes were implemented under is_edp check. To add psr support for eDP, we started using a new set of eDP bridge ops. We are moving the eDP specific code in the dp_bridge_mode_valid function to a new eDP function, edp_bridge_mode_valid under the eDP bridge ops. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524736/ Link: https://lore.kernel.org/r/1677774797-31063-11-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/dp: Add basic PSR support for eDPVinod Polimera11-1/+411
Add support for basic panel self refresh (PSR) feature for eDP. Add a new interface to set PSR state in the sink from DPU. Program the eDP controller to issue PSR enter and exit SDP to the sink. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524734/ Link: https://lore.kernel.org/r/1677774797-31063-10-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/dp: use atomic callbacks for DP bridge opsVinod Polimera3-9/+15
Use atomic variants for DP bridge callback functions so that the atomic state can be accessed in the interface drivers. The atomic state will help the driver find out if the display is in self refresh state. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/524731/ Link: https://lore.kernel.org/r/1677774797-31063-9-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/disp/dpu: reset the datapath after timing engine disableVinod Polimera1-0/+1
Reset the datapath after disabling the timing gen, such that it can start on a clean slate when the intf is enabled back. This was a recommended sequence from the DPU HW programming guide. Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524729/ Link: https://lore.kernel.org/r/1677774797-31063-8-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabledVinod Polimera1-0/+21
There can be a race between timing gen disable and vblank irq. The wait post timing gen disable may return early but intf disable sequence might not be completed. Ensure that, intf status is disabled before we retire the function. Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524727/ Link: https://lore.kernel.org/r/1677774797-31063-7-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/disp/dpu: get timing engine status from intf status registerVinod Polimera3-7/+16
Recommended way of reading the interface timing gen status is via status register. Timing gen status register will give a reliable status of the interface especially during ON/OFF transitions. This support was added from DPU version 5.0.0. Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524724/ Link: https://lore.kernel.org/r/1677774797-31063-6-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/msm/disp/dpu: check for crtc enable rather than crtc active to release ↵Vinod Polimera1-1/+1
shared resources According to KMS documentation, The driver must not release any shared resources if active is set to false but enable still true. Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset") Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524726/ Link: https://lore.kernel.org/r/1677774797-31063-5-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/bridge: add psr support for panel bridge callbacksVinod Polimera1-0/+48
This change will handle the psr entry exit cases in the panel bridge atomic callback functions. For example, the panel power should not turn off if the panel is entering psr. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Patchwork: https://patchwork.freedesktop.org/patch/524721/ Link: https://lore.kernel.org/r/1677774797-31063-4-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm/bridge: use atomic enable/disable callbacks for panel bridgeVinod Polimera1-8/+12
Use atomic variants for panel bridge callback functions such that certain states like self-refresh can be accessed as part of enable/disable sequence. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Patchwork: https://patchwork.freedesktop.org/patch/524720/ Link: https://lore.kernel.org/r/1677774797-31063-3-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-03-13drm: add helper functions to retrieve old and new crtcVinod Polimera1-0/+60
Add new helper functions, drm_atomic_get_old_crtc_for_encoder and drm_atomic_get_new_crtc_for_encoder to retrieve the corresponding crtc for the encoder. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Patchwork: https://patchwork.freedesktop.org/patch/524718/ Link: https://lore.kernel.org/r/1677774797-31063-2-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()Dmitry Baryshkov1-9/+6
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes") it sets the flag late, after all the qos functions have updated QoS programming. Move the flag update back to the place where it happened before the mentioned commit to let the pipe be programmed according to its current RT/non-RT state. Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/516239/ Link: https://lore.kernel.org/r/20221229191856.3508092-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/dpu: correct the UBWC version on sm6115Dmitry Baryshkov1-1/+1
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0. Change the catalog entry accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514337/ Link: https://lore.kernel.org/r/20221207142833.204193-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_formatDmitry Baryshkov1-1/+5
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514336/ Link: https://lore.kernel.org/r/20221207142833.204193-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/hdmi: make hdmi_phy_8960 OF clk providerDmitry Baryshkov1-5/+10
On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are preparing to convert the MSM8960 to use DT clocks properties (rather than global clock names), register the OF clock provider. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519211/ Link: https://lore.kernel.org/r/20230119132219.2479775-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/hdmi: switch hdmi_pll_8960 to use parent_dataDmitry Baryshkov1-3/+3
Replace parent_names usage with parent_data. Note, that this makes the PLL default to board's `pxo_board' clock rather than just `pxo' clock, as we are on a way to deprecate the global cxo/pxo clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519210/ Link: https://lore.kernel.org/r/20230119132219.2479775-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/dsi: properly handle the case of empty OPP table in ↵Dmitry Baryshkov1-9/+10
dsi_mgr_bridge_mode_valid It was left unnoticed during the review that even if there is no OPP table in device tree, one will be created by a call to the function devm_pm_opp_set_clkname(). This leads to dsi_mgr_bridge_mode_valid() rejecting all modes if DT contains no OPP table for the DSI host. Rework dsi_mgr_bridge_mode_valid() to handle this case by actually checking that the table is populated with frequency entries before returning an error. Fixes: 8328041b8c82 ("drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/520076/ Link: https://lore.kernel.org/r/20230124203600.3488766-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-26drm/msm/dpu: Add DSC hardware blocks to register snapshotMarijn Suijten1-0/+5
Add missing DSC hardware block register ranges to the snapshot utility to include them in dmesg (on MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) and the kms debugfs file. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/520175/ Link: https://lore.kernel.org/r/20230125101412.216924-1-marijn.suijten@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/mdp5: Add check for kzallocJiasheng Jiang1-1/+4
As kzalloc may fail and return NULL pointer, it should be better to check the return value in order to avoid the NULL pointer dereference. Fixes: 1cff7440a86e ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514154/ Link: https://lore.kernel.org/r/20221206074819.18134-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: Add check for pstatesJiasheng Jiang1-0/+2
As kzalloc may fail and return NULL pointer, it should be better to check pstates in order to avoid the NULL pointer dereference. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514160/ Link: https://lore.kernel.org/r/20221206080236.43687-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: Add check for cstateJiasheng Jiang1-1/+4
As kzalloc may fail and return NULL pointer, it should be better to check cstate in order to avoid the NULL pointer dereference in __drm_atomic_helper_crtc_reset. Fixes: 1cff7440a86e ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514163/ Link: https://lore.kernel.org/r/20221206080517.43786-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: fix sm8450 CTL configurationDmitry Baryshkov1-5/+5
Correct the CTL size on sm8450 platform. This fixes the incorrect merge of sm8350 support, which unfortunately also touched the SM8450 setup. Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/519671/ Link: https://lore.kernel.org/r/20230123080818.3069266-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: add missing ubwc_swizzle setting to catalogDmitry Baryshkov1-0/+5
Use the values from the vendor DTs to set ubwc_swizzle in the catalog. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/519662/ Link: https://lore.kernel.org/r/20230123062415.3027743-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: drop stale comment from struct dpu_mdp_cfg docDmitry Baryshkov1-1/+0
The field ubwc_static was removed from struct dpu_mdp_cfg some time ago. Drop the corresponding kerneldoc now. Fixes: 544d8b96150d ("drm/msm/dpu: update UBWC config for sm8150 and sm8250") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/519554/ Link: https://lore.kernel.org/r/20230121135457.2788199-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm: use strscpy instead of strncpyDmitry Baryshkov1-1/+1
Using strncpy can result in non-NULL-terminated destination string. Use strscpy instead. This fixes following warning: drivers/gpu/drm/msm/msm_fence.c: In function ‘msm_fence_context_alloc’: drivers/gpu/drm/msm/msm_fence.c:25:9: warning: ‘strncpy’ specified bound 32 equals destination size [-Wstringop-truncation] 25 | strncpy(fctx->name, name, sizeof(fctx->name)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518787/ Link: https://lore.kernel.org/r/20230118020152.1689213-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-24drm/msm/dpu: sc7180: add missing WB2 clock controlDmitry Baryshkov1-0/+2
Add missing DPU_CLK_CTRL_WB2 to sc7180_mdp clocks array. Fixes: 51e4d60e6ba5 ("drm/msm/dpu: add writeback support for sc7180") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/518504/ Link: https://lore.kernel.org/r/20230116103055.780767-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22Merge branch 'msm-next-lumag' into HEADDmitry Baryshkov48-393/+1628
Merge display-related changes targeting Qualcomm DRM MSM driver. Notable changes: DPU, DSI, MDSS: - Support for SM8350, SM8450 SM8550 and SC8280XP platform Core: - Added bindings for SM8150 (driver support already present) DPU: - Partial support for DSC on SM8150 and SM8250 - Fixed color transformation matrix being lost on suspend/resume DP: - Support for DP on SDM845 and SC8280XP platforms - HPD fixes - Support for limiting DP link rate via DT property, this enables support for HBR3 rates. DSI: - Validate display modes according to the DSI OPP table - DSI PHY support for the SM6375 platform - Fixed byte intf clock selection for 14nm PHYs MDP5: - Schema conversion to YAML Misc fixes as usual Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', ↵Dmitry Baryshkov41-373/+1580
'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi', 'msm-next-lumag-mdp5' and 'msm-next-lumag-mdp4' into msm-next-lumag DPU, DSI, MDSS: - Support for SM8350, SM8450 SM8550 and SC8280XP platform Core: - Added bindings for SM8150 (driver support already present) DPU: - Partial support for DSC on SM8150 and SM8250 - Fixed color transformation matrix being lost on suspend/resume DP: - Support for DP on SDM845 and SC8280XP platforms - HPD fixes - Support for limiting DP link rate via DT property, this enables support for HBR3 rates. DSI: - Validate display modes according to the DSI OPP table - DSI PHY support for the SM6375 platform - Fixed byte intf clock selection for 14nm PHYs MDP5: - Schema conversion to YAML Misc fixes as usual Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: Allow 2 CTRLs on v2.5.0Konrad Dybcio1-2/+2
v2.5.0 support was originally added for SC7280, but this hw is also present on SM8350, which has one more DSI host. Bump up the dsi count and fill in the register of the secondary host to allow it to probe. This should not have any adverse effects on SC7280, as the secondary CTRL will only be touched if it's defined, anyway. Fixes: 65c391b31994 ("drm/msm/dsi: Add DSI support for SC7280") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519513/ Link: https://lore.kernel.org/r/20230120210101.2146852-1-konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: correct byte intf clock rate for 14nm DSI PHYDmitry Baryshkov3-8/+11
According to the vendor kernel, byte intf clock rate should be a half of the byte clock only when DSI PHY version is above 2.0 (in other words, 10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently MSM DSI code handles only the second part of the clause (C-PHY vs D-PHY), skipping DSI PHY version check, which causes issues on some of 14nm DSI PHY platforms (e.g. qcm2290). Move divisor selection to DSI PHY code, pass selected divisor through shared timings and set byte intf clock rate accordingly. Cc: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6115P J606F Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519006/ Link: https://lore.kernel.org/r/20230118130027.2345719-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: Add phy configuration for SM6375Konrad Dybcio3-0/+23
SM6375 uses a boring standard 7nm PHY. Add a configuration entry for it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/518511/ Link: https://lore.kernel.org/r/20230116114059.346327-2-konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()Abhinav Kumar1-0/+19
Currently there is no protection against a user trying to set an unsupported mode on DSI. Implement a check based on the opp table whether the byte clock for the mode can be supported by validating whether an opp table entry exists. For devices which have not added opp table support yet, skip this check otherwise it will break bootup on those devices. changes in v3: - make the comment shorter - handle all errors except ENODEV Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/15 Reported-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/518008/ Link: https://lore.kernel.org/r/20230112001600.12791-2-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: add a helper method to compute the dsi byte clkAbhinav Kumar2-7/+16
Re-arrange the dsi_calc_pclk method to two helpers, one to compute the DSI byte clk and the other to compute the pclk. This makes the separation of the two clean and also allows clients to compute and use the dsi byte clk separately. changes in v2: - move the assignments to definition lines Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/518005/ Link: https://lore.kernel.org/r/20230112001600.12791-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: Drop the redundant fail labelJiasheng Jiang1-16/+8
Drop the redundant fail label and change the "goto fail" into "return ret" since they are the same. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517816/ Link: https://lore.kernel.org/r/20230111011006.6238-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: Add missing check for alloc_ordered_workqueueJiasheng Jiang1-0/+3
Add check for the return value of alloc_ordered_workqueue as it may return NULL pointer and cause NULL pointer dereference. Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/517646/ Link: https://lore.kernel.org/r/20230110021651.12770-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: add support for DSI 2.7.0Neil Armstrong2-0/+17
Add support for DSI 2.7.0 (block used on sm8550). Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517517/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-7-660c3bcb127f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: add support for DSI-PHY on SM8550Neil Armstrong4-16/+79
SM8550 use a 4nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 4nm variant inside the common 5+7nm driver. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517515/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-6-660c3bcb127f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: add support for DSI 2.6.0Dmitry Baryshkov2-0/+3
Add support for DSI 2.6.0 (block used on sm8450). Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514237/ Link: https://lore.kernel.org/r/20221207012231.112059-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-22drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450Dmitry Baryshkov4-13/+118
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm variants inside the common 5+7nm driver. Co-developed-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514230/ Link: https://lore.kernel.org/r/20221207012231.112059-7-dmitry.baryshkov@linaro.org [DB: changed compatibles per Krzysztof's request] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: Reapply CTM if modeset is neededJessica Zhang1-1/+1
Add a !drm_atomic_crtc_needs_modeset() check to _dpu_crtc_setup_cp_blocks() so that CTM is reapplied if the LM/DSPP blocks were reallocated during modeset or after a suspend/resume. Changes in V2: - Fixed commit message Changes in V3: - Added mention of suspend/resume case back to commit message Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/23 Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519151/ Link: https://lore.kernel.org/r/20230118233848.611-1-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: use sm8350_regdma on SM8350 platformDmitry Baryshkov1-1/+1
Correct sm8350_dpu_cfg.dma_cfg to point to sm8350_regdma rather than sm8250_regdma. Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518791/ Link: https://lore.kernel.org/r/20230118020455.1689929-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdmaDmitry Baryshkov1-0/+2
SC8280XP configuration missed the reg_dma configuration. We do not use regdma for now, but let's put the correct pointer anyway. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518790/ Link: https://lore.kernel.org/r/20230118020455.1689929-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: add missing dpu_encoder kerneldocDmitry Baryshkov2-0/+2
Describe missing dpu_encoder_phys_wb_is_master() argument and struct dpu_encoder_virt.wide_bus_en field. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518794/ Link: https://lore.kernel.org/r/20230118020549.1690078-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: enable DPU_MDP_AUDIO_SELECT for sc8180xDmitry Baryshkov1-1/+1
According to the discussion ([1]) on the mailing list, platforms before sm8250 (and derivatives) should program HDMI_DP_CORE_SELECT register to route audio to the DP ports. Enable DPU_MDP_AUDIO_SELECT on sc8180x to program correponding register. [1] https://lore.kernel.org/all/f86504ba-835a-6e30-6c30-8bb89b1359c4@quicinc.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518461/ Link: https://lore.kernel.org/r/20230115140022.489881-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: simplify blend configurationDmitry Baryshkov1-111/+45
Rewrite dpu_hw_ctl_setup_blendstage() to use static data configuration rather than using a switch-case. This simplifies adding support for new pipes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 Patchwork: https://patchwork.freedesktop.org/patch/518485/ Link: https://lore.kernel.org/r/20230116063316.728496-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: simplify ctl_setup_blendstage calculationDmitry Baryshkov1-19/+19
Extract the common expression in the dpu_hw_ctl_setup_blendstage() function. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 Patchwork: https://patchwork.freedesktop.org/patch/518483/ Link: https://lore.kernel.org/r/20230116063316.728496-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-21drm/msm/dpu: fix blend setup for DMA4 and DMA5 layersDmitry Baryshkov3-6/+30
SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend stages. Add proper support for this register to allow using these two planes for image processing. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 Patchwork: https://patchwork.freedesktop.org/patch/518481/ Link: https://lore.kernel.org/r/20230116063316.728496-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-18drm/msm/dp: Remove INIT_SETUP delayBjorn Andersson1-1/+1
During initalization of the DisplayPort controller an EV_HPD_INIT_SETUP event is generated, but with a delay of 100 units. This delay existed to circumvent bug in the QMP combo PHY driver, where if the DP part was powered up before USB, the common properties would not be properly initialized - and USB wouldn't work. This issue was resolved in the recent refactoring of the QMP driver, so it's now possible to remove this delay. While there is still a timing dependency in the current implementation, test indicates that it's now possible to boot with an external display on USB Type-C and have the display power up, without disconnecting and reconnecting the cable. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518729/ Link: https://lore.kernel.org/r/20230117172951.2748456-1-quic_bjorande@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-18drm/msm/dpu: enable sourcesplit for sc7180/sc7280Dmitry Baryshkov1-7/+7
According to the vendor dts files, both sc7180 and sc7280 support the source split mode (using two LMs for a single output). Change these two platforms to use MIXER_SDM845_MASK, which includes DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK, since this platform doesn't seem to support source split mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518479/ Link: https://lore.kernel.org/r/20230116034435.569512-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-01-18drm/msm/dpu: merge two CRTC debugfs dirsDmitry Baryshkov1-6/+2
For each CRTC we are creating two different debugfs directories one using crtc index (created automatically for the CRC files) and another one using CRTC name/object ID (for state and status files). This can be confusing, so move our custom files to crtc->debugfs_entry, effetively merging two debugfs dirs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518065/ Link: https://lore.kernel.org/r/20230112053659.1361298-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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