aboutsummaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2019-10-18Merge branches 'pm-cpufreq' and 'pm-sleep'Rafael J. Wysocki5-31/+15
* pm-cpufreq: ACPI: processor: Avoid NULL pointer dereferences at init time cpufreq: Avoid cpufreq_suspend() deadlock on system shutdown * pm-sleep: PM: sleep: include <linux/pm_runtime.h> for pm_wq ACPI: PM: Drop Dell XPS13 9360 from LPS0 Idle _DSM blacklist
2019-10-17net: phy: micrel: Update KSZ87xx PHY nameMarek Vasut1-2/+2
The KSZ8795 PHY ID is in fact used by KSZ8794/KSZ8795/KSZ8765 switches. Update the PHY ID and name to reflect that, as this family of switches is commonly refered to as KSZ87xx Signed-off-by: Marek Vasut <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: David S. Miller <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: George McCollister <[email protected]> Cc: Heiner Kallweit <[email protected]> Cc: Sean Nyekjaer <[email protected]> Cc: Tristram Ha <[email protected]> Cc: Woojung Huh <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17net: phy: micrel: Discern KSZ8051 and KSZ8795 PHYsMarek Vasut1-4/+36
The KSZ8051 PHY and the KSZ8794/KSZ8795/KSZ8765 switch share exactly the same PHY ID. Since KSZ8051 is higher in the ksphy_driver[] list of PHYs in the micrel PHY driver, it is used even with the KSZ87xx switch. This is wrong, since the KSZ8051 configures registers of the PHY which are not present on the simplified KSZ87xx switch PHYs and misconfigures other registers of the KSZ87xx switch PHYs. Fortunatelly, it is possible to tell apart the KSZ8051 PHY from the KSZ87xx switch by checking the Basic Status register Bit 0, which is read-only and indicates presence of the Extended Capability Registers. The KSZ8051 PHY has those registers while the KSZ87xx switch does not. This patch implements simple check for the presence of this bit for both the KSZ8051 PHY and KSZ87xx switch, to let both use the correct PHY driver instance. Fixes: 9d162ed69f51 ("net: phy: micrel: add support for KSZ8795") Signed-off-by: Marek Vasut <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: David S. Miller <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: George McCollister <[email protected]> Cc: Heiner Kallweit <[email protected]> Cc: Sean Nyekjaer <[email protected]> Cc: Tristram Ha <[email protected]> Cc: Woojung Huh <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-18drm/i915: Pass in intel_gt at some for_each_engine sitesTvrtko Ursulin15-67/+67
Where the function, or code segment, operates on intel_gt, we need to start passing it instead of i915 to for_each_engine(_masked). This is another partial step in migration of i915->engines[] to gt->engines[]. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-18drm/i915: Make for_each_engine_masked work on intel_gtTvrtko Ursulin11-32/+37
Medium term goal is to eliminate the i915->engine[] array and to get there we have recently introduced equivalent array in intel_gt. Now we need to migrate the code further towards this state. This next step is to eliminate usage of i915->engines[] from the for_each_engine_masked iterator. For this to work we also need to use engine->id as index when populating the gt->engine[] array and adjust the default engine set indexing to use engine->legacy_idx instead of assuming gt->engines[] indexing. v2: * Populate gt->engine[] earlier. * Check that we don't duplicate engine->legacy_idx v3: * Work around the initialization order issue between default_engines() and intel_engines_driver_register() which sets engine->legacy_idx for now. It will be fixed properly later. v4: * Merge with forgotten v2.5. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17Merge tag 'drm-fixes-2019-10-18' of git://anongit.freedesktop.org/drm/drmLinus Torvalds21-95/+150
Pull drm fixes from Dave Airlie: "This is this weeks fixes for drm. The dma-resv one is probably the more important one a fair few people have reported it, besides that it's a couple of panfrost, a few i915 and a few amdgpu fixes. One radeon patch to fix some ppc64 related issues caused an x86 regression so is getting reverted for now. Summary: dma-resv: - shared fences for lima/panfrost ttm: - prefault regression fix - lifetime fix panfrost: - stopped job timeout fix - missing register values amdgpu: - smu7 powerplay fix - bail earlier for cik/si detection - navi SDMA fix radeon: - revert a ppc64 shutdown fix that broke x86 i915: - VBT information handling fix - Circular locking fix - preemption vs resubmission virtual requests fix" * tag 'drm-fixes-2019-10-18' of git://anongit.freedesktop.org/drm/drm: drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request drm/i915/userptr: Never allow userptr into the mappable GGTT drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin drm/i915/execlists: Refactor -EIO markup of hung requests drm/panfrost: Handle resetting on timeout better drm/panfrost: Add missing GPU feature registers drm/ttm: fix handling in ttm_bo_add_mem_to_lru drm/ttm: Restore ttm prefaulting drm/ttm: fix busy reference in ttm_mem_evict_first drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe sync drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1 Revert "drm/radeon: Fix EEH during kexec" drm/msm/dsi: Implement reset correctly dma-buf/resv: fix exclusive fence get drm/edid: Add 6 bpc quirk for SDC panel in Lenovo G50 drm/tiny: Kconfig: Remove always-y THERMAL dep. from TINYDRM_REPAPER drm/amdgpu/powerplay: fix typo in mvdd table setup
2019-10-17drm/i915: Don't disable interrupts independently of the lockSebastian Andrzej Siewior1-8/+4
The locks (active.lock and rq->lock) need to be taken with disabled interrupts. This is done in i915_request_retire() by disabling the interrupts independently of the locks itself. While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla it does not on PREEMPT_RT. Chris Wilson confirmed that local_irq_disable() was just introduced as an optimisation to avoid enabling/disabling interrupts during lock/unlock combo. Enable/disable interrupts as part of the locking instruction. Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-18Merge tag 'drm-misc-fixes-2019-10-17' of ↵Dave Airlie8-22/+34
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes -dma-resv: Change shared_count to post-increment to fix lima crash (Qiang) -ttm: A couple fixes related to lifetime and restore prefault behavior (Christian & Thomas) -panfrost: Fill in missing feature reg values and fix stoppedjob timeouts (Steven) Cc: Qiang Yu <[email protected]> Cc: Thomas Hellstrom <[email protected]> Cc: Christian König <[email protected]> Cc: Steven Price <[email protected]> Signed-off-by: Dave Airlie <[email protected]> From: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20191017203419.GA142909@art_vandelay
2019-10-17drm/amdgpu: fix amdgpu trace event print string format errorKevin Wang1-9/+9
the trace event print string format error. (use integer type to handle string) before: amdgpu_test_kev-1556 [002] 138.508781: amdgpu_cs_ioctl: sched_job=8, timeline=gfx_0.0.0, context=177, seqno=1, ring_name=ffff94d01c207bf0, num_ibs=2 after: amdgpu_test_kev-1506 [004] 370.703783: amdgpu_cs_ioctl: sched_job=12, timeline=gfx_0.0.0, context=234, seqno=2, ring_name=gfx_0.0.0, num_ibs=1 change trace event list: 1.amdgpu_cs_ioctl 2.amdgpu_sched_run_job 3.amdgpu_ib_pipe_sync Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/psp: add psp memory training implementation(v3)Tianci.Yin3-0/+171
add memory training implementation code to save resume time. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: reserve vram for memory training(v4)Tianci.Yin1-0/+91
memory training using specific fixed vram segment, reserve these segments before anyone may allocate it. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: add psp memory training callbacks and macroTianci.Yin2-0/+73
add interface for memory training. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/atomfirmware: add memory training related helper functions(v3)Tianci.Yin4-0/+150
parse firmware to get memory training capability and fb location. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: update atomfirmware header with memory training related members(v3)Tianci.Yin1-6/+21
add new vram_reserve_block structure and atomfirmware_internal_constants enumeration Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: introduce psp_v11_0_is_sos_alive interface(v2)Tianci.Yin1-9/+13
introduce psp_v11_0_is_sos_alive func for common use. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: add a generic fb accessing helper function(v3)Tianci.Yin3-11/+33
add a generic helper function for accessing framebuffer via MMIO Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: update amdgpu_discovery to handle revisionTianci.Yin2-2/+4
update amdgpu_discovery to get IP revision. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/powerplay: implement interface pp_power_profile_modePrike Liang1-0/+34
implement get_power_profile_mode for getting power profile mode status. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/vcn: fix allocation size in enc ring testAlex Deucher1-12/+23
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. - Session info is 128K according to mesa - Use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Tested-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/uvd7: fix allocation size in enc ring test (v2)Alex Deucher1-11/+22
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Tested-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/uvd6: fix allocation size in enc ring test (v2)Alex Deucher1-10/+21
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Tested-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DSC_SUPPORT=nAlex Deucher1-0/+2
Add proper config check. Reviewed-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Make dc_link_detect_helper staticYueHaibing1-1/+2
Fix sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6: warning: symbol 'dc_link_detect_helper' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: null check pp_smu clock table before using itBhawanpreet Lakha1-1/+1
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: handle dp is usb-cBhawanpreet Lakha3-1/+116
This patch adds handling of dp is usb-c, it is not tested but is needed to support dp over usb-c Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: use requested_dispclk_khz instead of clkBhawanpreet Lakha1-11/+2
Use requested_dispclk_khz / 1000 directly Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: enable smu set dcfclkLewis Huang1-2/+2
[Why] SMU fixed this issue after version 0x370c00 [How] enable smu send message to set dcfclk after smu version 0x370c00 Signed-off-by: Lewis Huang <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: fix header for RN clk mgrjoseph gravenor1-1/+1
[why] Should always MP0_BASE for any register definition from MP per-IP header files. I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file. The reason we should only use MP0_BASE is There is only one set of per-IP headers MP that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2 and an ecryption engine that can be used only by MP0. As a result all register definitions from MP file should be based only on MP0_BASE data. [How] Change MP1_BASE to MP0_BASE Signed-off-by: joseph gravenor <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add sanity check for clk table from smuEric Yang1-0/+8
[Why] Handle the case where we don't get a valid table. Also fixes compiler warning for variable potentially used before assignment. [How] If the entire table has no valid fclk, reject the table and use our own hard code. Signed-off-by: Eric Yang <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Fix rn audio playback and video playback speedMichael Strauss1-8/+7
[WHY] dprefclk is improperly read due to incorrect units used. Causes an audio clock to be improperly set, making audio non-functional and videos play back too fast [HOW] Scale dprefclk value from MHz to KHz (multiply by 1000) to ensure that dprefclk_khz is in correct units Signed-off-by: Michael Strauss <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: handle "18" case in TruncToValidBPPBhawanpreet Lakha1-0/+2
Handle 18 DecimalBPP like other cases Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update odm mode validation to be in line with policyDmytro Laktyushkin1-1/+8
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add dummy functions to smu for Renoir Silicon DiagsSung Lee1-1/+1
[Why] Previously only dummy functions were added in Diags for FPGA. On silicon, this would lead to a segmentation fault on silicon diags. [How] Check if diags silicon and if so, add dummy functions. Signed-off-by: Sung Lee <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: change PP_SM defs to 8Bhawanpreet Lakha1-2/+2
DPM level is 8 these were incorrect before. Fix them Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update renoir bounding box and res_capsBhawanpreet Lakha1-11/+13
The values for bounding box and res_caps were incorrect. So Fix them Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update dcn21 hubbub registersBhawanpreet Lakha1-10/+7
use dcn20 common regs define to share some regs with dcn20 Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add detile buffer size for renoirBhawanpreet Lakha1-0/+1
Detile buffer size affects dcc caps, it was already added for dcn2. Now add it for dcn21 Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: correct dcn21 NUM_VMID to 16Dmytro Laktyushkin1-1/+1
1 vmid limitation only exists for HOSTVM which is a custom use case anyway. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: use dcn10 version of program tiling on RenoirEric Yang1-1/+3
[Why] Renoir is gfx9, same as dcn10, not dcn20. Signed-off-by: Eric Yang <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: initialize RN gpuvm context programming functionDmytro Laktyushkin1-1/+1
Renoir can use vm contexes as long as HOSTVM is off so this should be initialized. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Temporary workaround to toggle watermark settingLewis Huang4-0/+15
[Why] Watermarks not propagated to DCHUBP after it is powered on [How] Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: fix incorrect page table address for renoirBhawanpreet Lakha1-6/+17
Incorrect page table address and programming sys aperture for stutter gather, so fix it. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: enable hostvm based on roimmu active for dcn2.1Dmytro Laktyushkin1-15/+25
Enabling hostvm when ROIMMU is not active seems to break GPUVM. This fixes the issue by not enabling hostvm if ROIMMU is not activated. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: move the bounding box patch before calculate wmLewis Huang1-0/+25
[why] driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box [How] Move the patch function before calculate wm. Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: joseph graveno <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programmingBhawanpreet Lakha4-4/+69
it allows us to do urgent latency programming Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: create dcn21_link_encoder filesBhawanpreet Lakha6-4/+555
[Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add renoir hw_seqBhawanpreet Lakha7-28/+255
This change adds renoir hw_seq, needed to do renoir specific hw programing Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DCN_BASE regsBhawanpreet Lakha1-0/+34
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: disable ext aux support for vegaRoman Li1-1/+1
[Why] Earlier changes to support configurable aux timeout caused dc init failure on vega due to missing reg defs. Needs to be disabled until implemented for vega. [How] Set extended aux timeout cap for vega to false. Signed-off-by: Roman Li <[email protected]> Reviewed-By: abdoulaye berthe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.