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2019-10-26drm/i915: Extract the GuC interrupt handlersAndi Shyti3-102/+89
Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT interrupt facilities rather than the central dispatch. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Extract GT render power state managementAndi Shyti24-2310/+2126
i915_irq.c is large. One reason for this is that has a large chunk of the GT render power management stashed away in it. Extract that logic out of i915_irq.c and intel_pm.c and put it under one roof. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915/tgl: Adjust the location of RING_MI_MODE in the context imageChris Wilson2-3/+87
The location of RING_MI_MODE (used to stop the ring across resets) moved for Tigerlake. Fixup the new location and include a selftest to verify the location in the default context image. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Encapsulate kconfig constant values inside boolean predicatesChris Wilson5-5/+19
Avoid angering clang and smatch by using a constant value in a '&&' test, by forcing that constant value into a boolean. E.g., drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand] if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) { ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: kbuild test robot <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Nathan Chancellor <[email protected]> Cc: Nick Desaulniers <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: Nathan Chancellor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swingJosé Roberto de Souza2-0/+8
This sequence was recently added to fix internal HW sequences to reset TC ports. HSDES: 1507287614 HSDES: 14010071447 BSpec: 49292 Reviewed-by: Lucas De Marchi <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/pmu: Initialise the spinlock before registeringChris Wilson1-18/+19
As the GT may be running in parallel with the module initialisation code, we may enter i915_pmu_gt_parked() as we are executing i915_pmu_register(). We have to init the spinlock before we mark pmu.event_init so that it is available for use by i915_pmu_gt_parked() (which may run as soon as event_init is set). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127 Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests/blt: add some kthreads into the mixMatthew Auld1-25/+153
We can be more aggressive in our testing by launching a number of kthreads, where each is submitting its own copy or fill batches on a set of random sized objects. Also since the underlying fill and copy batches can be pre-empted mid-batch(for particularly large objects), throw in a random mixture of ctx priorities per thread to make pre-emption a possibility. Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: add sanity selftest for huge-GTT-pagesMatthew Auld1-0/+99
Now that for all the relevant backends we do randomised testing, we need to make sure we still sanity check the obvious cases that might blow up, such that introducing a temporary regression is less likely. Also rather than do this for every backend, just limit to our two memory types: system and local. Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke testsMatthew Auld1-149/+80
Ditch the dubious static list of sizes to enumerate, in favour of choosing a random size within the limits of each backing store. With repeated CI runs this should give us a wider range of object sizes, and in turn more page-size combinations, while using less machine time. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: extend coverage to include LMEM huge-pagesMatthew Auld1-1/+122
Add LMEM objects to list of backends we test for huge-GTT-pages. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: add write-dword test for LMEMMatthew Auld1-0/+166
Simple test writing to dwords across an object, using various engines in a randomized order, checking that our writes land from the cpu. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/lmem: support kernel mappingAbdiel Janulgue5-18/+192
We can create LMEM objects, but we also need to support mapping them into kernel space for internal use. Signed-off-by: Abdiel Janulgue <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Signed-off-by: Steve Hampson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: setup io-mapping for LMEMAbdiel Janulgue1-2/+26
Create an io-mapping to describe the CPU aperture for lmem. Signed-off-by: Abdiel Janulgue <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: support creating LMEM objectsMatthew Auld8-0/+159
We currently define LMEM, or local memory, as just another memory region, like system memory or stolen, which we can expose to userspace and can be mapped to the CPU via some BAR. Signed-off-by: Matthew Auld <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Abdiel Janulgue <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: split gen11_irq_handler to make it shareableLucas De Marchi1-5/+14
Split gen11_irq_handler() to receive as parameter the function pointers. This allows to share the interrupt handler even if the enable/disable functions are different. Make sure it's always inlined to avoid the extra indirect call on the hot path. Checking with gcc 9 this produce the exact same code as of now: $ size drivers/gpu/drm/i915/i915_irq*.o text data bss dec hex filename 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq.o 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq_new.o $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble gen11_irq_handler' > /tmp/old.s $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble gen11_irq_handler' > /tmp/new.s $ git diff --no-index /tmp/{old,new}.s $ So, no change in behavior, just a simple refactor. Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: do not set MOCS control values on dgfxLucas De Marchi1-0/+6
On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: add new gen12 dgfx platform macroStuart Summers1-0/+4
Add a new macro for GEN12 platforms to be grouped under dgfx feature set. Signed-off-by: Stuart Summers <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: Add is_dgfx to device infoJosé Roberto de Souza2-0/+2
This will be helpful to diferentiate a set of GPUs with the same GEN version. Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/amdgpu: If amdgpu_ib_schedule fails return back the error.Andrey Grodzovsky1-1/+3
Use ERR_PTR to return back the error happened during amdgpu_ib_schedule. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/sched: Set error to s_fence if HW job submission failed.Andrey Grodzovsky1-3/+16
Problem: When run_job fails and HW fence returned is NULL we still signal the s_fence to avoid hangs but the user has no way of knowing if the actual HW job was ran and finished. Fix: Allow .run_job implementations to return ERR_PTR in the fence pointer returned and then set this error for s_fence->finished fence so whoever wait on this fence can inspect the signaled fence for an error. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0chen gong1-1/+1
The parameters what SMU_MSG_PowerUpVcn need is 0, not 1 Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settings for navi12Tianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: correct current clock level label for ArcturusEvan Quan1-8/+16
For dpm disabled case, it's assumed the only one support clock level is always current clock level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: skip unsupported clock limit settings on Arcturus V2Evan Quan2-116/+39
For Arcturus, clock limit settings on uclk/socclk/fclk domains are not supported. V2: simplify the code to support both SGPU and MGPU cases Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Allow reading more status registers on si/cikMarek Olšák5-1/+34
Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Move amdgpu_ras_recovery_init to after SMU ready.Andrey Grodzovsky2-11/+13
For Arcturus the I2C traffic is done through SMU tables and so we must postpone RAS recovery init to after they are ready which is in amdgpu_device_ip_hw_init_phase2. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Use ARCTURUS in RAS EEPROM.Andrey Grodzovsky1-1/+8
Add Arcturus EEPROM/I2C support in generic EEPROM code. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: Add EEPROM I2C read/write support to Arcturus.Andrey Grodzovsky1-0/+229
The communication is done through SMU table and hence the code is in powerplay. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: Add interface for I2C transactions to SMU.Andrey Grodzovsky1-0/+9
Will be used by Arcturus support for RAS page retirement. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Add DC feature mask to disable fractional pwmLeo Li3-0/+8
[Why] Some LED panel drivers might not like fractional PWM. In such cases, backlight flickering may be observed. [How] Add a DC feature mask to disable fractional PWM, and associate it with the preexisting dc_config flag. The flag is only plumbed through the dmcu firmware, so plumb it through the driver path as well. To disable, add the following to the linux cmdline: amdgpu.dcfeaturemask=0x4 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957 Signed-off-by: Leo Li <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Tested-by: Lukáš Krejčí <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: remove unused parameter in amdgpu_gfx_kiq_free_ringNirmoy Das5-7/+5
Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/vcn: Enable VCN2.5 encodingJames Zhu1-3/+0
After VCN2.5 firmware (Version ENC: 1.1 Revision: 11), VCN2.5 encoding can work properly. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)Pelloux-prayer, Pierre-eric1-0/+1
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Fix SDMA hang when performing VKexample testchen gong1-0/+1
VKexample test hang during Occlusion/SDMA/Varia runs. Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue. Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: define macros for retire page reservationGuchun Chen1-6/+11
Easy for maintainance. Signed-off-by: Guchun Chen <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: refine reboot debugfs operation in ras case (v3)Guchun Chen1-7/+12
Ras reboot debugfs node allows user one easy control to avoid gpu recovery hang problem and directly reboot system per card basis, after ras uncorrectable error happens. However, it is one common entry, which should get rid of ras_ctrl node and remove ip dependence when inputting by user. So add one new auto_reboot node in ras debugfs dir to achieve this. v2: in commit mssage, add justification why ras reboot debugfs node is needed. v3: use debugfs_create_bool to create debugfs file for boolean value Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdkfd: don't use dqm lock during device reset/suspend/resumePhilip Yang3-10/+43
If device reset/suspend/resume failed for some reason, dqm lock is hold forever and this causes deadlock. Below is a kernel backtrace when application open kfd after suspend/resume failed. Instead of holding dqm lock in pre_reset and releasing dqm lock in post_reset, add dqm->sched_running flag which is modified in dqm->ops.start and dqm->ops.stop. The flag doesn't need lock protection because write/read are all inside dqm lock. For HWS case, map_queues_cpsch and unmap_queues_cpsch checks sched_running flag before sending the updated runlist. v2: For no-HWS case, when device is stopped, don't call load/destroy_mqd for eviction, restore and create queue, and avoid debugfs dump hdqs. Backtrace of dqm lock deadlock: [Thu Oct 17 16:43:37 2019] INFO: task rocminfo:3024 blocked for more than 120 seconds. [Thu Oct 17 16:43:37 2019] Not tainted 5.0.0-rc1-kfd-compute-rocm-dkms-no-npi-1131 #1 [Thu Oct 17 16:43:37 2019] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [Thu Oct 17 16:43:37 2019] rocminfo D 0 3024 2947 0x80000000 [Thu Oct 17 16:43:37 2019] Call Trace: [Thu Oct 17 16:43:37 2019] ? __schedule+0x3d9/0x8a0 [Thu Oct 17 16:43:37 2019] schedule+0x32/0x70 [Thu Oct 17 16:43:37 2019] schedule_preempt_disabled+0xa/0x10 [Thu Oct 17 16:43:37 2019] __mutex_lock.isra.9+0x1e3/0x4e0 [Thu Oct 17 16:43:37 2019] ? __call_srcu+0x264/0x3b0 [Thu Oct 17 16:43:37 2019] ? process_termination_cpsch+0x24/0x2f0 [amdgpu] [Thu Oct 17 16:43:37 2019] process_termination_cpsch+0x24/0x2f0 [amdgpu] [Thu Oct 17 16:43:37 2019] kfd_process_dequeue_from_all_devices+0x42/0x60 [amdgpu] [Thu Oct 17 16:43:37 2019] kfd_process_notifier_release+0x1be/0x220 [amdgpu] [Thu Oct 17 16:43:37 2019] __mmu_notifier_release+0x3e/0xc0 [Thu Oct 17 16:43:37 2019] exit_mmap+0x160/0x1a0 [Thu Oct 17 16:43:37 2019] ? __handle_mm_fault+0xba3/0x1200 [Thu Oct 17 16:43:37 2019] ? exit_robust_list+0x5a/0x110 [Thu Oct 17 16:43:37 2019] mmput+0x4a/0x120 [Thu Oct 17 16:43:37 2019] do_exit+0x284/0xb20 [Thu Oct 17 16:43:37 2019] ? handle_mm_fault+0xfa/0x200 [Thu Oct 17 16:43:37 2019] do_group_exit+0x3a/0xa0 [Thu Oct 17 16:43:37 2019] __x64_sys_exit_group+0x14/0x20 [Thu Oct 17 16:43:37 2019] do_syscall_64+0x4f/0x100 [Thu Oct 17 16:43:37 2019] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Suggested-by: Felix Kuehling <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: Change Navi14's DWB flag to 1Zhan liu1-1/+1
[Why] DWB (Display Writeback) flag needs to be enabled as 1, or system will throw out a few warnings when creating dcn20 resource pool. Also, Navi14's dwb setting needs to match Navi10's, which has already been set to 1. [How] Change value of num_dwb from 0 to 1. Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/display: add dc feature mask for psr enablementRoman Li2-1/+3
[Why] Adding psr mask to dc features allows selectively disable/enable psr. Current psr implementation may not work with non-pageflipping application. Until resolved it should be disabled by default. [How] Add dcfeaturemask for psr enablement. Disable by default. To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: clear the swSMU code layerEvan Quan12-318/+519
With this cleanup, the APIs from amdgpu_smu.c will map to ASIC specific ones directly. Those can be shared around all SMU V11/V12 ASICs will be put in smu_v11_0.c and smu_v12_0.c respectively. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: split out those internal used swSMU APIs V2Evan Quan9-160/+212
Those swSMU APIs used internally are moved to smu_internal.h while others are kept in amdgpu_smu.h. V2: give a better name smu_internal.h for the place to hold those internal APIs Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: add lock protection for swSMU APIs V2Evan Quan12-199/+781
This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by: Evan Quan <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Acked-by: Feifei Xu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: add VCN0 and VCN1 needed headersJane Jian1-0/+12
Add mmsch part registers Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2Joshua Aberback1-1/+2
[Why] This workaround was put in dcn2 DMLv1, and now we need it in DMLv2. Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: fix hubbub deadline programingEric Yang2-0/+2
[Why] Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A. Was not filled in. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: fix avoid_split for dcn2+ validationDmytro Laktyushkin1-4/+7
We are currently incorrectly processing avoid split at highest voltage level. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: Do not call update bounding box on dc createSung Lee1-1/+7
[Why] In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP. This causes an issue on dc init where dcn2_1_soc which has been updated by update_bw_bounding_box gets put into dml->soc. As update_bw_bounding_box is currently incorrect for dcn2.1, this makes dml calculations fail due to incorrect parameters, leading to a crash on PnP. [How] Comment out update_bw_bounding_box call for now. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/display: Add center mode for integer scaling in DCReza Amini1-8/+35
[why] We want to use maximum space on display to show source [how] For Centered Mode: Replicate source as many times as possible to use maximum of display active space add borders. Signed-off-by: Reza Amini <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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