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2019-10-28drm/tegra: sor: Unify clock setup for eDP, HDMI and DPThierry Reding1-11/+81
With the clocks modelled consistently across SoC generations, the clock setup for eDP, HDMI and DP can now be unified. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Support DisplayPort on Tegra194Thierry Reding1-0/+5
Reuse parameters from earlier generations to support DisplayPort on Tegra194. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Deduplicate connector type detection codeThierry Reding1-109/+109
The connector type detection code is duplicated in two places. Keeping both places in sync is an extra maintenance burden that can be avoided by comparing the connector type operations that are set upon the first detection. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Implement pad clock for all SOR instancesThierry Reding1-6/+14
So far the pad clock was only needed on the second SOR instance. The clock does exist for all SOR instances, though, so make sure it is always implemented. This prepares for further unification of the code in subsequent patches. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Use correct SOR index on Tegra210Thierry Reding1-0/+5
The device tree bindings for the Tegra210 SOR don't require the controller instance to be defined, since the instance can be derived from the compatible string. The index is never used on Tegra210, so we got away with it not getting set. However, subsequent patches will change that, so make sure the proper index is used. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Remove tegra186-sor1 supportThierry Reding1-18/+0
It turns out that SOR1 is just another instance of the same block as the SOR0, so there is no need to distinguish them. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Add DisplayPort supportThierry Reding3-6/+348
Add support for regular DisplayPort on Tegra210 and Tegra186. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Filter eDP ratesThierry Reding1-0/+26
The SOR found on Tegra SoCs does not support all the rates potentially advertised by eDP 1.4. Make sure that the rates that are not supported are filtered out. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Stabilize eDPThierry Reding1-89/+49
Rework eDP code to correspond more closely to what's documented. This also improves the reliability of modesets. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Hook up I2C-over-AUX to outputThierry Reding1-0/+2
This is necessary for the output abstraction to retrieve a list of valid modes from the EDID of a connected panel/monitor. This will be useful in conjunction with DisplayPort support that will be added in a subsequent patch, so that the driver can read EDID via the AUX channel. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: sor: Use DP link training helpersThierry Reding4-290/+470
Make use of the DP link training helpers to implement full and fast link training. While at it, refactor some of the code and remove various code sequences that are not necessary. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Add DisplayPort link training helperThierry Reding2-0/+524
Add a helper that will perform link training as described in the DisplayPort specification. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Add support for eDP link ratesThierry Reding2-0/+136
Parses additional link rates from DPCD if the sink supports eDP 1.4. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Add drm_dp_link_choose() helperThierry Reding2-0/+60
This helper chooses an appropriate configuration, according to the bitrate requirements of the video mode and the capabilities of the DisplayPort sink. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Enable alternate scrambler reset when supportedThierry Reding1-0/+7
If the sink is eDP and supports the alternate scrambler reset, enable it. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Set channel coding on link configurationThierry Reding1-1/+10
Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports it. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read AUX read interval from DPCDThierry Reding2-0/+42
Store the AUX read interval from DPCD, so that it can be used to wait for the durations given in the specification during link training. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read eDP version from DPCDThierry Reding2-2/+18
If the sink supports eDP, read the eDP revision from it's DPCD. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read alternate scrambler reset capability from sinkThierry Reding2-0/+12
Parse from the sink capabilities whether or not the eDP alternate scrambler reset value of 0xfffe is supported. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read channel coding capability from sinkThierry Reding2-0/+10
Parse from the sink capabilities whether or not it supports ANSI 8B/10B channel coding as specified in ANSI X3.230-1994, clause 11. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read TPS3 capability from sinkThierry Reding2-0/+10
The TPS3 capability can be exposed by DP 1.2 and later sinks if they support the alternative training pattern for channel equalization. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Read fast training capability from linkThierry Reding2-0/+10
While probing the DisplayPort link, query the fast training capability. If supported, drivers can use the fast link training sequence instead of the more involved full link training sequence. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Probe link using existing parsing helpersThierry Reding1-7/+6
Use existing parsing helpers to probe a DisplayPort link. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Turn link capabilities into booleansThierry Reding3-8/+36
Rather than storing capabilities as flags in an integer, use a separate boolean per capability. This simplifies the code that checks for these capabilities. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Track link capabilities alongside settingsThierry Reding4-28/+39
Store capabilities in max_* fields and add separate fields for the currently selected settings. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dp: Add drm_dp_link_reset() implementationThierry Reding1-1/+12
Subsequent patches will add non-volatile fields to struct drm_dp_link, so introduce a function to zero out only the volatile fields. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Add missing kerneldoc for struct drm_dp_linkThierry Reding1-0/+7
The drm_dp_link structure tracks capabilities on the DP link. Add some kerneldoc to explain what each of its fields means. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dpaux: Parameterize CMH, DRVZ and DRVIThierry Reding1-10/+38
The CMH, DRVZ and DRVI values vary depending on the SoC generation. Move them into SoC specific structures so that DT compatible string matching can be used to select the right parameters and write them to hardware at the right time. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dpaux: Fix crash if VDD supply is absentThierry Reding1-8/+14
In order to properly make the VDD supply optional, all accesses to the regulator need to be ignored, because the regulator core doesn't treat NULL special. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dpaux: Retry on transfer size mismatchThierry Reding1-7/+18
When a transfer didn't complete transmission of the requested number of bytes, signal that the transaction should be retried. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: dpaux: Support monitor hotpluggingThierry Reding1-18/+29
The dpaux driver has a quirk built-in that will delay initialization of the display driver for a short while, trying to detect an eDP panel. The reason for this quirk is that the panel may not report as connected until after the display driver has initialized, at which point the fbdev emulation will have fallen back to 1024x768 as default resolution, which will likely not be the eDP panel's native resolution. With upcoming DisplayPort support, the code needs to be able to cope with hotpluggable monitors as well. Waiting for a panel to show up is no longer going to work because the monitor may not be attached on boot. If the output runs in DisplayPort mode, skip waiting for the panel to show up. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: gem: Use sg_alloc_table_from_pages()Thierry Reding1-7/+2
Instead of manually creating the SG table for a discontiguous buffer, use the existing sg_alloc_table_from_pages(). Note that this is not safe to be used with the ARM DMA/IOMMU integration code because that will not ensure that the whole buffer is mapped contiguously. Depending on the size of the individual entries the mapping may end up containing holes to ensure alignment. However, we only ever use these buffers with explicit IOMMU API usage and know how to avoid these holes. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: gem: Always map SG tables for DMA-BUFsThierry Reding1-3/+3
When an importer wants to map a DMA-BUF, make sure to always actually map it, irrespective of whether the buffer is contiguous or not. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: gem: Use dma_get_sgtable()Thierry Reding1-4/+2
Rather than manually creating an SG table in an incorrect way, let the standard dma_get_sgtable() function do it. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: gem: Rename paddr -> iovaThierry Reding5-16/+16
The address can refer to either physical memory or IO virtual memory. If referring to IO virtual memory, there will always be an associated physical memory address. Rename this variable to "iova" to clarify in all cases that this is the IO virtual memory, which in the absence of an IOMMU is identical to the physical address. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Move IOMMU group into host1x clientThierry Reding7-40/+29
Handling of the IOMMU group attachment is common to all clients, so move the group into the client to simplify code. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: vic: Use common IOMMU attach/detach codeThierry Reding1-19/+8
Reuse common code to attach to or detach from an IOMMU domain. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: vic: Inherit DMA mask from host1xThierry Reding1-0/+7
VIC, just like all other host1x clients, has the same addressing range as its parent host1x device. Inherit the DMA mask to reflect that. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: vic: Skip stream ID programming without IOMMUThierry Reding1-3/+5
If VIC is not behind an IOMMU, don't touch any of the registers related to stream ID programming. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Use DRM_DEBUG_DRIVER for driver messagesThierry Reding1-4/+4
The driver-specific messages should use the DRM_UT_DRIVER category so that they can be properly filtered. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Inherit device DMA parameters from host1xThierry Reding2-0/+18
The display controllers and VIC don't have any limitations on the DMA segment size. Inherit the DMA parameters from the parent device, which also doesn't have any such limitations. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Make host1x_cdma_wait_pushbuffer_space() staticBen Dooks (Codethink)1-3/+3
The host1x_cdma_wait_pushbuffer_space() function is not declared or directly called from outside the file it is in, so make it static. Fixes the following sparse warning: drivers/gpu/host1x/cdma.c:235:5: warning: symbol 'host1x_cdma_wait_pushbuffer_space' was not declared. Should it be static? Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Request channels for clients, not devicesThierry Reding5-9/+11
A struct device doesn't carry much information that a channel might be interested in, but the client very much does. Request channels for the clients rather than their parent devices and store a pointer to them in order to have that information available when needed. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Explicitly initialize host1x_info structuresThierry Reding1-0/+12
It's technically not required to explicitly initialize the fields that will be zero by default, but it's easier to read these structures if they are all initialized uniformly. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Remove gratuitous blank lineThierry Reding1-1/+0
Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Do not limit DMA segment sizeThierry Reding3-1/+6
host1x nor any its clients have any limitations on the DMA segment size, so don't pretend that they do. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/fb-helper: Remove drm_fb_helper_defio_init() and update docsThomas Zimmermann1-48/+13
There are no users of drm_fb_helper_defio_init(), so we can remove it. The documentation around defio support is a bit misleading and should mention compatibility issues with SHMEM helpers. Clarify this. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Noralf Trønnes <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-27drm/i915/rps: Flip interpretation of ips fmin/fmax to max rpsChris Wilson1-3/+5
ips uses clock delays as opposed to rps frequency bins. To fit the delays into the same rps calculations, we need to invert the ips delays. Fixes: 3e7abf814193 ("drm/i915: Extract GT render power state management") Signed-off-by: Chris Wilson <[email protected]> Cc: Andi Shyti <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-27drm/i915: Put future HW and their uAPIs under STAGING & BROKENChris Wilson3-0/+28
We would like some freedom to break the user API/ABI for future HW but yet still expose the driver for upstream development on that HW. Currently, we have the i915.force_probe module parameter to avoid binding to HW while the driver is under development, but that is still a little too soft with respect to the stringent no-regression rules if we also plan to be redesigning the uAPI to go along with the new HW. To allow the uAPI to be changed during development, only expose that API and in development HW under STAGING (and BROKEN). Hopefully, making it explicit that such interfaces to that HW are under development and not to be blindly enabled by distributions. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Dave Airlie <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Split memory_region initialisation into its own fileChris Wilson6-74/+75
Pull the memory region bookkeeping into its file. Let's start clean and see how long it lasts! Signed-off-by: Chris Wilson <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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