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2024-06-14drm/amdgpu: add lock in amdgpu_gart_invalidate_tlbYunxiang Li1-1/+5
We need to take the reset domain lock before flush hdp. We can't put the lock inside amdgpu_device_flush_hdp itself because it is used during reset where we already take the write side lock. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: fix locking scope when flushing tlbYunxiang Li1-32/+34
Which method is used to flush tlb does not depend on whether a reset is in progress or not. We should skip flush altogether if the GPU will get reset. So put both path under reset_domain read lock. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> CC: [email protected]
2024-06-14drm/amdgpu: call flush_gpu_tlb directly in gfxhub enableYunxiang Li3-5/+7
Here since we are in reset and takes the reset_domain write side lock already. We can't use the flush tlb helper which tries to take the read side. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: use helper in amdgpu_gart_unbindYunxiang Li1-4/+1
When amdgpu_gart_invalidate_tlb helper is introduced this part was left out of the conversion. Avoid the code duplication here. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: remove tlb flush in amdgpu_gtt_mgr_recoverYunxiang Li1-2/+0
At this point the gart is not set up, there's no point to invalidate tlb here and it could even be harmful. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu/kfd: remove is_hws_hang and is_resettingYunxiang Li7-59/+45
is_hws_hang and is_resetting serves pretty much the same purpose and they all duplicates the work of the reset_domain lock, just check that directly instead. This also eliminate a few bugs listed below and get rid of dqm->ops.pre_reset. kfd_hws_hang did not need to avoid scheduling another reset. If the on-going reset decided to skip GPU reset we have a bad time, otherwise the extra reset will get cancelled anyway. remove_queue_mes forgot to check is_resetting flag compared to the pre-MES path unmap_queue_cpsch, so it did not block hw access during reset correctly. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: fix sriov host flr handlerYunxiang Li6-52/+50
We send back the ready to reset message before we stop anything. This is wrong. Move it to when we are actually ready for the FLR to happen. In the current state since we take tens of seconds to stop everything, it is very likely that host would give up waiting and reset the GPU before we send ready, so it would be the same as before. But this gets rid of the hack with reset_domain locking and also let us tell how slow ready to reset actually is from the host. The ready to reset speed can be improved later. Signed-off-by: Yunxiang Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: add skip_hw_access checks for sriovYunxiang Li1-0/+9
Accessing registers via host is missing the check for skip_hw_access and the lockdep check that comes with it. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: add reset source in various casesEric Huang3-0/+3
To fullfill the reset event description. Suggested-by: Lijo Lazar <[email protected]> Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: fix NULL pointer in amdgpu_reset_get_descEric Huang1-4/+2
amdgpu_job_ring may return NULL, which causes kernel NULL pointer error, using another way to print ring name instead of ring->name. Suggested-by: Lijo Lazar <[email protected]> Signed-off-by: Eric Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: dc 3.2.287Aric Cyr1-1/+1
This version brings the following changes: - Add sequential ONO sequencing for DCN35 - Add new GPINT command definitions - reduce ODM slice count to initial new dc state only when needed - Enable copying of bounding box data from VBIOS DMUB - Guard reading 3DLUT registers for dcn32/dcn35 Reviewed-by: Zaeem Mohamed <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix DSC slice and delay calculationsSung Joon Kim3-18/+29
[why] There are other factors that determine the number of DSC slices. The slices should not be determined in DML but retrieve the value calculated from driver. [how] Update the logic to determine DSC slice. Make DSCDelay per display pipe. Reviewed-by: Jun Lei <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Increase MAX_LINKS by 2Alex Hung1-1/+1
Two additional virtual links are created and thus increasing size for dc->links by two. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35Nicholas Kazlauskas1-14/+15
[Why] 3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers now exist in MCM state. [How] Add guards when reading DPP state based on whether the register has a valid offset. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Various DML2 fixes for FAMS2Dillon Varone6-38/+11
- Ensure SubVP stream settings match ODM policy - Fix MALL size calculations when DCC is enabled - Fail if any stream fails DRR policy check Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Program DIG FE source select for DVI before PHY enAlvin Lee1-1/+1
[Description] In newer DCN's the programming of SYMCLK_FE_SRC_SEL depends on the value of DIG_FE_SOURCE_SELECT. If DIG_FE_SOURCE_SELECT is not already programmed at the time of PHY / DIG enable then the FW sequence will program an incorrect SYMCLK source. Ensure that we program DIG_FE_SOURCE_SELECT for all DIO scenarios (DVI in this particular case) before going through the PHY / DIG enable sequence. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/pm: remove dead code in navi10_emit_clk_levels and ↵Jesse Zhang1-4/+0
navi10_print_clk_levels Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Yang Wang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: remove dead code in atom_get_src_intJesse Zhang1-4/+4
Since the range of align is 0~7, the expression is: align = (attr >> 3) & 7. In the case of ATOM_ARG_IMM, the code cannot reach the default case. So there is no need for "break". Signed-off-by: Jesse Zhang <[email protected]> Suggested-by: Tim Huang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Introduce deferred Replay coasting vtotal updateChunTao Tso3-0/+21
Add functions to defer updating of coasting vtotal after source refresh rate update. Reviewed-by: Robin Chen <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: ChunTao Tso <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add NULL check for 'afb' before dereferencing in ↵Srinivasan Shanmugam1-4/+12
amdgpu_dm_plane_handle_cursor_update This commit adds a null check for the 'afb' variable in the amdgpu_dm_plane_handle_cursor_update function. Previously, 'afb' was assumed to be null, but was used later in the code without a null check. This could potentially lead to a null pointer dereference. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1298 amdgpu_dm_plane_handle_cursor_update() error: we previously assumed 'afb' could be null (see line 1252) Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add null check for 'afb' in amdgpu_dm_update_cursorSrinivasan Shanmugam1-4/+12
This commit adds a null check for the 'afb' variable in the amdgpu_dm_update_cursor function. Previously, 'afb' was assumed to be null at line 8388, but was used later in the code without a null check. This could potentially lead to a null pointer dereference. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8433 amdgpu_dm_update_cursor() error: we previously assumed 'afb' could be null (see line 8388) drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c 8379 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 8380 struct drm_plane_state *old_plane_state, 8381 struct dc_stream_update *update) 8382 { 8383 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8384 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8385 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; ^^^^^ 8386 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8388 uint64_t address = afb ? afb->address : 0; ^^^^^ Checks for NULL 8389 struct dc_cursor_position position = {0}; 8390 struct dc_cursor_attributes attributes; 8391 int ret; 8392 8393 if (!plane->state->fb && !old_plane_state->fb) 8394 return; 8395 8396 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 8397 amdgpu_crtc->crtc_id, plane->state->crtc_w, 8398 plane->state->crtc_h); 8399 8400 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 8401 if (ret) 8402 return; 8403 8404 if (!position.enable) { 8405 /* turn off cursor */ 8406 if (crtc_state && crtc_state->stream) { 8407 dc_stream_set_cursor_position(crtc_state->stream, 8408 &position); 8409 update->cursor_position = &crtc_state->stream->cursor_position; 8410 } 8411 return; 8412 } 8413 8414 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8415 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8416 8417 memset(&attributes, 0, sizeof(attributes)); 8418 attributes.address.high_part = upper_32_bits(address); 8419 attributes.address.low_part = lower_32_bits(address); 8420 attributes.width = plane->state->crtc_w; 8421 attributes.height = plane->state->crtc_h; 8422 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8423 attributes.rotation_angle = 0; 8424 attributes.attribute_flags.value = 0; 8425 8426 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 8427 * legacy gamma setup. 8428 */ 8429 if (crtc_state->cm_is_degamma_srgb && 8430 adev->dm.dc->caps.color.dpp.gamma_corr) 8431 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 8432 --> 8433 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; ^^^^^ ^^^^^ Unchecked dereferences 8434 8435 if (crtc_state->stream) { 8436 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8437 &attributes)) 8438 DRM_ERROR("DC failed to set cursor attributes\n"); 8439 8440 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 8441 8442 if (!dc_stream_set_cursor_position(crtc_state->stream, 8443 &position)) 8444 DRM_ERROR("DC failed to set cursor position\n"); 8445 8446 update->cursor_position = &crtc_state->stream->cursor_position; 8447 } 8448 } Fixes: 66eba12a5482 ("drm/amd/display: Do cursor programming with rest of pipe") Reported-by: Dan Carpenter <[email protected]> Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add monitor patch skip disable crtc during psr and ips1Lewis Huang3-1/+6
[Why] For some panel, it cannot handle pseudo vblank set by otg resync when leave psr [How] The monitor patch will keep otg_on during enter IPS1. And then we don't need to do otg resync when wake up. Reviewed-by: Duncan Ma <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: add set ips disableChiawen Huang2-0/+12
[How&Why] Once IPS active, all the DCN resources are not be allowed to access. It needs to a function for 3rd party to on/off IPS. Reviewed-by: Duncan Ma <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chiawen Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add recovery timeout to FAMS2Dillon Varone2-0/+2
[WHY&HOW] Add 5ms timeout to trigger recovery and force allow P-State in DMUB. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Force max clocks unconditionally when p-state is unsupportedDillon Varone1-16/+20
[WHY&HOW] UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update to SMU. When this happens, the UCLK provided should be max if switching is unsupported. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Change the order of setting DP_IS_USB_C flagWayne Lin1-7/+3
[Why] enc10->base.features.flags.bits.DP_IS_USB_C will be overwritten if we set it before initializing enc10->base.features [How] Determine DP_IS_USB_C after enc10->base.features is initialized. Besides, bp_cap_info.DP_IS_USB_C will never be set in get_connector_speed_cap_info(). Remove the redudant code. Reviewed-by: Roman Li <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: bypass ODM before CRTC offYihan Zhu1-0/+11
[WHY] OPPs couldn't disconnect from the ODM that cause the double buffer pending not being latched due to missing VUPDATE. [HOW] Moving memory blanking before OTG turn off to make sure double buffer latched correctly. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display/dcn401: use pre-allocated temp structure for bounding boxAlex Deucher2-14/+7
This mirrors what the driver does for older DCN generations. Should fix: [ 26.924055] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 [ 26.924060] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1022, name: modprobe [ 26.924063] preempt_count: 2, expected: 0 [ 26.924064] RCU nest depth: 0, expected: 0 [ 26.924066] Preemption disabled at: [ 26.924067] [<ffffffffc089e5e0>] dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924322] CPU: 9 PID: 1022 Comm: modprobe Not tainted 6.8.0+ #20 [ 26.924325] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 26.924326] Call Trace: [ 26.924327] <TASK> [ 26.924329] dump_stack_lvl+0x37/0x50 [ 26.924333] ? dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924589] dump_stack+0x10/0x20 [ 26.924592] __might_resched+0x16a/0x1c0 [ 26.924596] __might_sleep+0x42/0x70 [ 26.924598] __kmalloc_node_track_caller+0x2ad/0x4b0 [ 26.924601] ? dm_helpers_allocate_gpu_mem+0x12/0x20 [amdgpu] [ 26.924855] ? dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925122] kmemdup+0x20/0x50 [ 26.925124] ? kernel_fpu_begin_mask+0x6b/0xe0 [ 26.925127] ? kmemdup+0x20/0x50 [ 26.925129] dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925393] dc_create+0x311/0x670 [amdgpu] [ 26.925649] amdgpu_dm_init+0x2aa/0x1fa0 [amdgpu] [ 26.925903] ? irq_work_queue+0x38/0x50 [ 26.925907] ? vprintk_emit+0x1e7/0x270 [ 26.925910] ? dev_printk_emit+0x83/0xb0 [ 26.925914] ? amdgpu_device_rreg+0x17/0x20 [amdgpu] [ 26.926133] dm_hw_init+0x14/0x30 [amdgpu] v2: drop extra memcpy Fixes: 669d6b078ed8 ("drm/amd/display: avoid large on-stack structures") Reviewed-by: Harry Wentland <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Suggested-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: George Zhang <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2024-06-14drm/amd/display: use pre-allocated temp structure for bounding boxAlex Deucher3-12/+5
This mirrors what the driver does for older DCN generations. Should fix: BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 449, name: kworker/u64:8 preempt_count: 2, expected: 0 RCU nest depth: 0, expected: 0 Preemption disabled at: ffffffffc0ce1580>] dc_fpu_begin+0x30/0xd0 [amdgpu] CPU: 5 PID: 449 Comm: kworker/u64:8 Tainted: G W 6.8.0+ #35 Hardware name: System manufacturer System Product Name/ROG STRIX X570-E GAMING WIFI II, BIOS 4204 02/24/2022 Workqueue: events_unbound async_run_entry_fn v2: drop extra memcpy Fixes: 88c61827cedc ("drm/amd/display: dynamically allocate dml2_configuration_options structures") Reviewed-by: Harry Wentland <[email protected]> Tested-by: George Zhang <[email protected]> (v1) Suggested-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: George Zhang <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2024-06-14drm/amdgpu: add sdma 7.0 support for copy dcc bufferFrank Min4-4/+27
1. Add dcc buffer flag for copy buffer 2. Add sdma 7.0 support copy dcc buffer Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Frank Min <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: support for DCC featureLikun Gao2-0/+9
Deal with AMDGPU_GEM_CREATE_GFX12_DCC to set DCC bit when needed. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: add additional VM bitsAlex Deucher1-0/+1
Add additional VM PTE bits. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Simplify if conditionsThorsten Blum2-4/+4
The if conditions !A || A && B can be simplified to !A || B. Fixes the following Coccinelle/coccicheck warnings reported by excluded_middle.cocci: WARNING !A || A && B is equivalent to !A || B WARNING !A || A && B is equivalent to !A || B WARNING !A || A && B is equivalent to !A || B Compile-tested only. Signed-off-by: Thorsten Blum <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Extend PSRSU residency modeJack Chang7-7/+23
1. To support multiple PSRSU residency measurement mode Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Jack Chang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add outbox notification support for HPD redetectNicholas Kazlauskas3-0/+32
[Why] HPD sense changes can occur during low power states and need to be notified from firmware to driver. Upon notification the hotplug redetection routines should execute. [How] Add Support in DMUB srv and DMUB srv stat for receiving these notifications. DM can hook them up and process the HPD redetection once received. Reviewed-by: Duncan Ma <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/ci: mark kms_addfb_basic@addfb25-bad-modifier as passing on msmDmitry Baryshkov2-2/+0
The commit b228501ff183 ("drm/msm: merge dpu format database to MDP formats") made get_format take modifiers into account. This makes kms_addfb_basic@addfb25-bad-modifier pass on MDP4 and MDP5 platforms. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Acked-by: Helen Koike <[email protected]> Signed-off-by: Helen Koike <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240613-msm-pass-addfb25-bad-modifier-v1-1-23c556e96c8a@linaro.org
2024-06-14drm/i915: Remove bogus MST check in intel_dp_has_audio()Ville Syrjälä1-4/+2
No idea what this MST checks is doing in intel_dp_has_audio(). Looks completely pointless, so get rid of it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Utilize edp_disable_dsc from VBTVille Syrjälä3-0/+9
Disable eDP DSC usage when instructed to do so by the VBT. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Reuse intel_dp_supports_dsc() for MSTVille Syrjälä3-16/+7
intel_dp_supports_dsc() now works for MST as well, reuse it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Use intel_dp_has_dsc() during .compute_config()Ville Syrjälä1-2/+4
Reuse intel_dp_has_dsc() during .compute_config() instead of repeating some of the checks again by hand. We'll be adding more checks to intel_dp_has_dsc() and this will make sure we cover both .mode_valid() and .compute_config() with them. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Handle MST in intel_dp_has_dsc()Ville Syrjälä3-3/+6
Utilize intel_dp_has_dsc() for MST as well. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Extract intel_dp_has_dsc()Ville Syrjälä1-2/+14
Extract a helper to check whether the source+sink combo supports DSC. That basic check is needed both during mode validation and compute config. We'll also need to add extra checks to both places, so having a single place for it is nicer. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: Drop redundant dsc_decompression_aux checkVille Syrjälä1-1/+0
If we have no dsc_decompression_aux (only possible on MST) then we won't have the dsc_dpcd caps either. So checking both is not needed. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-14drm/panel-edp: drop several legacy panelsDmitry Baryshkov1-166/+7
The panel-edp driver supports legacy compatible strings for several eDP panels which were never used in DT files present in Linux tree and most likely have never been used with the upstream kernel. Drop compatibles for these panels in favour of using a generic "edp-panel" device on the AUX bus. Reviewed-by: Douglas Anderson <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2024-06-14drm/panel-edp: add fat warning against adding new panel compatiblesDmitry Baryshkov1-1/+18
Add a fat warning against adding new panel compatibles to the panel-edp driver. All new users of the eDP panels are supposed to use the generic "edp-panel" compatible device on the AUX bus. The remaining compatibles are either used by the existing DT or were used previously and are retained for backwards compatibility. Suggested-by: Doug Anderson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2024-06-14drm/i915: remove unused pipe/plane B register macrosJani Nikula1-21/+0
None of these are used. The parametrized register macros all depend on the pipe/plane A offset macros alone. Remove the unused ones. v2: Rebase Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/16d278bea466a69cdce94fd83d98dd15ce1a8c89.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-14drm/i915: relocate some DSPCNTR reg bit definitionsJani Nikula2-2/+2
Some plane B/C specific bits were left next to the unused _DSPBCNTR macro. Move them next to the DSPCNTR() macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/85409fbe5073797c0dc17df43eeb25abe9ff889f.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-14drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE()Jani Nikula1-2/+2
Do not rely on having dev_priv local variable, pass it to the macro. Cc: Zhenyu Wang <[email protected]> Cc: Zhi Wang <[email protected]> Cc: [email protected] Reviewed-by: Zhi Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/2ff78ebd0dc84178f5feacee7ef2a6cb4132b9ae.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-14drm/i915/gvt: rename range variable to strideJani Nikula1-2/+2
Range is a bit odd name for what really is stride. Rename. Switch to u32 while at it. Cc: Zhenyu Wang <[email protected]> Cc: Zhi Wang <[email protected]> Cc: [email protected] Reviewed-by: Zhi Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8b8d4acee15da07845ed1779d6856d5c3f50a132.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-14drm/i915/gvt: use proper i915_reg_t for calc_index() parametersJani Nikula1-8/+10
In order to be able to use the proper register macros instead of the underscore prefixed ones, pass i915_reg_t for the calc_index() parameters. Side note: DSPSURF is really about planes, not pipes. Fixed stride doesn't work for plane C for CHV (but that's okay for gvt). This doesn't support planes beyond C either. But all that is unrelated to the change at hand. Cc: Zhenyu Wang <[email protected]> Cc: Zhi Wang <[email protected]> Cc: [email protected] Reviewed-by: Zhi Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/282b19c44d83c96b52c261cfc7218e7e54076cba.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
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