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This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni <[email protected]>
Reviewed-by: James Ausmus <[email protected]>
Signed-off-by: Mahesh Kumar <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.
This patch removes the PLANE_NV12_BUF_CFG write for ICL.
Changes Since V1:
- Improve commit message as per Paulo's comment
Reviewed-by: Paulo Zanoni <[email protected]>
Reviewed-by: James Ausmus <[email protected]>
Signed-off-by: Mahesh Kumar <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo):
- Coding style issue.
Changes since v5 (from Paulo):
- Do the final checks according to BSpec.
Reviewed-by: Paulo Zanoni <[email protected]>
Signed-off-by: Mahesh Kumar <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it compile.
- Fix a few coding style issues.
v3:
- Rebase on top of upstream patches
v4 (from Paulo):
- Bikeshed if statements (James).
Reviewed-by: Paulo Zanoni <[email protected]>
Reviewed-by: James Ausmus <[email protected]>
Signed-off-by: Mahesh Kumar <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already says.
Reviewed-by: Paulo Zanoni <[email protected]>
Reviewed-by: James Ausmus <[email protected]>
Signed-off-by: Mahesh Kumar <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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* pci/virtualization:
PCI: Expose ari_enabled in sysfs
PCI: Add function 1 DMA alias quirk for Marvell 9128
PCI: Mark Ceton InfiniTV4 INTx masking as broken
xen/pci: Use acpi_noirq_set() helper to avoid #ifdef
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* pci/trivial:
PCI: Clean up whitespace in linux/pci.h, pci/pci.h
PCI: Tidy up pci/probe.c comments
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* pci/switchtec:
switchtec: Add device IDs for PSX 24xG3 and PSX 48xG3
switchtec: Add Global Fabric Manager Server (GFMS) event
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* pci/resource:
PCI: tegra: Remove PCI_REASSIGN_ALL_BUS use on Tegra
resource: Set type when reserving new regions
resource: Set type of "reserve=" user-specified resources
irqchip/i8259: Set I/O port resource types correctly
powerpc: Set I/O port resource types correctly
MIPS: Set I/O port resource types correctly
vgacon: Set VGA struct resource types
PCI: Use dev_info() rather than dev_err() for ROM validation
PCI: Remove PCI_REASSIGN_ALL_RSRC use on arm and arm64
PCI: Remove sysfs resource mmap warning
Conflicts:
drivers/pci/rom.c
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* pci/msi:
PCI: Disable MSI for HiSilicon Hip06/Hip07 only in Root Port mode
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* pci/misc:
PCI: Add dummy pci_irqd_intx_xlate() for CONFIG_PCI=n build
PCI: Add wrappers for dev_printk()
PCI: Remove unnecessary messages for memory allocation failures
PCI: Add #defines for Completion Timeout Disable feature
hinic: Replace PCI pool old API
net: e100: Replace PCI pool old API
block: DAC960: Replace PCI pool old API
MAINTAINERS: Include more PCI files
PCI: Remove unneeded kallsyms include
powerpc/pci: Unroll two pass loop when scanning bridges
powerpc/pci: Use for_each_pci_bridge() helper
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* pci/hotplug:
PCI: pciehp: Assume NoCompl+ for Thunderbolt ports
PCI: hotplug: Drop checking of PCI_BRIDGE_CONTROL in *_unconfigure_device()
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* pci/enumeration:
RDMA/qedr: Use pci_enable_atomic_ops_to_root()
PCI: Add pci_enable_atomic_ops_to_root()
PCI: Make PCI_SCAN_ALL_PCIE_DEVS work for Root as well as Downstream Ports
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* pci/dt-resources:
PCI: Make of_irq_parse_pci() static
powerpc/pci: Use of_irq_parse_and_map_pci() helper
PCI: Move OF-related PCI functions into PCI core
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* pci/dpc:
PCI/DPC: Reformat DPC register definitions
PCI/DPC: Add and use DPC Status register field definitions
PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error()
PCI/DPC: Remove unnecessary RP PIO register structs
PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info()
PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info()
PCI/DPC: Make RP PIO log size check more generic
PCI/DPC: Rename local "status" to "dpc_status"
PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error()
PCI/DPC: Process RP PIO details only if RP PIO extensions supported
PCI/DPC: Read RP PIO Log Size once at probe
PCI/DPC: Rename struct dpc_dev.rp to rp_extensions
PCI/DPC: Add local variable for DPC capability offset
PCI/DPC: Rename interrupt_event_handler() to dpc_work()
PCI/DPC: Fix interrupt message number print
PCI/DPC: Enable DPC only if AER is available
PCI/DPC: Fix shared interrupt handling
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* pci/dma:
PCI: Remove NULL device handling from PCI DMA API
net: tsi108: Use DMA API properly
media: ttusb-dec: Remove pci_zalloc_coherent() abuse
media: ttusb-budget: Remove pci_zalloc_coherent() abuse
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* pci/deprecate-get-bus-and-slot:
video: fbdev: riva: deprecate pci_get_bus_and_slot()
video: fbdev: nvidia: deprecate pci_get_bus_and_slot()
video: fbdev: intelfb: deprecate pci_get_bus_and_slot()
openprom: Deprecate pci_get_bus_and_slot()
xen/pcifront: Deprecate pci_get_bus_and_slot()
PCI: Deprecate pci_get_bus_and_slot()
PCI: ibmphp: Deprecate pci_get_bus_and_slot()
PCI: cpqhp: Deprecate pci_get_bus_and_slot()
pch_gbe: Deprecate pci_get_bus_and_slot()
bnx2x: Deprecate pci_get_bus_and_slot()
powerpc/via-pmu: Deprecate pci_get_bus_and_slot()
iommu/amd: Deprecate pci_get_bus_and_slot()
sl82c105: deprecate pci_get_bus_and_slot()
drm/nouveau: deprecate pci_get_bus_and_slot()
drm/gma500: Deprecate pci_get_bus_and_slot()
ibft: Deprecate pci_get_bus_and_slot()
edd: Deprecate pci_get_bus_and_slot()
agp: sworks: Deprecate pci_get_bus_and_slot()
agp: nvidia: Deprecate pci_get_bus_and_slot()
ata: Deprecate pci_get_bus_and_slot()
x86/PCI: Deprecate pci_get_bus_and_slot()
powerpc/PCI: Deprecate pci_get_bus_and_slot()
alpha/PCI: Deprecate pci_get_bus_and_slot()
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* pci/aspm:
PCI/ASPM: Unexport internal ASPM interfaces
PCI/ASPM: Enable Latency Tolerance Reporting when supported
PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics
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Driver check the wrong register bit in rtl_ocp_tx_cond() that keep driver
waiting until timeout.
Fix this by waiting for the right register bit.
Signed-off-by: Chunhao Lin <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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The Quectel EP06 is a Cat. 6 LTE modem. It uses the same interface as
the EC20/EC25 for QMI, and requires the same "set DTR"-quirk to work.
Signed-off-by: Kristian Evensen <[email protected]>
Acked-by: Bjørn Mork <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Pull assorted small fixes queued for merge window.
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Pull Wacom device driver updates. These don't have to go on top of the
hid_have_special_driver[] revamp, as the whole group is assumed to
have a special driver based on VID.
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Pull hid-elo device detection fix
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'for-4.16/hid-quirks-cleanup/elecom', 'for-4.16/hid-quirks-cleanup/ish', 'for-4.16/hid-quirks-cleanup/multitouch', 'for-4.16/hid-quirks-cleanup/pixart', 'for-4.16/hid-quirks-cleanup/rmi', 'for-4.16/hid-quirks-cleanup/sony' and 'for-4.16/hid-quirks-cleanup/toshiba' into for-linus
Pull assorted device driver fixes (ASUS, Elecom, Intel-ISH, Multitouch, PixArt, RMI,
Sony and Toshiba) based on top the hid-quirks revamp.
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This series from Benjamin Tissoires finally removes one of the big PITAs
in the hid-core, which is the absolute need of having added all the new
device IDs into the horrid hid_have_special_driver[]
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This patch adds support to the Cadence PCIe controller in endpoint mode.
Since pieces of source code are shared with the host driver (Root
Complex mode), we create a new directory under drivers/pci dedicated to
the Cadence PCIe controller. The common code is placed into
drivers/pci/cadence/pcie-cadence.c and used by both the host and
endpoint controller drivers.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Fix the pci_epf_make() function so it can now bind many EPF devices to the
same EPF driver.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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This patchs moves generic source code from
drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.
Indeed the extracted lines of code were duplicated by many host
controller drivers. Regrouping them into a generic function gives a
change to properly share this code without introducing a useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Clean up drivers/Makefile by moving the pci/endpoint and pci/dwc entries
from drivers/Makefile into drivers/pci/Makefile.
Since we don't want to introduce any dependency between CONFIG_PCI and
CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile.
Hence all Makefiles in drivers/pci/ were updated accordingly so no file is
compiled when CONFIG_PCI is not defined.
Also, we add a comment to reinforce that EPC and EPF libraries must be
initialized before their users. Hence built-in EPC drivers, such as
those of Designware, are linked after the endpoint core libraries.
Finally, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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This is a precautionary measure as I have no evidence to suggest we've
hit a bug here (I was hoping this might explain gdg's odd behaviour, but
alas), but given that we have a function to flush the ggtt writes it
seems prudent to use it prior to changing the fence register. Due to the
intrinsic nature of the GTT often operating as an independent mmio path,
we should not just rely on the write to the fence acting as a full flush
for GTT writes.
Signed-off-by: Chris Wilson <[email protected]>
Cc: Joonas Lahtinen <[email protected]>
Reviewed-by: Joonas Lahtinen <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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guc_log_relay_file_create will return -EEXIST if we invoke
relay_late_setup_files multiple times as part of i915_guc_log_control.
However this is to be not cosidered as fail and need to return 0.
This was mistakenly introduced in the below commit. Fix it.
Fixes: 70deeaddc6e6 "drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex"
Signed-off-by: Sagar Arun Kamble <[email protected]>
Cc: Chris Wilson <[email protected]>
Cc: Michal Wajdeczko <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Chris Wilson <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
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If NO_DMA=y:
ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_sys_dmac.ko] undefined!
ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_internal_dmac.ko] undefined!
Add dependencies on HAS_DMA to fix this.
Fixes: e578afab6e5f57e7 ("mmc: renesas_sdhi: remove wrong depends on to enable compile test")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The bounce buffer is gone from the MMC core, and now we found out
that there are some (crippled) i.MX boards out there that have broken
ADMA (cannot do scatter-gather), and also broken PIO so they must
use SDMA. Closer examination shows a less significant slowdown
also on SDMA-only capable Laptop hosts.
SDMA sets down the number of segments to one, so that each segment
gets turned into a singular request that ping-pongs to the block
layer before the next request/segment is issued.
Apparently it happens a lot that the block layer send requests
that include a lot of physically discontiguous segments. My guess
is that this phenomenon is coming from the file system.
These devices that cannot handle scatterlists in hardware can see
major benefits from a DMA-contiguous bounce buffer.
This patch accumulates those fragmented scatterlists in a physically
contiguous bounce buffer so that we can issue bigger DMA data chunks
to/from the card.
When tested with a PCI-integrated host (1217:8221) that
only supports SDMA:
0b:00.0 SD Host controller: O2 Micro, Inc. OZ600FJ0/OZ900FJ0/OZ600FJS
SD/MMC Card Reader Controller (rev 05)
This patch gave ~1Mbyte/s improved throughput on large reads and
writes when testing using iozone than without the patch.
dmesg:
sdhci-pci 0000:0b:00.0: SDHCI controller found [1217:8221] (rev 5)
mmc0 bounce up to 128 segments into one, max segment size 65536 bytes
mmc0: SDHCI controller on PCI [0000:0b:00.0] using DMA
On the i.MX SDHCI controllers on the crippled i.MX 25 and i.MX 35
the patch restores the performance to what it was before we removed
the bounce buffers.
Cc: Pierre Ossman <[email protected]>
Cc: Benoît Thébaudeau <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Benjamin Beckmeyer <[email protected]>
Cc: [email protected] # v4.14+
Fixes: de3ee99b097d ("mmc: Delete bounce buffer handling")
Tested-by: Benjamin Beckmeyer <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Previously, we relied on only running the hangcheck while somebody was
waiting on the GPU, in order to minimise the amount of time hangcheck
had to run. (If nobody was watching the GPU, nobody would notice if the
GPU wasn't responding -- eventually somebody would care and so kick
hangcheck into action.) However, this falls apart from around commit
4680816be336 ("drm/i915: Wait first for submission, before waiting for
request completion"), as not all waiters declare themselves to hangcheck
and so we could switch off hangcheck and miss GPU hangs even when
waiting under the struct_mutex.
If we enable hangcheck from the first request submission, and let it run
until the GPU is idle again, we forgo all the complexity involved with
only enabling around waiters. We just have to remember to be careful that
we do not declare a GPU hang when idly waiting for the next request to
be come ready, as we will run hangcheck continuously even when the
engines are stalled waiting for external events. This should be true
already as we should only be tracking requests submitted to hardware for
execution as an indicator that the engine is busy.
Fixes: 4680816be336 ("drm/i915: Wait first for submission, before waiting for request completion"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104840
Signed-off-by: Chris Wilson <[email protected]>
Cc: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Mika Kuoppala <[email protected]>
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Don't let a lessee control what the current DRM master is set to;
that's the job of the "real" master. Otherwise, the lessee would
disable all access to master operations for the owner and all lessees
under it.
This matches the same check made in the SET_MASTER ioctl.
Signed-off-by: Keith Packard <[email protected]>
Fixes: 2ed077e467ee ("drm: Add drm_object lease infrastructure [v5]")
Cc: <[email protected]> # v4.15+
Signed-off-by: Daniel Vetter <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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