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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Used PCI configure space read to flush PCI function reset register write
Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Fixed system panic when extents enabled with large number of small blocks
Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Alex Iannicelli <[email protected]>
Signed-off-by: James Smart <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Adapt comment and printk string after renaming sd_init_command to sd_prep_fn
Adapt comment and printk string after renaming sd_attach to sd_probe
Signed-off-by: Petr Uzel <[email protected]>
Acked-by: Hannes Reinecke <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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This patch adds support for Universal Flash Storage(UFS)
host controllers. The UFS host controller driver
includes host controller initialization method.
The Initialization process involves following steps:
- Initiate UFS Host Controller initialization process by writing
to Host controller enable register
- Configure UFS Host controller registers with host memory space
datastructure offsets.
- Unipro link startup procedure
- Check for connected device
- Configure UFS host controller to process requests
- Enable required interrupts
- Configure interrupt aggregation
[jejb: fix warnings in 32 bit compile]
Signed-off-by: Santosh Yaraganavi <[email protected]>
Signed-off-by: Vinayak Holikatti <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
Reviewed-by: Vishak G <[email protected]>
Reviewed-by: Girish K S <[email protected]>
Reviewed-by: Namjae Jeon <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Signed-off-by: Petr Uzel <[email protected]>
Acked-by: Vikas Chaudhary <[email protected]>
Signed-off-by: James Bottomley <[email protected]>
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Following commit broke DT support for tegra-kbc by removing pdata
allocation completely:
commit 023cea0ecfa2df034096c3f4afa796a0b2d1188a
Author: Shridhar Rasal <[email protected]>
Date: Fri Feb 3 00:27:30 2012 -0800
Input: tegra-kbc - allow skipping setting up some of GPIO pins
This patch restores it.
Signed-off-by: Viresh Kumar <[email protected]>
Signed-off-by: Dmitry Torokhov <[email protected]>
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Move linux specific module parameter gts and bfs out of ACPICA core
code to sleep.c.
Signed-off-by: Lin Ming <[email protected]>
Signed-off-by: Len Brown <[email protected]>
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Enhanced the sleep/wake interfaces to optionally execute the
_GTS method (Going To Sleep), and the _BFS method (Back From
Sleep). Windows apparently does not execute these methods, and
therefore these methods are often untested. It has been seen on
some systems where the execution of these methods causes errors
and also prevents the machine from entering S5. It is therefore
suggested that host operating systems do not execute these methods
by default. In the future, perhaps these methods can be optionally
executed based on the age of the system and/or what is the newest
version of Windows that the BIOS asks for via _OSI.
Signed-off-by: Lin Ming <[email protected]>
Signed-off-by: Bob Moore <[email protected]>
Signed-off-by: Len Brown <[email protected]>
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As docg3 is intolerant against reentrancy, especially
because of its weird register access (ie. a register read is
performed by a first register write), each access to the
docg3 IO space must be locked.
Lock the IO space with a mutex, shared by all chips on the
same cascade, as they all share the same IO space.
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Group floors into a common cascade structure. This will provide a common
structure to store common data to all cascaded docg3 chips, like IO
addressing, locking protection.
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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After several tries with ubifs, it appears empirically that constructor
provided figures for erase/write timeouts are underestimated. A timeout
of 100ms seems to work with a 5 years worn chip, and no timeouts occur
anymore.
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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The last erase block was not accessible, as the out of bound
check was incorrectly rejecting the last block.
The read/write/erase offset checks were forbidding the usage of the
last block, because of the calculation which was considering the
byte after the last instead of the last byte.
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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A lot of functions have been marked __devinit, but they shouldn't, because they
are needed for bbt_scan. While I believe the whole MX23 handling should be done
entirely different, I am missing the resources to fix it. So, let's have at least
the annotations correct.
Signed-off-by: Wolfram Sang <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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phram_setup() is only called from init_phram() which is in .init.text,
so it must be in the same section to avoid a section mismatch warning.
Signed-off-by: Ryosuke Saito <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Initialization of 'erase_info->fail_addr' to MTD_FAIL_ADDR_UNKNOWN prior
erase operation is duplicated accross several MTD drivers, and also taken
care of by some MTD users as well.
Harmonize it: initialize 'fail_addr' within 'mtd_erase()' interface.
Signed-off-by: Shmulik Ladkani <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
Signed-off-by: Matthieu Castet <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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major == 0 allocates dynamic major, not major == -1
Signed-off-by: Maxim Levitsky <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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This patch adds support to configure the SPEAr SMI driver via
device-tree instead of platform_data.
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Additionally, after failing in mtd_device_parse_register(), the driver
unmap/free code is now executed.
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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This patch adds support to configure the FSMC NAND driver (used amongst
others on SPEAr platforms) via device-tree instead of platform_data.
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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doc_probe_device() is only called from docg3_probe() which is in .init.text,
so it must be in the same section to avoid a section mismatch warning.
Signed-off-by: Ryosuke Saito <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
because of two reasons
- the cpu gets locked on AHB bus while reading from NAND
- the cpu is unnecessarily used when dma can do the job
This patch adds the support for accessing the device through DMA
Signed-off-by: Vipin Kumar <[email protected]>
Reviewed-by: Viresh Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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The default way of accessing nand device is using the nand width. This means
that 8bit devices are using u8 * and 16bit devices are accessed using u16 *.
This results in a non-optimal performance since the FSMC is designed to
translate the normal word accesses into device width based accesses. This patch
implements read_buf and write_buf callbacks using word by word accesses.
Signed-off-by: Vipin Kumar <[email protected]>
Reviewed-by: Viresh Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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fsmc controller takes time to calculate the bch8 codes and the error offsets.
The calculate logic checks for completion upto a timeout. This patch adds a
error print when this timer expires and the ecc or error offsets are not yet
calculated.
Signed-off-by: Vipin Kumar <[email protected]>
Reviewed-by: Viresh Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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fsmc_nand driver currently uses normal kzalloc, request_mem etc routines. This
patch replaces these routines with devm_kzalloc and devm_request_mem_region etc.
Consequently, the error and driver removal scenarios are curtailed.
Signed-off-by: Vipin Kumar <[email protected]>
Reviewed-by: Viresh Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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FSMC controllers provide registers to program the required timing values for
attached NAND device. The timing values used until now are relaxed and should
work for all devices.
Although, for read/write performance improvements, the fsmc nand driver should
accept nand timings as a platform data and program the timing parameters into
fsmc registers accordingly.
This patch implements this modification. Additionally, it programs the default
timing parameters if these are not passed via platform data.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Ideally, the block should have 0xff written on the bad block position. Any value
other than 0xff implies a bad block. In practical situations, there can be
bit flips in the oob area as well which means that a block with 0x7f being read
at bad block position may imply a bad block but it is infact only a bit flip in
the bad block byte.
To resolve this problem, the block is marked as good if number of high bits is
greater than or equal to badblockbits (initialized to 7)
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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ECC can correct up to 8 bits in 512 bytes data + 13 bytes ecc. This means that
the algorithm can correct a max of 8 bits in 4200 bits ie the error indices can
be from 0 to 4199. Of these 0 to 4095 are for data and 4096 to 4199 for ecc.
The driver flips the bit only if the index is <= 4096. This is a bug since the
data bits are only from 0 to 4095.
This patch modifies the check as < 4096
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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The ECC logic of FSMC works on 512 bytes data + 13 bytes ECC to generate error
indices of up to 8 incorrect bits. The FSMC driver reads 14 instead of 13 oob
bytes to accommodate for 16 bit device as well.
Unfortunately, the internal ecc state machine gets corrupted for 8 bit devices
reading 512 + 14 bytes of data resulting in error indices not getting reported.
Fix this by reading 14 bytes only for 16 bit devices
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
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