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2017-11-14Merge branch 'clk-const' into clk-nextStephen Boyd25-86/+86
* clk-const: clk: make clk_init_data const clk: imx: make clk_ops const clk: mmp: make clk_ops const clk: hisilicon: make clk_ops const clk: mxs: make clk_ops const clk: sirf: make clk_ops const clk: spear: make clk_ops const CLK: SPEAr: make aux_clk_masks structures const CLK: SPEAr: make structure field and function argument as const
2017-11-14Merge branch 'clk-sunxi' into clk-nextStephen Boyd2-3/+1
* clk-sunxi: clk: sunxi: explicitly request exclusive reset control clk: sunxi: fix build warning
2017-11-14Merge branch 'clk-hikey' into clk-nextStephen Boyd4-6/+14
* clk-hikey: clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: hi6220: mark clock cs_atb_syspll as critical
2017-11-14Merge tag 'tegra-for-4.15-clk-2' of ↵Stephen Boyd14-72/+118
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk drivers updates from Thierry Reding: This contains cleanups and minor fixes for the Tegra clock driver. * tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() clk: tegra: dfll: Fix drvdata overwriting issue clk: tegra: Fix cclk_lp divisor register clk: tegra: Bump SCLK clock rate to 216 MHz clk: tegra: Use common definition of APBDMA clock gate clk: tegra: Correct parent of the APBDMA clock clk: tegra: Add AHB DMA clock entry clk: tegra: Mark APB clock as critical clk: tegra: Make tegra_clk_pll_params __ro_after_init clk: tegra: Fix sor1_out clock implementation clk: tegra: Use tegra_clk_register_periph_data() clk: tegra: Add peripheral clock registration helper clk: tegra: Check BPMP response return code dt-bindings: clock: tegra: Add sor1_out clock firmware: tegra: Propagate error code to caller
2017-11-14clk: uniphier: fix DAPLL2 clock rate of Pro5Masahiro Yamada1-1/+1
The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-14clk: uniphier: fix parent of miodmac clock dataMasahiro Yamada1-4/+3
The "miodmac" is not a child of "stdmac". They are independent from each other. Fix it. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-14clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'Shawn Guo1-1/+11
Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock. Let's add this mux clock as 'sdio0_mux', and correct the parent of 'clk_sdio0_ciu' to be it. Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-14clk: hisilicon: Delete an error message for a failed memory allocation in ↵Markus Elfring1-3/+1
hisi_register_clkgate_sep() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <[email protected]> Reviewed-by: Leo Yan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-14clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua1-1/+1
UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by: Zhong Kaihua <[email protected]> Signed-off-by: Guodong Xu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-14dma-buf: try to replace a signaled fence in ↵Christian König1-3/+15
reservation_object_add_shared_inplace The amdgpu issue to also need signaled fences in the reservation objects should be fixed by now. Optimize the handling by replacing a signaled fence when adding a new shared one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14dma-buf: keep only not signaled fence in ↵Christian König1-17/+21
reservation_object_add_shared_replace v3 The amdgpu issue to also need signaled fences in the reservation objects should be fixed by now. Optimize the list by keeping only the not signaled yet fences around. v2: temporary put the signaled fences at the end of the new container v3: put the old fence at the end of the new container as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Tested-by: Chris Wilson <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glkRodrigo Vivi2-9/+19
Display is not sending a PMRsp when a PMReq is received at the same time that all planes are turned off. State machine in the dcprunit is stuck in the WAIT4DONE state which means that there is no fill_done. WA: disable arbiter clock gating, set bit [27] of 0x46530 v2: As Ville pointed out, based on the description the issue can happen when disabling the planes, similar to WaRsPkgCStateDisplayPMReq:hsw Also description of the issue was updated on commit message to make it more clear that we need this earlier. v3: Restore comment about possibility to system hang to where we are sure about it, without speculation. (Ville). v4: Remove doubled sob. Actually do v3 changes :/ Cc: Radhakrishna Sripada <[email protected]> Cc: Imre Deak <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14drm/amdgpu: set f_mapping on exported DMA-bufsChristian König1-1/+5
Otherwise we can't correctly CPU map TTM buffers. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-11-14drm/amdgpu: Properly allocate VM invalidate eng v2ozeng1-3/+12
v1: Properly allocate TLB invalidation engine to avoid conflict. v2: Added comments to codes Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian Konig <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-11-14drm/amd/display: fix MST link training fail division by 0Eric Yang1-2/+4
When link training fail in MST case, we will divide by 0 when calculating avg_time_slots_per_mtp, so we cannot proceed. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/amd/display: Fix formatting for null pointer dereference fixHarry Wentland1-1/+1
Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/amd/display: Remove dangling planes on dc commit stateLeo (Sunpeng) Li1-2/+35
When disabling pipe splitting, we need to make sure we disable both planes used. This should be done for Linux as well. Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/amd/display: add flip_immediate to commit update for streamBhawanpreet Lakha1-1/+4
This struct is not updated on page flip and causes vblank_mode to not work as expected Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Tested-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/amd/display: Miss register MST encoder cbsJerry (Fangzhi) Zuo1-1/+11
It is to fix: MST display failed to resume from S3 Need to properly setup MST encoder cbs. Otherwise drm_device encoder doesn't register its own cbs, leading to NULL encoder->funcs in drm_atomic_helper_resume(). Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/amd/display: Fix warnings on S3 resumeLeo (Sunpeng) Li1-0/+28
This is a followup to the following revert: Rex Zhu Revert "drm/amd/display: Match actual state during S3 resume." Three things needed to be addressed: 1. Potential memory leak on dc_state creation in atomic_check during s3 resume 2. Warnings are now seen in dmesg during S3 resume 3. Since dc_state is now created in atomic_check, what the reverted patch was addressing needs to be reevaluated. This change addresses the above: 1. Since the suspend procedure calls drm_atomic_state_clear, our hook for releasing the dc_state is called. This frees it before atomic_check creates it during resume. The leak does not occur. 2. The dc_crtc/plane_state references kept by the atomic states need to be released before calling atomic_check, which warns if they are non-null. This is because atomic_check is responsible for creating the dc_*_states. This is a special case for S3 resume, since the atomic state duplication that occurs during suspend also copies a reference to the dc_*_states. 3. See 2. comments are also updated to reflect this. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-14drm/fsl-dcu: enable IRQ before drm_atomic_helper_resume()Stefan Agner1-1/+1
The resume helpers wait for a vblank to occurre hence IRQ need to be enabled. This avoids a warning as follows during resume: WARNING: CPU: 0 PID: 314 at drivers/gpu/drm/drm_atomic_helper.c:1249 drm_atomic_helper_wait_for_vblanks.part.1+0x284/0x288 [CRTC:28:crtc-0] vblank wait timed out Signed-off-by: Stefan Agner <[email protected]>
2017-11-14drm/fsl-dcu: avoid disabling pixel clock twice on suspendStefan Agner1-1/+0
With commit 0a70c998d0c5 ("drm/fsl-dcu: enable pixel clock when enabling CRTC") the pixel clock is controlled by the CRTC code. Disabling the pixel clock in suspend leads to a warning due to the second clk_disable_unprepare call: WARNING: CPU: 0 PID: 359 at drivers/clk/clk.c:594 clk_core_disable+0x8c/0x90 Remove clk_disable_unprepare call for pixel clock to avoid unbalanced clock disable on suspend. Fixes: 0a70c998d0c5 ("drm/fsl-dcu: enable pixel clock when enabling CRTC") Signed-off-by: Stefan Agner <[email protected]>
2017-11-14drm/fsl-dcu: Don't set connector DPMS propertyLaurent Pinchart1-5/+0
Since commit 4a97a3da420b ("drm: Don't update property values for atomic drivers") atomic drivers must not update property values as properties are read from the state instead. To catch remaining users, the drm_object_property_set_value() function now throws a warning when called by atomic drivers on non-immutable properties, and we hit that warning when creating connectors. The easy fix is to just remove the drm_object_property_set_value() as it is used here to set the initial value of the connector's DPMS property to OFF. The DPMS property applies on top of the connector's state crtc pointer (initialized to NULL) that is the main connector on/off control, and should thus default to ON. Fixes: 4a97a3da420b ("drm: Don't update property values for atomic drivers") Cc: [email protected] Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Stefan Agner <[email protected]>
2017-11-14Merge tag 'staging-4.15-rc1' into v4l_for_linusMauro Carvalho Chehab1117-9923/+10072
There are some conflicts between staging and media trees, as reported by Stephen Rothwell <[email protected]>. So, merge from staging. * tag 'staging-4.15-rc1': (775 commits) staging: lustre: add SPDX identifiers to all lustre files staging: greybus: Remove redundant license text staging: greybus: add SPDX identifiers to all greybus driver files staging: ccree: simplify ioread/iowrite staging: ccree: simplify registers access staging: ccree: simplify error handling logic staging: ccree: remove dead code staging: ccree: handle limiting of DMA masks staging: ccree: copy IV to DMAable memory staging: fbtft: remove redundant initialization of buf staging: sm750fb: Fix parameter mistake in poke32 staging: wilc1000: Fix bssid buffer offset in Txq staging: fbtft: fb_ssd1331: fix mirrored display staging: android: Fix checkpatch.pl error staging: greybus: loopback: convert loopback to use generic async operations staging: greybus: operation: add private data with get/set accessors staging: greybus: loopback: Fix iteration count on async path staging: greybus: loopback: Hold per-connection mutex across operations staging: greybus/loopback: use ktime_get() for time intervals staging: fsl-dpaa2/eth: Extra headroom in RX buffers ... Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2017-11-14Merge airlied/drm-next into drm-intel-next-queuedRodrigo Vivi941-23231/+34012
Catchup with upstream. Signed-off-by: Rodrigo Vivi <[email protected]>
2017-11-14drm/i915: Unconditionally apply the Broxton register workaround setChris Wilson1-17/+12
Having removed the preproduction Broxton support (see commit 0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction machines")), we know we then always need the production Broxton workaround set and do not need a predicate upon revision. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14drm/i915: Remove pre-production Broxton register workaroundsChris Wilson1-55/+1
We've begun excluding pre-production Broxton machines since commit 0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction machines"), now remove the list of workaround register values for those early machines. Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnlChris Wilson2-6/+5
gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't sticking. Commit 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a masked register in the context image, but commit 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as an ordering unmasked register. The masked write will be losing the default settings if we trust the original commit. That gem_workarounds reports the value is lost entirely is more worrying though -- but it clearly suggests that it is not a masked register in the context image, so unify both w/a to use the original rmw. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103705 Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.") References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") Signed-off-by: Chris Wilson <[email protected]> Cc: Rafael Antognolli <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Oscar Mateo <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Rafael Antognolli <[email protected]>
2017-11-14mailbox/omap: unregister mbox classArvind Yadav1-1/+5
platform_driver_register() can fail here and we must unregister mbox class. Signed-off-by: Arvind Yadav <[email protected]> Acked-by: Suman Anna <[email protected]> Signed-off-by: Jassi Brar <[email protected]>
2017-11-14mailbox: mailbox-test: don't rely on rx_buffer content to signal data readySudeep Holla1-5/+6
Currently we rely on the first byte of the Rx buffer to check if there's any data available to be read. If the first byte of the received buffer is zero (i.e. null character), then we fail to signal that data is available even when it's available. Instead introduce a boolean variable to track the data availability and update it in the channel receive callback as ready and clear it when the data is read. Signed-off-by: Sudeep Holla <[email protected]> Signed-off-by: Jassi Brar <[email protected]>
2017-11-14mailbox: reset txdone_method TXDONE_BY_POLL if client knows_txdoneSudeep Holla2-4/+4
Currently the mailbox framework sets txdone_method to TXDONE_BY_POLL if the controller sets txdone_by_poll. However some clients can have a mechanism to do TXDONE_BY_ACK which they can specify by knows_txdone. However, we endup setting both TXDONE_BY_POLL and TXDONE_BY_ACK in that case. In such scenario, we may end up with below warnings as the tx ticker is run both by mailbox framework and the client. WARNING: CPU: 1 PID: 0 at kernel/time/hrtimer.c:805 hrtimer_forward+0x88/0xd8 CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.12.0-rc5 #242 Hardware name: ARM LTD ARM Juno Development Platform task: ffff8009768ca700 task.stack: ffff8009768f8000 PC is at hrtimer_forward+0x88/0xd8 LR is at txdone_hrtimer+0xd4/0xf8 Call trace: hrtimer_forward+0x88/0xd8 __hrtimer_run_queues+0xe4/0x158 hrtimer_interrupt+0xa4/0x220 arch_timer_handler_phys+0x30/0x40 handle_percpu_devid_irq+0x78/0x130 generic_handle_irq+0x24/0x38 __handle_domain_irq+0x5c/0xb8 gic_handle_irq+0x54/0xa8 This patch fixes the issue by resetting TXDONE_BY_POLL if client has set knows_txdone. Cc: Alexey Klimov <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Signed-off-by: Jassi Brar <[email protected]>
2017-11-14PCI/ASPM: Add L1 Substates definitionsBjorn Helgaas1-14/+20
Add and use #defines for L1 Substate register fields instead of hard-coding the masks. Also update comments to use names from the spec. No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Vidya Sagar <[email protected]>
2017-11-14PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLDBjorn Helgaas1-1/+1
Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream) device using the capability pointer of the *child* (downstream) device, which corrupted some random word of the parent's config space. Use the parent's L1 SS capability pointer to program its LTR_L1.2_THRESHOLD. Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Vidya Sagar <[email protected]> CC: [email protected] # v4.11+ CC: Rajat Jain <[email protected]>
2017-11-14drm/i915: fix 64bit divideLionel Landwerlin4-19/+18
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! Store the frequency in kHz and drop 64bit divisions. v2: Use div64_u64 (Matthew) v3: store frequency in kHz to avoid 64bit divs (Chris/Ville) Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace") Reported-by: Matthew Auld <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Ewelina Musial <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
2017-11-14drm/i915: Generalize transcoder loopingMika Kahola1-4/+6
To make looping through transcoders in intel_ddi.c more generic, let's switch to use 'for_each_pipe()' macro to do this. v2: Add a notion that we are dealing with transcoders instead of pipes (Jani) Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Ville Syrjälä <[email protected]>
2017-11-14drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+James Ausmus4-25/+76
Since GLK, some plane configuration settings have moved to the PLANE_COLOR_CTL register. Refactor handling of the register to work like PLANE_CTL. This also allows us to fix the set/read of the plane Alpha Mode for GLK+. v2: Adjust ordering of platform checks to be newest->oldest, drop redundant comment about alpha blending. (Ville) v3: Move Alpha Mode bits out of skl_plane_ctl_format into skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization of state->color_ctl on platforms that don't use it, and drop color_ctl local var. (Ville) v4: Consolidate skl_plane_ctl_format switch statement on formats that return the same settings. (Ville) Signed-off-by: James Ausmus <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Ville Syrjälä <[email protected]>
2017-11-14net: stmmac: fix LPI transitioning for dwmac4Niklas Cassel2-1/+25
The LPI transitioning logic in stmmac_main uses priv->tx_path_in_lpi_mode to enter/exit LPI. However, priv->tx_path_in_lpi_mode is assigned using the return value from host_irq_status(). So for dwmac4, priv->tx_path_in_lpi_mode was always false, so stmmac_tx_clean() would always try to put us in eee mode, and stmmac_xmit() would never take us out of eee mode. To fix this, make host_irq_status() read and return the LPI irq status also for dwmac4. This also increments the existing LPI counters, so that ethtool --statistics shows LPI transitions also for dwmac4. For dwmac1000, irqs are enabled/disabled using the register named "Interrupt Mask Register", and thus setting a bit disables that specific irq. For dwmac4 the matching register is named "MAC_Interrupt_Enable", and thus setting a bit enables that specific irq. Looking at dwmac1000_core.c, the irqs that are always enabled are: LPI and PMT. Looking at dwmac4_core.c, the irqs that are always enabled are: PMT. To be able to read the LPI irq status, we need to enable the LPI irq also for dwmac4. Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14atm: horizon: Fix irq release errorArvind Yadav1-1/+1
atm_dev_register() can fail here and passed parameters to free irq which is not initialised. Initialization of 'dev->irq' happened after the 'goto out_free_irq'. So using 'irq' insted of 'dev->irq' in free_irq(). Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14liquidio: Missing error code in liquidio_init_nic_module()Dan Carpenter1-1/+2
We accidentally return success if lio_vf_rep_modinit() fails instead of propogating the error code. Fixes: e20f469660ad ("liquidio: synchronize VF representor names with NIC firmware") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14ibmvnic: Feature implementation of Vital Product Data (VPD) for the ibmvnic ↵Desnes Augusto Nunes do Rosario2-4/+176
driver This patch implements and enables VDP support for the ibmvnic driver. Moreover, it includes the implementation of suitable structs, signal transmission/handling and functions which allows the retrival of firmware information from the ibmvnic card through the ethtool command. Signed-off-by: Desnes A. Nunes do Rosario <[email protected]> Signed-off-by: Thomas Falcon <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14net: mvneta: fix handling of the Tx descriptor counterSimon Guinot1-5/+8
The mvneta controller provides a 8-bit register to update the pending Tx descriptor counter. Then, a maximum of 255 Tx descriptors can be added at once. In the current code the mvneta_txq_pend_desc_add function assumes the caller takes care of this limit. But it is not the case. In some situations (xmit_more flag), more than 255 descriptors are added. When this happens, the Tx descriptor counter register is updated with a wrong value, which breaks the whole Tx queue management. This patch fixes the issue by allowing the mvneta_txq_pend_desc_add function to process more than 255 Tx descriptors. Fixes: 2a90f7e1d5d0 ("net: mvneta: add xmit_more support") Cc: [email protected] # 4.11+ Signed-off-by: Simon Guinot <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14net: hns3: Updates MSI/MSI-X alloc/free APIs(depricated) to new APIsSalil Mehta2-81/+43
This patch migrates the HNS3 driver code from use of depricated PCI MSI/MSI-X interrupt vector allocation/free APIs to new common APIs. Signed-off-by: Salil Mehta <[email protected]> Suggested-by: Christoph Hellwig <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14net: dsa: lan9303: correctly check return value of devm_gpiod_get_optionalPan Bian1-1/+1
Function devm_gpiod_get_optional() returns an ERR_PTR on failure. Its return value should not be validated by a NULL check. Instead, use IS_ERR. Signed-off-by: Pan Bian <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14net: phy: realtek: fix RTL8211F interrupt modeHeiner Kallweit1-0/+2
After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY interrupt on some platforms" ethernet stopped working on my Odroid-C2 which has a RTL8211F phy. It turned out that no interrupts were triggered. Further analysis showed the register INER can't be altered on page 0. Because register INSR needs to be accessed via page 0xa43 I assumed that register INER needs to be accessed via some page too. Some brute force check resulted in page 0xa42 being the right one. With this patch the phy is working properly in interrupt mode. Fixes: 3447cf2e9a11 ("net/phy: Add support for Realtek RTL8211F") Signed-off-by: Heiner Kallweit <[email protected]> Tested-by: Jerome Brunet <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14drm/i915: Introduce GEM proxyTina Zhang3-4/+47
GEM proxy is a kind of GEM, whose backing physical memory is pinned and produced by guest VM and is used by host as read only. With GEM proxy, host is able to access guest physical memory through GEM object interface. As GEM proxy is such a special kind of GEM, a new flag I915_GEM_OBJECT_IS_PROXY is introduced to ban host from changing the backing storage of GEM proxy. v3: - update "Reviewed-by". (Joonas) v2: - return -ENXIO when pin and map pages of GEM proxy to kernel space. (Chris) Here are the histories of this patch in "Dma-buf support for Gvt-g" patch-set: v14: - return -ENXIO when gem proxy object is banned by ioctl. (Chris) (Daniel) v13: - add comments to GEM proxy. (Chris) - don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris) - check GEM proxy bar after finishing i915_gem_object_wait. (Chris) - remove GEM proxy bar in i915_gem_madvise_ioctl. v6: - add gem proxy barrier in the following ioctls. (Chris) i915_gem_set_caching_ioctl i915_gem_set_domain_ioctl i915_gem_sw_finish_ioctl i915_gem_set_tiling_ioctl i915_gem_madvise_ioctl Signed-off-by: Tina Zhang <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> #v1 Reviewed-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14drm/i915: Object w/o backing storage is banned by -ENXIOTina Zhang1-1/+1
-ENXIO should be returned when operations are banned from changing backing storage of objects without backing storage. v4: - update "Reviewed-by". (Joonas) v3: - separate this patch from "Introduce GEM proxy" patch-set. (Joonas) v2: - update the patch description and subject to just mention objects w/o backing storage, instead of "GEM proxy". (Joonas) Signed-off-by: Tina Zhang <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-14mlxsw: spectrum_router: Add batch neighbour deletionIdo Schimmel1-3/+12
In commit 4a3c67a6e7cd ("mlxsw: spectrum_router: Don't batch neighbour deletion") I removed the support for batch deletion of neighbours on a router interface (RIF) since at that time the firmware did not support it for IPv6 neighbours. This is now supported by the version enforced by the driver, so there is no reason to delete neighbours one by one anymore. Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: Jiri Pirko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14mlxsw: spectrum: Update minimum firmware version to 13.1530.152Shalom Toledo1-2/+2
This new firmware contains: - Support Spectrum A1 revision - Batch deletion of IPv6 neighbours - Remove incorrect VPD capability Signed-off-by: Shalom Toledo <[email protected]> Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: Jiri Pirko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2017-11-14ACPI / utils: Fix memory leak in acpi_evaluate_reference() error pathXiongfeng Wang1-0/+1
When package.count is larger than ACPI_MAX_HANDLES, buffer.pointer is not freed before the function returns AE_NO_MEMORY. Fix this possible memory leak by kfree'ing it. Signed-off-by: Xiongfeng Wang <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2017-11-14drm/i915: Fix function name in commentLucas De Marchi1-1/+1
Commit 78597996370c (drm/i915/bxt: Fix PPS lost state after suspend breaking eDP link training) renamed the function to intel_power_sequencer_reset() but forgot to update comment. Cc: Imre Deak <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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