aboutsummaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2020-10-27cpufreq: e_powersaver: remove unreachable breakZhang Qilong2-2/+0
A 'break' following a 'return' statement is pointless, so remove it. Signed-off-by: Zhang Qilong <[email protected]> Acked-by: Viresh Kumar <[email protected]> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <[email protected]>
2020-10-27Merge tag 'devicetree-fixes-for-5.10-1' of ↵Linus Torvalds1-2/+11
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - More binding additionalProperties/unevaluatedProperties additions - More yamllint fixes on additions in the merge window - CrOS embedded controller schema updates to fix warnings - LEDs schema update adding ID_RGB - A reserved-memory fix for regions starting at address 0x0 * tag 'devicetree-fixes-for-5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: Another round of adding missing 'additionalProperties/unevalutatedProperties' dt-bindings: Explicitly allow additional properties in board/SoC schemas dt-bindings: More whitespace clean-ups in schema files mfd: google,cros-ec: add missing properties dt-bindings: input: convert cros-ec-keyb to json-schema dt-bindings: i2c: convert i2c-cros-ec-tunnel to json-schema of: Fix reserved-memory overlap detection dt-bindings: mailbox: mtk-gce: fix incorrect mbox-cells value dt-bindings: leds: Update devicetree documents for ID_RGB
2020-10-27drm/amdgpu/swsmu: drop smu i2c bus on navi1xAlex Deucher1-25/+0
Stop registering the SMU i2c bus on navi1x. This leads to instability issues when userspace processes mess with the bus and also seems to cause display stability issues in some cases. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1314 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1341 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amdgpu: drop mem_global_referencedChristian König1-1/+0
Not used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amdgpu: add vangogh apu flagHuang Rui2-1/+4
This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amdgpu: enable MULTI_MON_PP_MCLK_SWITCH DC feature at defaultEvan Quan1-2/+10
With this, for multiple monitors in sync(e.g. with the same model), mclk switching will be allowed. That helps saving some idle power on some ASICs(e.g. Polaris). Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/display: correct asic type check V2Evan Quan5-7/+16
Check chip family also to avoid wrong identification. V2: use the correct macro without AMDGPU prefix Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: drop redundant display settingEvan Quan1-12/+0
As this is already performed in smu7_set_power_state_tasks(). Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: reconfigure smc on display vbitimeout setting changeEvan Quan2-0/+7
Reconfigure smc display settings on vbitimeout change. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the mclk switching settingEvan Quan2-17/+108
Correct the mclk switching setting for multiple displays. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: enable Polaris watermark table settingEvan Quan2-1/+60
Enable watermark table setting for Polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: fulfill the Polaris implementation for ↵Evan Quan1-0/+67
get_clock_by_type_with_latency() Fulfill Polaris get_clock_by_type_with_latency(). Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct vddc_dep_on_dal_pwrl setupEvan Quan1-3/+15
Correct Polaris10 setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct SMC sclk/mclk boot level setupEvan Quan1-0/+8
Correct Polaris smc boot level setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct pcie spc cap setupEvan Quan1-0/+2
Correct Polaris10 pcie spc cap setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct clk/voltage dependence setupEvan Quan1-0/+2
Correct Polaris10 clk/voltage dependence setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the way to get the highest vddcEvan Quan1-2/+28
Populate the correct highest vddc setting on Polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct sclk/mclk dpm enablementEvan Quan2-3/+9
Correct Polaris10 sclk/mclk dpm enablement. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct smc voltage controller setupEvan Quan1-1/+2
Correct Polaris10 smc voltage controller setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct platformcaps setupEvan Quan3-4/+19
Correct Polaris10 platformcaps setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct VRconfig settingEvan Quan1-1/+14
Correct Polaris VRconfig setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct vddc phase control settingEvan Quan2-14/+24
Correct Polaris10 vddc phase control. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct avfs fuse settingsEvan Quan1-32/+23
Correct Polaris10 avfs fuse setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct Polaris DIDT configurationsEvan Quan2-2/+34
Correct Polaris DIDT enablement. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct Polaris powertune table setupEvan Quan3-1/+85
Correct powertune table setup for Polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the checks for sclk/mclk SS supportEvan Quan4-1/+26
Correct sclk/mclk SS support checks. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct VR shared rail infoEvan Quan5-2/+34
Add VR shared rail info. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add mc register table initializationEvan Quan4-0/+58
Add mc register table initialization. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add edc leakage controller settingEvan Quan6-0/+252
Enable edc controller table setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: setup zero rpm parameters for polaris10Evan Quan3-0/+29
Only if the ZeroRPM feature is supported. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct polaris10 clock stretcher data table settingEvan Quan1-31/+11
By using the saved copy of ro_range_maximum and ro_range_minimum. Correct the setting for "LdoRefSel". Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the settings for ro range minimum and maximumEvan Quan2-0/+65
Make the settings more precise. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: drop redundant efuse mask calculationsEvan Quan4-6/+10
By moving that in atomfw_read_efuse(). Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: optimize AC timing programmingEvan Quan1-1/+1
Programming AC Timing Parameters is only dependent on MCLK. No need to nest loop for each SCLK DPM level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/powerplay: separate Polaris fan table setup from TongaEvan Quan2-1/+87
Instead of sharing the fan table setup with Tonga, Polaris has its own fan table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add PWR_CKS_CNTL settingEvan Quan1-4/+11
This is for some special Polaris10 ASICs. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amdgpu: correct CG_ACLK_CNTL settingEvan Quan1-3/+11
Correct polaris CG_ACLK_CNTL setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: drop arb table first byte workaroundEvan Quan1-31/+0
As this is not needed for polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add pptable VRHotLevel settingEvan Quan1-0/+3
Add missing VRHotLevel setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the BootLinkLevel setupEvan Quan1-1/+1
Set the BootLinkLevel as the max level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the ACPI table setup V2Evan Quan1-1/+2
Correct the setting for "ActivityLevel". V2: rich the comment Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct mclk table setupEvan Quan1-12/+8
Correct the settings for "StutterEnable" and "EnabledForActivity". Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct sclk table setupEvan Quan1-2/+21
Correct Polaris10 sclk table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct vddci table setupEvan Quan1-2/+2
Make sure the settings are applied only when voltage controlled by gpio. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: populate smc samu tableEvan Quan1-0/+53
Add missing smc samu table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: populate smc vddc tableEvan Quan1-0/+26
Add missing vddc table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the checks for polaris kickersEvan Quan3-49/+48
By defining new Macros. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/vc4: drv: Add error handding for bindHoegeun Kwon1-0/+1
There is a problem that if vc4_drm bind fails, a memory leak occurs on the drm_property_create side. Add error handding for drm_mode_config. Signed-off-by: Hoegeun Kwon <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-27interconnect: qcom: use icc_sync state for sm8[12]50Dmitry Baryshkov2-6/+8
In addition to the rest of Qcom interconnect drivers use icc_sync_state for SM8150/SM8250 interconnect drivers to notify the interconnect framework when all consumers are probed and there is no need to keep the bandwidth set to maximum anymore. Also move the BCM initialization before creating the nodes to set the max bandwidth in hardware for the initialization/probing stage. Signed-off-by: Dmitry Baryshkov <[email protected]> Fixes: 7d3b0b0d8184 ("interconnect: qcom: Use icc_sync_state") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Georgi Djakov <[email protected]>
2020-10-27staging: fieldbus: anybuss: jump to correct label in an error pathJing Xiangfeng1-1/+1
In current code, controller_probe() misses to call ida_simple_remove() in an error path. Jump to correct label to fix it. Fixes: 17614978ed34 ("staging: fieldbus: anybus-s: support the Arcx anybus controller") Reviewed-by: Sven Van Asbroeck <[email protected]> Signed-off-by: Jing Xiangfeng <[email protected]> Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.