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2021-03-18octeontx2-pf: Add tc flower hardware offload on ingress trafficNaveen Mamindlapalli6-2/+551
This patch adds support for tc flower hardware offload on ingress traffic. Since the tc-flower filter rules use the same set of MCAM rules as the n-tuple filters, the n-tuple filters and tc flower rules are mutually exclusive. When one of the feature is enabled using ethtool, the other feature is disabled in the driver. By default the driver enables n-tuple filters during initialization. The following flow keys are supported. -> Ethernet: dst_mac -> L2 proto: all protocols -> VLAN (802.1q): vlan_id/vlan_prio -> IPv4: dst_ip/src_ip/ip_proto{tcp|udp|sctp|icmp}/ip_tos -> IPv6: ip_proto{icmpv6} -> L4(tcp/udp/sctp): dst_port/src_port The following flow actions are supported. -> drop -> accept -> redirect -> vlan pop The flow action supports multiple actions when vlan pop is specified as the first action. The redirect action supports redirecting to the PF/VF of same PCI device. Redirecting to other PCI NIX devices is not supported. Example #1: Add a tc filter rule to drop UDP traffic with dest port 80 # ethtool -K eth0 hw-tc-offload on # tc qdisc add dev eth0 ingress # tc filter add dev eth0 protocol ip parent ffff: flower ip_proto \ udp dst_port 80 action drop Example #2: Add a tc filter rule to redirect ingress traffic on eth0 with vlan id 3 to eth6 (ex: eth0 vf0) after stripping the vlan hdr. # ethtool -K eth0 hw-tc-offload on # tc qdisc add dev eth0 ingress # tc filter add dev eth0 parent ffff: protocol 802.1Q flower \ vlan_id 3 vlan_ethtype ipv4 action vlan pop action mirred \ ingress redirect dev eth6 Example #3: List the ingress filter rules # tc -s filter show dev eth4 ingress Example #4: Delete tc flower filter rule with handle 0x1 # tc filter del dev eth0 ingress protocol ip pref 49152 \ handle 1 flower Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-18octeontx2-pf: Add ip tos and ip proto icmp/icmpv6 flow offload supportNaveen Mamindlapalli3-4/+57
Add support for programming the HW MCAM match key with IP tos, IP(v6) proto icmp/icmpv6, allowing flow offload rules to be installed using those fields. The NPC HW extracts layer type, which will be used as a matching criteria for different IP protocols. The ethtool n-tuple filter logic has been updated to parse the IP tos and l4proto for HW offloading. l4proto tcp/udp/sctp/ah/esp/icmp are supported. See example usage below. Ex: Redirect l4proto icmp to vf 0 queue 0 ethtool -U eth0 flow-type ip4 l4proto 1 action vf 0 queue 0 Ex: Redirect flow with ip tos 8 to vf 0 queue 0 ethtool -U eth0 flow-type ip4 tos 8 vf 0 queue 0 Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: macb: simplify clk_init with dev_err_probeMichael Tretter1-11/+9
On some platforms, e.g., the ZynqMP, devm_clk_get can return -EPROBE_DEFER if the clock controller, which is implemented in firmware, has not been probed yet. As clk_init is only called during probe, use dev_err_probe to simplify the error message and hide it for -EPROBE_DEFER. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: mv88e6xxx: implement .port_set_policy for AmethystMarek Behún3-27/+99
The 16-bit Port Policy CTL register from older chips is on 6393x changed to Port Policy MGMT CTL, which can access more data, but indirectly and via 8-bit registers. The original 16-bit value is divided into first two 8-bit register in the Port Policy MGMT CTL. We can therefore use the previous code to compute the mask and shift, and then - if 0 <= shift < 8, we access register 0 in Port Policy MGMT CTL - if 8 <= shift < 16, we access register 1 in Port Policy MGMT CTL There are in fact other possible policy settings for Amethyst which could be added here, but this can be done in the future. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Pavana Sharma <pavana.sharma@digi.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: mv88e6xxx: add support for mv88e6393x familyPavana Sharma8-0/+771
The Marvell 88E6393X device is a single-chip integration of a 11-port Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers and three 10-Gigabit interfaces. This patch adds functionalities specific to mv88e6393x family (88E6393X, 88E6193X and 88E6191X). The main differences between previous devices and this one are: - port 0 can be a SERDES port - all SERDESes are one-lane, eg. no XAUI nor RXAUI - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER (on 6191X only one SERDES is capable of more than 1g; USXGMII is not yet supported with this change) - Port Policy CTL register is changed to Port Policy MGMT CTL register, via which several more registers can be accessed indirectly - egress monitor port is configured differently - ingress monitor/CPU/mirror ports are configured differently and can be configured per port (ie. each port can have different ingress monitor port, for example) - port speed AltBit works differently than previously - PHY registers can be also accessed via MDIO address 0x18 and 0x19 (on previous devices they could be accessed only via Global 2 offsets 0x18 and 0x19, which means two indirections; this feature is not yet leveraged with thiis commit) Co-developed-by: Ashkan Boldaji <ashkan.boldaji@digi.com> Signed-off-by: Ashkan Boldaji <ashkan.boldaji@digi.com> Signed-off-by: Pavana Sharma <pavana.sharma@digi.com> Co-developed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: mv88e6xxx: wrap .set_egress_port methodMarek Behún2-35/+33
There are two implementations of the .set_egress_port method, and both of them, if successful, set chip->*gress_dest_port variable. To avoid code repetition, wrap this method into mv88e6xxx_set_egress_port. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Pavana Sharma <pavana.sharma@digi.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: mv88e6xxx: change serdes lane parameter type from u8 type to intPavana Sharma5-99/+99
Returning 0 is no more an error case with MV88E6393 family which has serdes lane numbers 0, 9 or 10. So with this change .serdes_get_lane will return lane number or -errno (-ENODEV or -EOPNOTSUPP). Signed-off-by: Pavana Sharma <pavana.sharma@digi.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17ethernet/microchip:remove unneeded variable: "ret"dingsenjie1-2/+1
remove unneeded variable: "ret". Signed-off-by: dingsenjie <dingsenjie@yulong.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17ethernet/broadcom:remove unneeded variable: "ret"dingsenjie1-2/+1
remove unneeded variable: "ret". Signed-off-by: dingsenjie <dingsenjie@yulong.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: stmmac: add per-queue TX & RX coalesce ethtool supportOng Boon Leong7-49/+143
Extending the driver to support per-queue RX and TX coalesce settings in order to support below commands: To show per-queue coalesce setting:- $ ethtool --per-queue <DEVNAME> queue_mask <MASK> --show-coalesce To set per-queue coalesce setting:- $ ethtool --per-queue <DEVNAME> queue_mask <MASK> --coalesce \ [rx-usecs N] [rx-frames M] [tx-usecs P] [tx-frames Q] Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17octeontx2-af: Modify the return code for unsupported flow keysNaveen Mamindlapalli2-3/+5
The mbox handler npc_install_flow returns ENOTSUPP for unsupported flow keys. This patch modifies the return value to AF driver defined error code for debugging purpose. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17octeontx2-af: Avoid duplicate unicast rule in mcam_rules listSubbaraya Sundeep2-6/+7
A mcam rule described by mcam_rule struct has all the info such as the hardware MCAM entry number, match criteria and corresponding action etc. All mcam rules are stored in a linked list mcam->rules. When adding/updating a rule to the mcam->rules it is checked if a rule already exists for the mcam entry. If the rule already exists, the same rule is updated instead of creating new rule. This way only one mcam_rule exists for the only one default unicast entry installed by AF. But a PF/VF can get different NIXLF (or default unicast entry number) after a attach-detach-attach sequence. When that happens mcam_rules list end up with two default unicast rules. Fix the problem by deleting the default unicast rule list node always when disabling mcam rules. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17octeontx2-af: Use npc_install_flow API for promisc and broadcast entriesNaveen Mamindlapalli3-51/+67
Use npc_install_flow mailbox API for installing the default promisc and broadcast match entries. Earlier these entries were installed using low level npc_config_mcam_entry API, which does not store these rules and is not available when the rules are dumped using debugfs. Added chan_mask field to npc_install_flow_req to calculate channel mask when channel count is greater than 1 and configure the channel mask in entry kw_mask. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17octeontx2-af: Add support for multi channel in NIX promisc entryNalla, Pradeep3-4/+19
This patch adds support for multi channel NIX promisc entry. Packets sent on all those channels by the host should be received by the interface to which those channels belong. Channel count, if greater than 1, should be power of 2 as only one promisc entry is available for the interface. Key mask is modified such that incoming packets from channel base to channel count are directed to the same pci function. Signed-off-by: Nalla, Pradeep <pnalla@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17octeontx2-af: refactor function npc_install_flow for default entryNaveen Mamindlapalli5-62/+51
This patch refactors npc_install_flow function to install AF installed default MCAM entries similar to other MCAM entries installed by PF/VF. As a result the code would be more readable and easy to maintain. Modified npc_verify_entry and npc_verify_channel to properly check MCAM rules installed by AF. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17mlxsw: Allow 802.1d and .1ad VxLAN bridges to coexist on Spectrum>=2Amit Cohen3-15/+53
Currently only one EtherType can be configured for pushing in tunnels because EtherType is configured using SPVID.et_vlan for tunnel port. This behavior is forbidden by comparing mlxsw_sp_nve_config struct for each new tunnel, the struct contains 'ethertype' field which means that only one EtherType is legal at any given time. Remove 'ethertype' field to allow creating VxLAN devices with different bridges. To allow using several types of VxLAN bridges at the same time, the EtherType should be determined at the egress port. This behavior is achieved by setting SPVID to decide which EtherType to push at egress and for each local_port which is member in 802.1ad bridge, set SPEVET.et_vlan to ether_type1 (i.e., 0x88A8). Use switchdev_ops->init() to set different mlxsw_sp_bridge_ops for different ASICs in order to be able to split the behavior when port joins / leaves an 802.1ad bridge in different ASICs. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17mlxsw: Add struct mlxsw_sp_switchdev_ops per ASICAmit Cohen3-0/+31
A subsequent patch will need to implement different set of operations when a port joins / leaves an 802.1ad bridge, based on the ASIC type. Prepare for this change by allowing to initialize the bridge module based on the ASIC type via 'struct mlxsw_sp_switchdev_ops'. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17mlxsw: spectrum: Add mlxsw_sp_port_egress_ethtype_set()Amit Cohen2-0/+18
A subsequent patch will cause decapsulated packets to have their EtherType determined by the egress port. Add mlxsw_sp_port_egress_ethtype_set() which will be called when a port joins an 802.1ad bridge, so that it will set an 802.1ad EtherType on decapsulated packets transmitted through it, instead of the default 802.1q EtherType. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17mlxsw: reg: Add Switch Port Egress VLAN EtherType RegisterAmit Cohen1-0/+36
SPEVET configures which EtherType to push at egress for packets incoming through a local port for which 'SPVID.egr_et_set' is set. The next patches will use SPEVET to configure EtherType 0x88A8 and 0x8100 for local ports member in 802.1ad and 802.1q bridges, respectively. This allows using dual VxLAN bridges (802.1d and 802.1ad at the same time). Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17mlxsw: reg: Add egr_et_set field to SPVIDAmit Cohen1-0/+9
SPVID.egr_et_set=1 means that when VLAN is pushed at ingress (for untagged packets or for QinQ push mode) then the EtherType is decided at the egress port. The next patches will use this field for VxLAN devices (tunnel port) in order to allow using dual VxLAN bridges (802.1d and 802.1ad at the same time). Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: b53: support legacy tagsÁlvaro Fernández Rojas2-5/+8
These tags are used on BCM5325, BCM5365 and BCM63xx switches. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: ppp: Mundane typo fixes in the file pppoe.cBhaskar Chowdhury1-2/+2
s/procesing/processing/ s/comparations/comparisons/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: dsa: b53: relax is63xx() conditionÁlvaro Fernández Rojas1-4/+0
BCM63xx switches are present on bcm63xx and bmips devices. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17net: stmmac: add timestamp correction to rid CDC sync errorVoon Weifeng1-0/+16
According to Synopsis DesignWare EQoS Databook, the Clock Domain Cross synchronization error is introduced tue to the clock(GMII Tx/Rx clock) being different at the capture as compared to the PTP clock(clk_ptp_ref_i) that is used to generate the time. The CDC synchronization error is almost equal to 2 times the clock period of the PTP clock(clk_ptp_ref_i). On a Intel Tigerlake platform (with Marvell 88E2110 external PHY): Before applying this patch (with CDC synchronization error): ptp4l[64.044]: rms 8 max 13 freq +30877 +/- 11 delay 216 +/- 0 ptp4l[65.047]: rms 13 max 20 freq +30869 +/- 17 delay 213 +/- 0 ptp4l[66.050]: rms 12 max 20 freq +30857 +/- 11 delay 213 +/- 0 ptp4l[67.052]: rms 11 max 22 freq +30849 +/- 10 delay 215 +/- 0 ptp4l[68.055]: rms 10 max 16 freq +30853 +/- 13 delay 215 +/- 0 ptp4l[69.057]: rms 7 max 13 freq +30848 +/- 9 delay 216 +/- 0 ptp4l[70.060]: rms 8 max 13 freq +30846 +/- 10 delay 216 +/- 0 ptp4l[71.063]: rms 9 max 15 freq +30836 +/- 8 delay 218 +/- 0 After applying this patch (CDC syncrhonization error is taken care of): ptp4l[61.516]: rms 773 max 824 freq +31526 +/- 158 delay 200 +/- 0 ptp4l[62.519]: rms 427 max 596 freq +31668 +/- 39 delay 198 +/- 0 ptp4l[63.522]: rms 113 max 206 freq +31482 +/- 57 delay 198 +/- 0 ptp4l[64.525]: rms 40 max 56 freq +31316 +/- 29 delay 200 +/- 0 ptp4l[65.528]: rms 47 max 56 freq +31255 +/- 17 delay 200 +/- 0 ptp4l[66.531]: rms 26 max 36 freq +31246 +/- 9 delay 200 +/- 0 ptp4l[67.534]: rms 12 max 18 freq +31254 +/- 12 delay 202 +/- 0 ptp4l[68.537]: rms 7 max 12 freq +31263 +/- 10 delay 202 +/- 0 Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Wong Vee Khee <vee.khee.wong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17ionic: Update driver to use ethtool_sprintfAlexander Duyck1-85/+60
Update the ionic driver to make use of ethtool_sprintf. In addition add separate functions for Tx/Rx stats strings in order to reduce the total amount of indenting needed in the driver code. Acked-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17bna: Update driver to use ethtool_sprintfAlexander Duyck1-161/+105
Update the bnad_get_strings to make use of ethtool_sprintf and avoid unnecessary line wrapping. To do this we invert the logic for the string set test and instead exit immediately if we are not working with the stats strings. In addition the function is broken up into subfunctions for each area so that we can simply call ethtool_sprintf once for each string in a given subsection. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17vmxnet3: Update driver to use ethtool_sprintfAlexander Duyck1-34/+19
So this patch actually does 3 things. First it removes a stray white space at the start of the variable declaration in vmxnet3_get_strings. Second it flips the logic for the string test so that we exit immediately if we are not looking for the stats strings. Doing this we can avoid unnecessary indentation and line wrapping. Then finally it updates the code to use ethtool_sprintf rather than a memcpy and pointer increment to write the ethtool strings. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17virtio_net: Update driver to use ethtool_sprintfAlexander Duyck1-11/+7
Update the code to replace instances of snprintf and a pointer update with just calling ethtool_sprintf. Also replace the char pointer with a u8 pointer to avoid having to recast the pointer type. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17netvsc: Update driver to use ethtool_sprintfAlexander Duyck1-22/+11
Replace instances of sprintf or memcpy with a pointer update with ethtool_sprintf. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17ena: Update driver to use ethtool_sprintfAlexander Duyck1-14/+11
Replace instances of snprintf or memcpy with a pointer update with ethtool_sprintf. Acked-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17hisilicon: Update drivers to use ethtool_sprintfAlexander Duyck5-162/+90
Update the hisilicon drivers to make use of ethtool_sprintf. The general idea is to reduce code size and overhead by replacing the repeated pattern of string printf statements and ETH_STRING_LEN counter increments. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17nfp: Replace nfp_pr_et with ethtool_sprintfAlexander Duyck3-49/+36
The nfp_pr_et function is nearly identical to ethtool_sprintf except for the fact that it passes the pointer by value and as a return whereas ethtool_sprintf passes it as a pointer. Since they are so close just update nfp to make use of ethtool_sprintf Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17intel: Update drivers to use ethtool_sprintfAlexander Duyck4-101/+50
Update the Intel drivers to make use of ethtool_sprintf. The general idea is to reduce code size and overhead by replacing the repeated pattern of string printf statements and ETH_STRING_LEN counter increments. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Acked-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-17Merge tag 'mlx5-updates-2021-03-16' of ↵David S. Miller23-271/+493
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-updates-2021-03-16 mlx5 uplink representor netdev persistence. Before this patchset we used to have separate netdevs for Native NIC mode and Switchdev mode (uplink representor netdev), meaning that if user switches modes between Native to Switchdev and vice versa, the driver would cleanup the current netdev representor and create a new one for the new mode, such behavior created an administrative nightmare for users, where users need to be aware of such loss of both data path and control path configurations, e.g. netdev attributes and arp/route tables, where the later is more painful. A simple solution for this is not to replace the netdev in first place and use a single netdev to serve the uplink/physical port whether it is in switchdev mode or native mode. We already have different HW profiles for each netdev mode, in this series we just replace the HW profile on the fly and we keep the same netdev attached. Refactoring: Some refactoring has been made to overcome some technical difficulties 1) The netdev is created with the maximum amount of tx/rx queues to serve the two profiles. 2) Some ndos are not supported in some modes, so we added a mode check for such cases, e.g legacy sriov ndos must be blocked in switchdev mode. 3) Some mlx5 netdev private attributes need to be moved out of profiles and kept in a persistent place, where the netdev is created e.g devlink port and other global HW resources 4) The netdev devlink port is now always registered with the switch id Implementation: the last three patches implement the mechanism now as the netdev can be shared. 5) Don't recreate the netdev on switchdev mode changes 6) Prevent changing switchdev mode when some netdev operations are active, mostly when TC rules are being processed. This is required since the netdev is kept registered while switchdev mode can be changed. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-16net/mlx5: E-Switch, Protect changing mode while adding rulesRoi Dayan4-3/+122
We re-use the native NIC port net device instance for the Uplink representor, a driver currently cannot unbind TC setup callback actively, hence protect changing E-Switch mode while adding rules. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5: E-Switch, Change mode lock from mutex to rw semaphoreRoi Dayan3-20/+19
E-Switch mode change routine will take the write lock to prevent any consumer to access the E-Switch resources while E-Switch is going through a mode change. In the next patch E-Switch consumers (e.g vport representors) will take read_lock prior to accessing E-Switch resources to prevent E-Switch mode changing in the middle of the operation. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Do not reload ethernet ports when changing eswitch modeRoi Dayan7-54/+115
When switching modes between legacy and switchdev and back, do not reload ethernet interfaces. just change the profile from nic profile to uplink rep profile in switchdev mode. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Unregister eth-reps devices firstRoi Dayan1-4/+4
When we clean all the interfaces, i.e. rescan or reload module, we need to clean eth-reps devices first, before eth devices. We will re-use the native NIC port net device instance for the Uplink representor. Changing eswitch mode will skip destroying the eth device so the net device won't be destroyed and only change the profile. Creating uplink eth-rep will initialize the representor related resources. In that sense when we destroy all devices we first need to destroy eth-rep devices so uplink eth-rep will clean all representor related resources and only then destroy the eth device which will destroy rest of the resources and the net device. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5: Move devlink port from mlx5e priv to mlx5e resourcesRoi Dayan6-9/+28
We re-use the native NIC port net device instance for the Uplink representor, and the devlink port. When changing profiles we reset the mlx5e priv but we should still use the devlink port so move it to mlx5e resources. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5: Move mlx5e hw resources into a sub objectRoi Dayan7-31/+34
This is to separate between resources attributes and other attributes we will want to use. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Register nic devlink port with switch idRoi Dayan2-1/+29
We will re-use the native NIC port net device instance for the Uplink representor. Since the netdev will be kept registered while we engage switchdev mode also the devlink will be kept registered. Register the nic devlink port with switch id so it will be available when changing profiles. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Move devlink port register and unregister callsRoi Dayan2-11/+21
We will re-use the native NIC port net device instance for the Uplink representor. As such we also don't want to unregister/register the devlink port as part of the profile. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Verify dev is present in some ndosRoi Dayan3-0/+26
We will re-use the native NIC port net device instance for the Uplink representor. While changing profiles private resources are not available but some ndos are not checking if the netdev is present. So for those ndos check the netdev is present in the driver before accessing the private resources. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Use nic mode netdev ndos and ethtool ops for uplink representorRoi Dayan1-129/+4
Remove dedicated uplink rep netdev ndos and ethtools ops. We will re-use the native NIC port net device instance and ethtool ops for the Uplink representor. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Add offload stats ndos to nic netdev opsRoi Dayan3-3/+37
We will re-use the native NIC port net device instance for the Uplink representor, hence same ndos must be used. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Distinguish nic and esw offload in tc setup block cbRoi Dayan1-1/+6
We will re-use the native NIC port net device instance for the Uplink representor, hence same ndos will be used. Now we need to distinguish in the TC callback if the mode is legacy or switchdev and set the proper flag. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Allow legacy vf ndos only if in legacy modeRoi Dayan3-9/+51
We will re-use the native NIC port net device instance for the Uplink representor. Several VF ndo ops are not relevant in switchdev mode. Disallow them when eswitch mode is not legacy as a preparation. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-03-16net/mlx5e: Same max num channels for both nic and uplink profilesSaeed Mahameed1-1/+2
In downstream patches NIC netdev can change profile dynamically from NIC mode to uplink mode and vise-versa. It is required that both profiles must advertise the same max amount of tx/rx queues. Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com>
2021-03-16net: ocelot: Remove ocelot_xfh_get_cpuqHoratiu Vultur1-2/+1
Now when extracting frames from CPU the cpuq is not used anymore so remove it. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-16net: ocelot: Extend MRPHoratiu Vultur2-81/+158
This patch extends MRP support for Ocelot. It allows to have multiple rings and when the node has the MRC role it forwards MRP Test frames in HW. For MRM there is no change. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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