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2021-12-17crypto: hisilicon/qm - modify the handling method after abnormal interruptionWeili Qian1-2/+2
After processing an interrupt event and the interrupt function is enabled by writing the QM_DOORBELL_CMD_AEQ register, the hardware may generate new interrupt events due to processing other user's task when the subsequent interrupt events have not been processed. The new interrupt event will disrupt the current normal processing flow and cause other problems. Therefore, the operation of writing the QM_DOORBELL_CMD_AEQ doorbell register needs to be placed after all interrupt events processing are completed. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/qm - code movementWeili Qian1-69/+69
This patch does not change any code, just code movement. Preparing for next patch. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/qm - remove unnecessary device memory resetWeili Qian1-5/+18
The internal memory of the device needs to be reset only when the device is globally initialized. Other scenarios, such as function reset, do not need to perform reset. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/qm - fix deadlock for remove driverYang Shen1-2/+1
When remove the driver and executing the task occur at the same time, the following deadlock will be triggered: Chain exists of: sva_lock --> uacce_mutex --> &qm->qps_lock Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&qm->qps_lock); lock(uacce_mutex); lock(&qm->qps_lock); lock(sva_lock); And the lock 'qps_lock' is used to protect qp. Therefore, it's reasonable cycle is to continue until the qp memory is released. So move the release lock infront of 'uacce_remove'. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/zip - enable ssid for sva sglYang Shen1-1/+2
For Kunpeng 920, the bit 0 of register 'HZIP_SGL_RUSER_32_63' stand for whether the ssid is valid. So this bit should be set as valid for sva mode. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/hpre - fix memory leak in hpre_curve25519_src_init()Weili Qian1-1/+1
hpre_curve25519_src_init() allocates memory for 'ptr' before calling memcmp(). If memcmp() returns 0, the function will return '-EINVAL' without freeing memory. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: marvell/octeontx - Use kcalloc() instead of kzalloc()Gustavo A. R. Silva1-3/+1
Use 2-factor multiplication argument form kcalloc() instead of kzalloc(). Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Gustavo A. R. Silva <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: cavium - Use kcalloc() instead of kzalloc()Gustavo A. R. Silva1-4/+1
Use 2-factor multiplication argument form kcalloc() instead of kzalloc(). Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Gustavo A. R. Silva <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: ccp - Add SEV_INIT_EX supportDavid Rientjes1-15/+178
Add new module parameter to allow users to use SEV_INIT_EX instead of SEV_INIT. This helps users who lock their SPI bus to use the PSP for SEV functionality. The 'init_ex_path' parameter defaults to NULL which means the kernel will use SEV_INIT, if a path is specified SEV_INIT_EX will be used with the data found at the path. On certain PSP commands this file is written to as the PSP updates the NV memory region. Depending on file system initialization this file open may fail during module init but the CCP driver for SEV already has sufficient retries for platform initialization. During normal operation of PSP system and SEV commands if the PSP has not been initialized it is at run time. If the file at 'init_ex_path' does not exist the PSP will not be initialized. The user must create the file prior to use with 32Kb of 0xFFs per spec. Signed-off-by: David Rientjes <[email protected]> Co-developed-by: Peter Gonda <[email protected]> Signed-off-by: Peter Gonda <[email protected]> Reviewed-by: Marc Orr <[email protected]> Reported-by: kernel test robot <[email protected]> Acked-by: Brijesh Singh <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Marc Orr <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Herbert Xu <[email protected]> Cc: David Rientjes <[email protected]> Cc: John Allen <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: ccp - Add psp_init_on_probe module parameterPeter Gonda1-7/+12
Add psp_init_on_probe module parameter that allows for skipping the PSP's SEV platform initialization during module init. User may decouple module init from PSP init due to use of the INIT_EX support in upcoming patch which allows for users to save PSP's internal state to file. The file may be unavailable at module init. Also moves the PSP ABI version log message to after successful PSP init instead of module init in case this new parameter is used. Signed-off-by: Peter Gonda <[email protected]> Acked-by: Brijesh Singh <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Marc Orr <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Herbert Xu <[email protected]> Cc: David Rientjes <[email protected]> Cc: John Allen <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: ccp - Refactor out sev_fw_alloc()Peter Gonda1-7/+13
Create a helper function sev_fw_alloc() which can be used to allocate aligned memory regions for use by the PSP firmware. Currently only used for the SEV-ES TMR region but will be used for the SEV_INIT_EX NV memory region. Signed-off-by: Peter Gonda <[email protected]> Reviewed-by: Marc Orr <[email protected]> Acked-by: David Rientjes <[email protected]> Acked-by: Brijesh Singh <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Marc Orr <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Herbert Xu <[email protected]> Cc: David Rientjes <[email protected]> Cc: John Allen <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: ccp - Move SEV_INIT retry for corrupted dataPeter Gonda1-14/+16
Move the data corrupted retry of SEV_INIT into the __sev_platform_init_locked() function. This is for upcoming INIT_EX support as well as helping direct callers of __sev_platform_init_locked() which currently do not support the retry. Signed-off-by: Peter Gonda <[email protected]> Reviewed-by: Marc Orr <[email protected]> Acked-by: David Rientjes <[email protected]> Acked-by: Tom Lendacky <[email protected]> Acked-by: Brijesh Singh <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Marc Orr <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Herbert Xu <[email protected]> Cc: David Rientjes <[email protected]> Cc: John Allen <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: ccp - Add SEV_INIT rc error logging on initPeter Gonda1-1/+2
Currently only the firmware error code is printed. This is incomplete and also incorrect as error cases exists where the firmware is never called and therefore does not set an error code. Signed-off-by: Peter Gonda <[email protected]> Reviewed-by: Marc Orr <[email protected]> Acked-by: David Rientjes <[email protected]> Acked-by: Tom Lendacky <[email protected]> Acked-by: Brijesh Singh <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Brijesh Singh <[email protected]> Cc: Marc Orr <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Herbert Xu <[email protected]> Cc: David Rientjes <[email protected]> Cc: John Allen <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: hisilicon/qm - fix incorrect return value of hisi_qm_resume()Weili Qian1-1/+1
When hisi_qm_resume() returns 0, it indicates that the device has started successfully. If the device fails to start, hisi_qm_resume() needs to return the actual error code to the caller instead of 0. Fixes: d7ea53395b72 ("crypto: hisilicon - add runtime PM ops") Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: octeontx2 - parameters for custom engine groupsSrujana Challa6-1/+142
Added devlink parameters to create and delete custom CPT engine groups. Example: devlink dev param set pci/0002:20:00.0 name egrp_create value \ "se:32;se.out" cmode runtime devlink dev param set pci/0002:20:00.0 name egrp_delete value \ "egrp:1" cmode runtime Signed-off-by: Srujana Challa <[email protected]> Signed-off-by: Shijith Thotton <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: octeontx2 - add apis for custom engine groupsSrujana Challa2-7/+322
Octeon TX2 CPT has three type of engines to handle symmetric, asymmetric and ipsec specific workload. For better utilization, these engines can be grouped to custom groups at runtime. This patch adds APIs to create and delete custom CPT engine groups. Signed-off-by: Srujana Challa <[email protected]> Signed-off-by: Shijith Thotton <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32 - Revert broken pm_runtime_resume_and_get changesHerbert Xu2-4/+5
We should not call pm_runtime_resume_and_get where the reference count is expected to be incremented unconditionally. This patch reverts these calls to the original unconditional get_sync call. Reported-by: Heiner Kallweit <[email protected]> Fixes: 747bf30fd944 ("crypto: stm32/cryp - Fix PM reference leak...") Fixes: 1cb3ad701970 ("crypto: stm32/hash - Fix PM reference leak...") Signed-off-by: Herbert Xu <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - reorder hw initializationNicolas Toromanoff1-13/+26
The CRYP IP checks the written key depending of the configuration, it's safer to write the whole configuration to hardware then the key to avoid unexpected key rejection. Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - fix bugs and crash in testsNicolas Toromanoff1-547/+243
Extra crypto manager auto test were crashing or failling due to 2 reasons: - block in a dead loop (dues to issues in cipher end process management) - crash due to read/write unmapped memory (this crash was also reported when using openssl afalg engine) Rework interrupt management, interrupts are masked as soon as they are no more used: if input buffer is fully consumed, "Input FIFO not full" interrupt is masked and if output buffer is full, "Output FIFO not empty" interrupt is masked. And crypto request finish when input *and* outpout buffer are fully read/write. About the crash due to unmapped memory, using scatterwalk_copychunks() that will map and copy each block fix the issue. Using this api and copying full block will also fix unaligned data access, avoid early copy of in/out buffer, and make useless the extra alignment constraint. Fixes: 9e054ec21ef8 ("crypto: stm32 - Support for STM32 CRYP crypto module") Reported-by: Marek Vasut <[email protected]> Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - fix lrw chaining modeNicolas Toromanoff1-1/+1
This fixes the lrw autotest if lrw uses the CRYP as the AES block cipher provider (as ecb(aes)). At end of request, CRYP should not update the IV in case of ECB chaining mode. Indeed the ECB chaining mode never uses the IV, but the software LRW chaining mode uses the IV field as a counter and due to the (unexpected) update done by CRYP while the AES block process, the counter get a wrong value when the IV overflow. Fixes: 5f49f18d27cd ("crypto: stm32/cryp - update to return iv_out") Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - fix double pm exitNicolas Toromanoff1-2/+0
Delete extraneous lines in probe error handling code: pm was disabled twice. Fixes: 65f9aa36ee47 ("crypto: stm32/cryp - Add power management support") Reported-by: Marek Vasut <[email protected]> Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - check early input dataNicolas Toromanoff1-1/+113
Some auto tests failed because driver wasn't returning the expected error with some input size/iv value/tag size. Now: Return 0 early for empty buffer. (We don't need to start the engine for an empty input buffer). Accept any valid authsize for gcm(aes). Return -EINVAL if iv for ccm(aes) is invalid. Return -EINVAL if buffer size is a not a multiple of algorithm block size. Fixes: 9e054ec21ef8 ("crypto: stm32 - Support for STM32 CRYP crypto module") Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - fix xts and race condition in crypto_engine requestsNicolas Toromanoff1-2/+0
Don't erase key: If key is erased before the crypto_finalize_.*_request() call, some pending process will run with a key={ 0 }. Moreover if the key is reset at end of request, it breaks xts chaining mode, as for last xts block (in case input len is not a multiple of block) a new AES request is started without calling again set_key(). Fixes: 9e054ec21ef8 ("crypto: stm32 - Support for STM32 CRYP crypto module") Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - fix CTR counter carryNicolas Toromanoff1-14/+13
STM32 CRYP hardware doesn't manage CTR counter bigger than max U32, as a workaround, at each block the current IV is saved, if the saved IV lower u32 is 0xFFFFFFFF, the full IV is manually incremented, and set in hardware. Fixes: bbb2832620ac ("crypto: stm32 - Fix sparse warnings") Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - don't print error on probe deferralEtienne Carriere1-1/+2
Change driver to not print an error message when the device probe is deferred for a clock resource. Signed-off-by: Etienne Carriere <[email protected]> Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-11crypto: stm32/cryp - defer probe for reset controllerEtienne Carriere1-2/+6
Change stm32 CRYP driver to defer its probe operation when reset controller device is registered but has not been probed yet. Signed-off-by: Etienne Carriere <[email protected]> Signed-off-by: Nicolas Toromanoff <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-03crypto: octeontx2 - uninitialized variable in kvf_limits_store()Dan Carpenter1-5/+4
If kstrtoint() fails then "lfs_num" is uninitialized and the warning doesn't make any sense. Just delete it. Fixes: 8ec8015a3168 ("crypto: octeontx2 - add support to process the crypto request") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-03crypto: sa2ul - Use bitfield helpersGeert Uytterhoeven1-9/+10
Use the FIELD_PREP() helper, instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-03crypto: caam - save caam memory to support crypto engine retry mechanism.Gaurav Jain3-0/+12
When caam queue is full (-ENOSPC), caam frees descriptor memory. crypto-engine checks if retry support is true and h/w queue is full(-ENOSPC), then requeue the crypto request. During processing the requested descriptor again, caam gives below error. (caam_jr 30902000.jr: 40000006: DECO: desc idx 0: Invalid KEY Command). This patch adds a check to return when caam input ring is full and retry support is true. so descriptor memory is not freed and requeued request can be processed again. Fixes: 2d653936eb2cf ("crypto: caam - enable crypto-engine retry mechanism") Signed-off-by: Gaurav Jain <[email protected]> Reviewed-by: Horia Geantă <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: hisilicon/qm - simplified the calculation of qos shaper parametersKai Ye1-29/+55
Some optimize for the calculation of qos shaper parameters. and modify the comments. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: hisilicon/qm - some optimizations of ths qos write processKai Ye1-41/+46
1. Optimize overly long functions. 2. Fix the format symbol does not match the actual type. 3. Use the PCI_DEVFN to get the function id. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: hisilicon/qm - modify the value of qos initializationKai Ye1-5/+7
The value of qos should be reset after flr resetting or device resetting. So set the max of qos value for every function. Then update the value of qos when user writing the alg_qos. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: hisilicon - modify the value of engine type rateKai Ye3-4/+4
Modify the value of type rate from new QM spec. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: sun8i-ce - Add support for the D1 variantCorentin Labbe2-0/+22
The Allwinner D1 SoC has a crypto engine compatible with sun8i-ce. Add support for it. Signed-off-by: Corentin Labbe <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - improve logging of PFVF messagesMarco Chiappero3-24/+17
Improve and simplify logging of PFVF messages. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - fix VF IDs in PFVF log messagesMarco Chiappero2-6/+6
PFVF debug messages use a mix of zero and one based VF IDs. Switch to zero based VF numbers in all log messages. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - do not rely on min versionMarco Chiappero10-32/+8
Remove min_iov_compat_ver field as for now all versions are compatible. Compatibility is determined by a series of rules and dynamic conditions such as specific configurations. In any case the minimum version requirement for compatibility is an inadequate and obsolete approach which should be removed. At this time compatibility can be assured across the currently available versions. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - refactor pfvf version request messagesMarco Chiappero1-19/+23
Refactor version handling logic for ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ and ADF_VF2PF_MSGTYPE_VERSION_REQ on the PF. Response messages are now filled only after fully parsing the request, in a consisted way with the rest of the PFVF codebase. This patch also fixes a harmless double setting for VERSION in the response for ADF_VF2PF_MSGTYPE_VERSION_REQ. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - pass the PF2VF responses back to the callersMarco Chiappero7-26/+33
Currently, any PF response to a VF request is fully parsed during the interrupt handling. This way the individual response values are stored into the accel_dev structure, preventing the caller to access and decode the full response message itself. Change this behavior, by letting the API return back the entire message to the caller, in order to: - keep correlated code together, that is, the (building of the) request and the (decoding of the) response; - avoid polluting the accel_dev data structure with unnecessary and at times temporary values; only the entire message is stored in a temporary buffer. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - use enums for PFVF protocol codesMarco Chiappero1-11/+22
Replace PFVF constants with enumerations for valid protocol codes. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - reorganize PFVF protocol definitionsMarco Chiappero1-17/+19
Organize PFVF protocol definitions by type rather than direction, by keeping related fields close. Also, make sure the order is consistent for both PF and VF definitions. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - reorganize PFVF codeMarco Chiappero22-276/+341
Reorganize the structure of the PFVF code by moving the content of adf_pf2vf_msg.c and adf_vf2pf_msg.c. The logic that handles high level messages has been moved to adf_pfvf_pf_msg.c and adf_pfvf_vf_msg.c. The implementation of low level communication primitives and the protocol is now included in adf_pfvf_pf_proto.c and adf_pfvf_vf_proto.c. In addition, the file adf_pf2vf_msg.h has been renamed in adf_pfvf_msg.h since it common to PF and VF and the copyright date for the touched files has been updated. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - abstract PFVF receive logicGiovanni Cabiddu4-44/+81
Refactor the PFVF receive logic so it is common between PF and VF and make it device specific. This is in preparation for the introduction of PFVF support in the qat_4xxx driver since the receive logic differs between QAT GEN2 and QAT GEN4 devices. Signed-off-by: Giovanni Cabiddu <[email protected]> Co-developed-by: Marco Chiappero <[email protected]> Signed-off-by: Marco Chiappero <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - abstract PFVF send functionMarco Chiappero4-91/+102
Make the PFVF send function device specific. This is in preparation for the introduction of PFVF support in the qat_4xxx driver since the send logic differs between QAT GEN2 and QAT GEN4 devices. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - differentiate between pf2vf and vf2pf offsetMarco Chiappero3-7/+10
Add the function get_vf2pf_offset() to adf_pfvf_ops to differentiate the CSRs used for pf2vf and vf2pf. Offsets may or may not be direction specific depending on QAT generation. Since in QAT GEN2 the CSR is not direction specific, i.e. there is a single mailbox register shared for pf2vf and vf2pf, both get_vf2pf_offset() and get_vf2pf_offset() will return the same offset. This change is to make the direction explicit, so it is easier to understand and debug and also in preparation for the introduction of PFVF support in the qat_4xxx driver since QAT GEN4 devices have a separate CSR for pf2vf and vf2pf communications. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - add pfvf_opsMarco Chiappero16-61/+76
Add pfvf_ops structure to isolate PFVF related functions inside the adf_hw_device_data structure. For GEN2, the structure is populated using one of the two helper functions, adf_gen2_init_pf_pfvf_ops() or adf_gen2_init_vf_pfvf_ops(), for the PF and VF driver respectively. For the DH895XCC PF driver, the structure is populated using adf_gen2_init_pf_pfvf_ops() but some of the functions are then overwritten. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - relocate PFVF disabled functionGiovanni Cabiddu3-6/+10
Move the function pfvf_comms_disabled() from the qat_4xxx module to intel_qat as it will be used by other components to keep the PFVF feature disabled. Signed-off-by: Giovanni Cabiddu <[email protected]> Reviewed-by: Marco Chiappero <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - relocate PFVF VF related logicMarco Chiappero11-29/+22
Move device specific PFVF logic related to the VF to the newly created adf_gen2_pfvf.c. This refactory is done to isolate the GEN2 PFVF code into its own file in preparation for the introduction of support for PFVF for GEN4 devices. Signed-off-by: Marco Chiappero <[email protected]> Reviewed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - relocate PFVF PF related logicMarco Chiappero9-69/+103
Move device specific PFVF logic related to the PF to the newly created adf_gen2_pfvf.c. This refactory is done to isolate the GEN2 PFVF code into its own file in preparation for the introduction of support for PFVF for GEN4 devices. In addition the PFVF PF logic for dh895xcc has been isolated to adf_dh895xcc_hw_data.c. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: qat - handle retries due to collisions in adf_iov_putmsg()Marco Chiappero1-33/+19
Rework __adf_iov_putmsg() to handle retries due to collisions internally, removing the need for an external retry loop. The functions __adf_iov_putmsg() and adf_iov_putmsg() have been merged together maintaining the adf_iov_putmsg() name. This will allow to use this function only for GEN2 devices, since collision are peculiar of this generation and therefore should be confined to the actual implementation of the transport/medium access. Note that now adf_iov_putmsg() will retry to send a message only in case of collisions and will now fail if an ACK is not received from the remote function. Signed-off-by: Marco Chiappero <[email protected]> Co-developed-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Giovanni Cabiddu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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