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2020-10-05drm/amdgpu: add TOC firmware support for apu (v3)Huang Rui4-10/+77
APU needs load toc firmware for gfx10 series on psp front door loading. v2: rebase against latest code v3: clarify error message Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add smu ip block for vangoghHuang Rui1-0/+1
This patch is to add ip block for vangogh. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: add vangogh ppt into swSMUHuang Rui2-0/+5
This patch is to add vangogh ppt funcions into swSMU block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: partially enable swsmu for vangoghHuang Rui1-0/+6
This patch is to partially enable swSMU for vangogh for the moment. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v4)Xiaojian Du2-0/+384
This patch is to add smu initialize functions for vangogh. v2: squash in updates v3: drop duplicate table entries v4: rebase fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2)Xiaojian Du2-0/+4
This patch is to add vangogh asic name in smu v11. v2: drop smu firmware name (N/A for VG) Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 smc header for vangoghXiaojian Du1-0/+86
This patch is to add smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2)Xiaojian Du1-0/+120
This patch is to add smu v11.5 firmware header for vangogh v2: squash in updates Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/admgpu/powerplay: add smu v11.5 driver interface header for vangoghXiaojian Du1-0/+239
This patch is to add smu v11.5 driver interface header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2)Xiaojian Du1-6/+47
This patch is to add new smu messages and feature masks for vangogh. v2: squash in updates and typo fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add nbio v7.2 for vangogh (v2)Huang Rui4-3/+383
VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio v2.3 for navi series, so add new nbio v7.2 block. v2: squash in fix for sdma and vcn instances Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add pcie port indirect read and write on nvHuang Rui2-0/+34
This patch is to add pcie port indirect read/write callback for nv series. They will be used for new asic. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: enable vcn3.0 for van goghThong Thai2-0/+10
Same as other VCN 3.0 asics. Signed-off-by: Thong Thai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add mmhub v2.3 for vangogh (v4)Huang Rui4-2/+590
There are too many register offset mismatch between mmhub v2.0 and v2.3. E.X: mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32: 0x072b(v2.0) 0x0940(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32: 0x072c(v2.0) 0x0941(v2.3) mmMMVM_INVALIDATE_ENG0_REQ: 0x06e3(v2.0) 0x0a01(v2.3) mmMMVM_INVALIDATE_ENG0_ACK: 0x06f5(v2.0) 0x0a02(v2.3) mmMMVM_CONTEXT0_CNTL: 0x06c0(v2.0) 0x0740(v2.3) mmMMVM_L2_PROTECTION_FAULT_STATUS: 0x068c(v2.0) 0x070c(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmDAGB0_CNTL_MISC2: 0x0071(v2.0) 0x0096(v2.3) ... Continuing using the same file mmhub v2.0 is not good choice, it will introduce a lot of checking with ASIC types. And also easy to introduce the issues that offset not align, this kind of issues are really hard to find. Van Gogh's mmhub vm invalidation is actually caused by the offset mismatch as well. So it would like to create a new file rather than stick to re-use orignal mmhub v2.0 here. v2: add missed translate_further programming. v3: sync with latest code v4: add missing callbacks Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdkfd: add Van Gogh KFD supportHuang Rui6-0/+29
This patch is to add GFX10 based APU Van Gogh KFD support. We will treat Van Gogh as "dgpu" (bypass IOMMU v2). Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: set ip blocks for van goghHuang Rui1-0/+9
Enable ip blocks for van gogh. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add sdma support for van goghHuang Rui1-0/+10
This patch adds the sdma v5.2 support for van gogh. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/gfx10: add updated register offsets for VGHAlex Deucher1-2/+16
Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gfx golden settings for vangogh (v3)Huang Rui1-1/+35
This patch is to add gfx golden settings for vangogh post si. v2: squash in updates v3: fix SPI register offset Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gfx support for van gogh (v3)Huang Rui1-1/+28
Add van gogh checks to gfx10 code. v2: squash in fixes v3: fix mode Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: set fw load type for van goghHuang Rui1-0/+2
This patch sets fw load type as direct for van gogh for the moment. Will switch to psp when psp is ready. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gmc v10 supports for van gogh (v4)Huang Rui1-1/+15
Add gfx memory controller support for van gogh. v2: don't use dynamic invalidate eng allocation for van gogh. v3: squash in other fixes v4: rebase Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: get the correct vram type for van goghHuang Rui2-0/+5
This patch is to get the correct vram type from atombios for van gogh. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tablesRoman Li1-1/+61
Required for vangogh. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: update new memory types in atomfirmware headerHuang Rui1-0/+5
Add new nemory types in atomfirmware header. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: use gpu virtual address for interrupt packet write space for vangoghHuang Rui1-2/+5
The interrupts are not stable while uses guest physical address (GPA) for interrupt packet write space even on direct loading case. v2: make condition more readable Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add van gogh support for ih blockHuang Rui1-0/+1
This patch adds the support for van gogh ih block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)Huang Rui1-1/+2
Van gogh only has one sdma. v2: use num_instances rather than APU flag Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add nv common ip block support for van goghHuang Rui1-0/+8
This patch adds common ip support for van gogh. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add vangogh_reg_base_init function for van goghHuang Rui4-1/+1568
This patch adds vangogh_reg_base_init function to init the register base for van gogh. v2: make vangogh_reg_base_init void, align equality sign Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add van gogh support for gpu_info and ip block settingHuang Rui1-1/+9
This patch adds van gogh support for gpu_info firmware and ip block setting. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add van gogh asic_type enum (v2)Huang Rui1-0/+1
This patch adds van gogh to amd_asic_type enum and amdgpu_asic_name[]. v2: add missing comma Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add vangogh asic header files (v2)Huang Rui11-0/+266481
This patch is to add vangogh asic header files. v2: squash in updates Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: HDMI remote sink need mode validation for LinuxFangzhi Zuo1-1/+1
[Why] Currently mode validation is bypassed if remote sink exists. That leads to mode set issue when a BW bottle neck exists in the link path, e.g., a DP-to-HDMI converter that only supports HDMI 1.4. Any invalid mode passed to Linux user space will cause the modeset failure due to limitation of Linux user space implementation. [How] Mode validation is skipped only if in edid override. For real remote sink, clock limit check should be done for HDMI remote sink. Have HDMI related remote sink going through mode validation to elimiate modes which pixel clock exceeds BW limitation. Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Change to correct unit on audio rateChris Park1-3/+2
[Why] Formula uses kHz in their formula while our driver operates with Hz. [How] Divide audio rate by 1000 on the initial variable that is entered into formula. Signed-off-by: Chris Park <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Eryk Brol <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Avoid set zero in the requested clkRodrigo Siqueira1-2/+1
[Why] Sometimes CRTCs can be disabled due to display unplugging or temporarily transition in the userspace; in these circumstances, DCE tries to set the minimum clock threshold. When we have this situation, the function bw_calcs is invoked with number_of_displays set to zero, making DCE set dispclk_khz and sclk_khz to zero. For these reasons, we have seen some ATOM bios errors that look like: [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for more than 5secs aborting [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck executing EA8A (len 761, WS 0, PS 0) @ 0xEABA [How] This error happens due to an attempt to optimize the bandwidth using the sclk, and the dispclk clock set to zero. Technically we handle this in the function dce112_set_clock, but we are not considering the case that this value is set to zero. This commit fixes this issue by ensuring that we never set a minimum value below the minimum clock threshold. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: align frag_end to covered address spaceAlex Sierra1-0/+2
align frag_end to the next pd when there are no page table entries on the current pde. This fixes invalidation of larger address space areas where some page tables are allocated and other aren't. Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: fix NULL pointer dereference for RenoirDirk Gouders1-5/+5
Commit c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") introduced a NULL pointer dereference when booting with amdgpu.discovery=0, because it removed the call of vega10_reg_base_init() for that case. Fix this by calling that funcion if amdgpu_discovery == 0 in addition to the case that amdgpu_discovery_reg_base_init() failed. Fixes: c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") Signed-off-by: Dirk Gouders <[email protected]> Cc: Hawking Zhang <[email protected]> Cc: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu/swsmu: add interrupt work handler for smu11 partsAlex Deucher5-2/+13
We need to schedule the smu AC/DC interrupt ack to avoid potentially sleeping if the smu message mutex is contended. Fixes: e1188aacad1730 ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu/swsmu: add interrupt work functionAlex Deucher2-0/+17
So we can schedule work from interrupts. This might include long tasks or things that could sleep. Fixes: e1188aacad1730 ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu: enable GDDR6 save-restore support for navy_flounderHawking Zhang1-0/+1
add mp0 11_0_11 for navy_flounder to the mem training supported list, otherwise the modeprobe would fail on navy_flounder with latest vbios. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu: support indirect access reg outside of mmio bar (v2)Hawking Zhang4-71/+53
support both direct and indirect accessor in unified helper functions. v2: Retire indirect mmio access via mm_index/data Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu: switch to indirect reg access helperHawking Zhang2-86/+16
Switch WREG32/RREG32_PCIE to use indirect reg access helper for soc15 and onwards Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu: add helper function for indirect reg access (v3)Hawking Zhang2-0/+142
Add helper function in order to remove RREG32/WREG32 in current pcie_rreg/wreg function for soc15 and onwards adapters. PCIE_INDEX/DATA pairs are used to access regsiters outside of mmio bar in the helper functions. The new helper functions help remove the recursion of amdgpu_mm_rreg/wreg from pcie_rreg/wreg and provide the oppotunity to centralize direct and indirect access in a single function. v2: Fixed typo and refine the comments v3: Remove unnecessary volatile local variable Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/amdkfd: Surface files in Sysfs to allow users to get number ofRamesh Errabolu2-2/+94
compute units that are in use. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Surface files in Sysfs that allow user to determine the number of compute units that are in use for a given process. One Sysfs file is used per device. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-By: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/amdgpu: Define and implement a function that collects number ofRamesh Errabolu2-0/+187
waves that are in flight. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-By: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: disable gfxoff temporarily for navy_flounderJiansong Chen1-0/+3
gfxoff is temporarily disabled for navy_flounder, since at present the feature caused some tdr when performing display operations. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: drop duplicated ecc check for vega10 (v5)Guchun Chen1-12/+7
The same ECC check has been executed in amdgpu_ras_init for vega10, prior to gmc_v9_0_late_init. v2: drop all atombios helper callings v3: use bit operation v4: correct inline comment, remove parity check statement v5: squash in build fix Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amd/display: add pipe reassignment prevention code to dcn3Dmytro Laktyushkin1-12/+49
Add code to gracefuly handle any pipe reassignment occuring on dcn3 hardware. This should only happen when new surfaces are used for an update rather than old ones updated. Fixes: 69fc1f4b976cea ("amd/drm/display: avoid dcn3 on flip opp change for slave pipes") Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-30drm/amdgpu: use function pointer for gfxhub functionsOak Zeng15-83/+155
gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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