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2020-10-26drm/amd/display: 3.2.107Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add an option to limit max DSC target bpp per sinkNikola Cornij5-13/+27
[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by: Nikola Cornij <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: [FW Promotion] Release 0.0.37Anthony Koo1-2/+2
| [Header Changes] | - Add GPINT to change timestamping mode for traces Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Define PSR ERROR Status bit VSC_SDPReza Amini1-1/+2
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by: Reza Amini <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Raise DPG height during timing synchronizationTaimur Hassan5-1/+41
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by: Taimur Hassan <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Set WM set A to 0 if full pstate not supportedAlvin Lee1-1/+1
[Why] If full pstate is not supported, we should set WM set A to 0 to prevent any hangs [How] If pstate is not supported, set watermark set A to 0 Signed-off-by: Alvin Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Reverting "Add connector to the state if DSC debugfs is set"Eryk Brol1-42/+0
This reverts commit c44a22b3128d143a66421004b728eed688c21ee6. Reason for revert: Patch introduces performance issues and might cause memory consistency problems with multiple connectors. Signed-off-by: Eryk Brol <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Source minimum HBlank supportAshley Thomas14-7/+49
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by: Ashley Thomas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: enable odm + full screen mpo on dcn21Dmytro Laktyushkin4-8/+52
[WHY & HOW] Enable ODM Combine + Fullscreen MPO on DCN2.1 For lower power consumption in video use cases. Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: add dcn21 bw validationDmytro Laktyushkin3-2/+122
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add Bounding Box State for Low DF PState but High Voltage StateSung Lee1-18/+53
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: nuke amdgpu_vm_bo_split_mapping v2Christian König1-103/+79
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by: Christian König <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> (v1) Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: increase the reserved VM size to 2MBChristian König1-2/+2
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by: Christian König <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/pm: update driver if version for dimgrey_cavefishTao Zhou1-1/+1
Per PMFW 59.9.0. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: added support for psp fw attestationJohn Clements7-20/+250
loaded fw can be queried from sys fs interface Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: enable IP discovery for vangoghXiaomeng Hou1-4/+0
enable IP discovery for vangogh. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amd/display: Fixed panic during seamless boot.David Galiffi1-1/+2
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by: David Galiffi <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: Fix size calculation when init onchip memoryxinhui pan1-2/+2
Size is page count here. Reviewed-by: Christian König <[email protected]> Signed-off-by: xinhui pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu_dm: fix a typoMauro Carvalho Chehab2-4/+4
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: fix some kernel-doc markupsMauro Carvalho Chehab2-2/+2
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by: Christian König <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23amdgpu: fix a few kernel-doc markup issuesMauro Carvalho Chehab1-3/+5
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by: Christian König <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: During compute disable GFXOFF for Sienna_CichlidHarish Kasiviswanathan1-0/+7
Workaround to fix the soft hang observed in certain compute applications. Acked-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: don't map BO in reserved regionMadhav Chauhan1-0/+10
2MB area is reserved at top inside VM. Suggested-by: Christian König <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu/display: add MALL support (v2)Bhawanpreet Lakha7-1/+110
Enable Memory Access at Last Level (MALL) feature for display. v2: squash in 64 bit division fixes Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)Likun Gao3-2/+6
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid. v2: drop module option. We need to add UAPI so userspace can request MALL per buffer. Reviewed-by: Christian König <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher3-0/+36
This adds the NOALLOC registers. Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: remove unneeded breakTom Rix7-43/+0
A break is not needed if it is preceded by a return or break Reviewed-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add DID for navi10 blockchain SKUTianci.Yin1-0/+1
Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin1-2/+12
The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: correct the cu and rb info for sienna cichlidLikun Gao1-0/+9
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amd/pm: remove the average clock value in sysfsKenneth Feng1-4/+8
if it's fine-grained clock dpm, remove the average clock value and reflects the real clock. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm: amdgpu: kernel-doc: update some adev parametersMauro Carvalho Chehab3-21/+20
Running "make htmldocs: produce lots of warnings on those files: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' They're related to the repacement of some parameters by adev, and due to a few renamed parameters. While here, uniform the name of the parameter for it to be the same on all functions using a pointer to struct amdgpu_device. Update the kernel-doc documentation accordingly. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amdgpu: Return boolean types instead of integer valuesSumera Priyadarsini1-2/+2
Return statements for functions returning bool should use truth and false instead of 1 and 0 respectively. Modify cik_event_interrupt.c to return false instead of 0. Issue found with Coccinelle. Signed-off-by: Sumera Priyadarsini <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/display: Fix the display corruption issue on Navi10Yifan Zhang1-3/+7
[Why] Screen corruption on Navi10 card [How] Set system context in DCN only on Renoir Tested-by: Matt Coffin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/pm: fix pp_dpm_fclkKenneth Feng1-0/+3
fclk value is missing in pp_dpm_fclk. add this to correctly show the current value. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21Revert drm/amdgpu: disable sienna chichlid UMC RASJohn Clements1-2/+2
This reverts commit 265c280a4807419249644156654e5c40a235ea84. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/pm: fix the wrong fan speed in fan1_inputKenneth Feng1-8/+3
fix the wrong fan speed in fan1_input when the fan control mode is manual. the fan speed value is not correct when we set manual mode to fan1_enalbe - 1. since the fan speed in the metrics table always reflects the real fan speed,we can fetch the fan speed for both auto and manual mode. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/display: Initialize num_pkrs on VANGOGH.Bas Nieuwenhuizen1-1/+2
As far a I can tell uses a variant of DCN3xx which uses num_pkrs. If we do not initialize the variable we will set the register field to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure 7 is not the value we want here. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-and-Tested-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/pm: update driver if file for sienna cichlidLikun Gao2-3/+13
Update driver if file for sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/pm: fix pcie information for sienna cichlidLikun Gao1-2/+2
Fix the function used for sienna cichlid to get correct PCIE information by pp_dpm_pcie. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amdgpu/gmc10: remove dummy read workaround for newer chipsAlex Deucher1-2/+4
Sienna Cichlid and newer have a hw fix so no longer require the workaround. Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/amdgpu: enable noretry for Sienna_Cichlid/Navy_Flounder/Dimgrey_CavefishChengming Gui1-0/+3
set noretry default value to 1 for sienna_cichlid/navy_founder/dimgrey_cavefish. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amdgpu: enable VCN PG and CG for vangoghBoyuan Zhang1-2/+7
Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amdkfd: Use same SQ prefetch setting as amdgpuJay Cornwall1-2/+3
0 causes instruction fetch stall at cache line boundary under some conditions on Navi10. A non-zero prefetch is the preferred default in any case. Fixes soft hang in Luxmark. Signed-off-by: Jay Cornwall <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amd/swsmu: correct wrong feature bit mappingKevin Wang1-10/+17
1. when smc feature bit isn't mapped, the feature state isn't showed on sysfs node of pp_features. 2. add pp_features table title Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-21drm/amdgpu: protect eeprom update from GPU resetDennis Li1-0/+8
because i2c is unstable in GPU reset, driver need protect eeprom update from GPU reset, to not miss any bad page record. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-16drm/amdgpu: move amdgpu_num_kcq handling to a helperAlex Deucher8-12/+22
Add a helper so we can set per asic default values. Also, the module parameter is currently clamped to 8, but clamp it per asic just in case some asics have different limits in the future. Enable the option on gfx6,7 as well for consistency. Acked-by: Nirmoy Das <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-16drm/amd/psp: Fix sysfs: cannot create duplicate filenameAndrey Grodzovsky1-1/+2
psp sysfs not cleaned up on driver unload for sienna_cichlid Fixes: ce87c98db428e7 ("drm/amdgpu: Include sienna_cichlid in USBC PD FW support.") Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-16drm/amd/display: Fix DCN302 makefileBhawanpreet Lakha1-0/+29
Some setups will fail to build. So copy dcn301 makefile setup which is known to work Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-16drm/amd/display: Use amdgpu_socbb.h instead of redefining structsBhawanpreet Lakha1-57/+1
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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