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2022-07-19drm/panel/panel-sitronix-st7701: Infer horizontal pixel count from TFT modeMarek Vasut1-6/+15
The horizontal pixel count is a property of the TFT matrix. Currently the driver hard-codes content of this register to specific value which is only compatible with one TFT matrix, likely the TS8550B one. Calculate the horizontal pixel count from the mode instead. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Adjust porch control bitfield nameMarek Vasut1-4/+6
Define DSI_CMD2_BK0_PORCTRL_VBP_MASK and DSI_CMD2_BK0_PORCTRL_VFP_MASK and move the vertical back and front porch calculation from macros into the st7701_init_sequence() function, so it is clear what this does. No functional change. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Infer vertical line count from TFT modeMarek Vasut1-6/+20
The vertical line count is a property of the TFT matrix. Currently the driver hard-codes content of this register to specific value which is only compatible with one TFT matrix, likely the TS8550B one. Calculate the vertical line count from the mode instead. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Make gamma correction TFT specificMarek Vasut1-7/+89
The gamma correction values are specific to the TFT which is attached to the ST7701 TFT matrix driver, move the gamma correction values from what incorrectly looks like common init sequence into TFT matrix specific settings. While doing so, add macros which defined fields within the gamma register file and a macro which mimics FIELD_PREP except works with constant expressions. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Make voltage supplies common to ST7701Marek Vasut1-22/+7
The ST7701 and ST7701S all have two voltage supplies, one for internal logic and one for the TFT matrix driver. The supplies are not property of the TFT matrix driver, so move them to common ST7701 code. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Enable DSI burst mode, LPM, non-continuous ↵Marek Vasut1-1/+2
clock The ST7701(S) is capable of DSI burst mode, which is more energy efficient than the non-burst modes. Make use of it. The ST7701(S) is capable of DSI non-continuous clock, since it sources the TFT matrix driver clock from internal clock source. The DSI non-continuous clock further reduce power utilization. The ST7701(S) uses DSI LPM for command transmissions, make sure this is configured correctly in the DSI mode flags. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm/panel/panel-sitronix-st7701: Make DSI mode flags common to ST7701Marek Vasut1-3/+1
The ST7701 and ST7701S are TFT matrix drivers with integrated multi protocol decoder capable of DSI/DPI/SPI input and 480x360...864 line TFT matrix output. Currently the only supported input is DSI. The protocol decoder is separate from the TFT matrix driver and is always capable of handling all of DSI non-burst mode with sync pulses or sync events as well as DSI burst mode. Move the DSI mode configuration from TFT matrix driver properties to common ST7701 code, because this is common to all TFT matrices. Signed-off-by: Marek Vasut <[email protected]> Cc: Guido Günther <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Thierry Reding <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm:remove rebundant word "in" in commentsshaomin Deng1-1/+1
there is a repeated word "in", so remove it. Signed-off-by: shaomin Deng <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-19drm:delete the repeated word "the" in commentsshaomin Deng1-1/+1
remove the rebundant word "the" from comments. Signed-off-by: shaomin Deng <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-18drm/amd/pm: enable mode1 reset for smu_v13_0_7Kenneth Feng2-0/+2
enable mode1 reset for smu_v13_0_7 since it's missing. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: correct the PSP_BL_CMD enumHawking Zhang1-2/+2
To match with the enum defined in trusted os Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: drop runpm from amdgpu_device structureGuchun Chen3-19/+15
It's redundant, as now switching to rpm_mode to indicate runtime power management mode. Suggested-by: Lijo Lazar <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: drop runtime pm disablement quirk on several sienna cichlid cardsGuchun Chen1-13/+0
This quirk is not needed any more as it's fixed by bypassing SMU FW reloading in runtime resume. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: skip SMU FW reloading in runpm BACO caseGuchun Chen1-0/+7
SMU is always alive, so it's fine to skip SMU FW reloading when runpm resumed from BACO, this can avoid some race issues when resuming SMU. Suggested-by: Evan Quan <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: introduce runtime pm modeGuchun Chen2-1/+14
It can benefit code consistency in future. Suggested-by: Lijo Lazar <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amd/display: Remove unnecessary NULL check in commit_planes_for_stream()Dan Carpenter1-1/+1
Smatch complains that: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3369 commit_planes_for_stream() warn: variable dereferenced before check 'stream' (see line 3114) The 'stream' pointer cannot be NULL and the check can be removed. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: Clarify asics naming in Kconfig optionsAndré Almeida1-2/+3
Clarify which architecture those asics acronyms refers to. Signed-off-by: André Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amd/display: Fix spelling mistake "supporing" -> "supporting"Colin Ian King1-1/+1
There is a spelling mistake in a dml_print message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amd/display: Enable building new display engine with KCOV enabledGuenter Roeck2-1/+4
The new display engine uses floating point math, which is not supported by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") tried to work around the problem by disabling CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS are enabled. The result is that KCOV can not be enabled on systems which require this display engine. A much simpler and less invasive solution is to disable KCOV selectively when compiling the display enagine while keeping it enabled for the rest of the kernel. Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") Cc: Arnd Bergmann <[email protected]> Cc: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: restore original stable pstate on ctx finiAlex Deucher1-27/+33
Save the original stable pstate on ctx init and restore it on ctx fini so that we restore a manually selected stable pstate on ctx exit. v2: fix init order (Alex) v3: don't add new variable to ctx struct (Evan) Fixes: c65b364c52ba ("drm/amdgpu/ctx: only reset stable pstate if the user changed it (v2)") Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: use the same HDP flush registers for all nbio 2.3.xAlex Deucher3-26/+1
Align RDNA2.x with other asics. One HDP bit per SDMA instance, aligned with firmware. This is effectively a revert of commit 369b7d04baf3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12"). On further discussions with the relevant hardware teams, re-align the bits for SDMA. Fixes: 369b7d04baf3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12") Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: use the same HDP flush registers for all nbio 7.4.xAlex Deucher3-26/+1
Align aldebaran with all other asics. One HDP bit per SDMA instance, aligned with firmware. This is effectively a revert of commit a0f9f8546668 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12"). On further discussions with the relevant hardware teams, re-align the bits for SDMA. Fixes: a0f9f8546668 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12") Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: create I2S platform devices for Jadeite platformVijendar Mukunda1-109/+184
Jadeite platform uses I2S MICSP instance. Create platform devices for DMA controller and I2S controller for Jadeite platform. Signed-off-by: Vijendar Mukunda <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: add dmi check for jadeite platformVijendar Mukunda1-0/+36
DMI check is required to distinguish Jadeite platform from Stoney base variant. Add DMI check logic for Jadeite platform. Signed-off-by: Vijendar Mukunda <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: Call trace info was found in dmesg when loading amdgpulin cao1-1/+3
In the case of SRIOV, the register smnMp1_PMI_3_FIFO will get an invalid value which will cause the "shift out of bound". In Ubuntu22.04, this issue will be checked an related call trace will be reported in dmesg. Signed-off-by: lin cao <[email protected]> Reviewed-by: Jingwen Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: fix for coding style issuesVijendar Mukunda1-23/+12
Fixed below checkpatch warnings and errors drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:131: CHECK: Comparison to NULL could be written "apd" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:150: CHECK: Comparison to NULL could be written "apd" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:196: CHECK: Prefer kernel type 'u64' over 'uint64_t' drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:224: CHECK: Please don't use multiple blank lines drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:226: CHECK: Comparison to NULL could be written "!adev->acp.acp_genpd" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:233: CHECK: Please don't use multiple blank lines drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:239: CHECK: Alignment should match open parenthesis drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:241: CHECK: Comparison to NULL could be written "!adev->acp.acp_cell" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:247: CHECK: Comparison to NULL could be written "!adev->acp.acp_res" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:253: CHECK: Comparison to NULL could be written "!i2s_pdata" drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:350: CHECK: Alignment should match open parenthesis drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:550: ERROR: that open brace { should be on the previous line Signed-off-by: Vijendar Mukunda <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: add umc ras functions for umc v8_10_0YiPeng Chai5-2/+464
1. Support query umc ras error counter. 2. Support ras umc ue error address remapping. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: add umc v8_10_0 ip headersYiPeng Chai2-0/+127
Add umc v8_10_0 register offset and shift masks header files Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: Get rid of amdgpu_job->external_hw_fenceAndrey Grodzovsky3-25/+6
This is a follow-up cleanup to [1]. See bellow refcount balancing for calling amdgpu_job_submit_direct after this cleanup as far as I calculated. amdgpu_fence_emit dma_fence_init 1 dma_fence_get(fence) 2 rcu_assign_pointer(*ptr, dma_fence_get(fence) 3 ---> amdgpu_job_submit_direct completes before fence signaled amdgpu_sa_bo_free (*sa_bo)->fence = dma_fence_get(fence) 4 amdgpu_job_free dma_fence_put 3 amdgpu_vcn_enc_get_destroy_msg *fence = dma_fence_get(f) 4 dma_fence_put(f); 3 amdgpu_vcn_enc_ring_test_ib dma_fence_put(fence) 2 amdgpu_fence_process dma_fence_put 1 amdgpu_sa_bo_remove_locked dma_fence_put 0 ---> amdgpu_job_submit_direct completes after fence signaled amdgpu_fence_process dma_fence_put 2 amdgpu_job_free dma_fence_put 1 amdgpu_vcn_enc_get_destroy_msg *fence = dma_fence_get(f) 2 dma_fence_put(f); 1 amdgpu_vcn_enc_ring_test_ib dma_fence_put(fence) 0 [1] - https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/ Signed-off-by: Andrey Grodzovsky <[email protected]> Suggested-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: limiting AV1 to first instance on VCN4 decodeSonny Jiang1-0/+131
AV1 is only supported on first instance. Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/mgag200:remove rebundant word "or" in commentsshaomin Deng1-1/+1
there is a repeated word "or" in comments, so remove it. Signed-off-by: shaomin Deng <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-18drm/bridge: it6505: Modified video clock calculation and video debug messageallen chen1-4/+2
Speed up video clock calculation and remove redundant video debug message. Signed-off-by: Pin-Yen Lin <[email protected]> Signed-off-by: Allen Chen <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-18drm/bridge: it6505: Add i2c api power on checkallen chen1-2/+10
Use i2c bus to read/write when it6505 power off will occur i2c error. Add this check will prevent i2c error when it6505 power off. Signed-off-by: Pin-Yen Lin <[email protected]> Signed-off-by: Allen Chen <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-18drm/bridge: it6505: Modified power sequenceallen chen1-1/+1
Change power sequence to meet it6505 data sheet requirement when boot on. Signed-off-by: Pin-Yen Lin <[email protected]> Signed-off-by: Allen Chen <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-18drm/bridge: it6505: Power on downstream device in .atomic_enablePin-Yen Lin1-0/+3
Send DPCD DP_SET_POWER_D0 command to the monitor in .atomic_enable callback. Without this command, some monitors won't show up again after changing the resolution. Fixes: 46ca7da7f1e8 ("drm/bridge: it6505: Send DPCD SET_POWER to downstream") Signed-off-by: Pin-Yen Lin <[email protected]> Reviewed-by: Allen Chen <[email protected]> Fixes: 46ca7da7f1e8 ("drm/bridge: it6505: Send DPCD SET_POWER to downstream") Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20220714173715.v2.1.I85af54e9ceda74ec69f661852825845f983fc343@changeid
2022-07-18drm/ssd130x: Use new regmap bulk write support to drop custom busJavier Martinez Canillas1-16/+5
Data writes for the ssd130x 4-wire SPI protocol need special handling, due the Data/Command control (D/C) pin having to be toggled prior to the write. The regmap API only allowed drivers to provide .reg_{read,write} callbacks to do per register read/write, but didn't provide a way for drivers to do the same for bulk read/writes. For this reason, a custom regmap bus was used by the driver just to define a bulk write callback that implements the D/C pin toggling. But the regmap API has been extended to support defining bulk read/write handlers, so the custom regmap bus is not needed anymore and could just be dropped. Signed-off-by: Javier Martinez Canillas <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Fix style issues in via_3d_reg headerSam Ravnborg1-13/+13
- Fix comments using wrong style - Drop repeated word This fixes all checkpatch complains and makes the file a little bit easier to read - as the eye is not distracted by the style violations. Suggested-by: Thomas Zimmermann <[email protected]> Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Make macros readable in the via_3d_reg headerSam Ravnborg1-148/+74
The macros for texture 1 setting all used continuation on a new line, resulting in a highly ureadable definition. Merge the lines so they are each on a single line. As a nice side-effect this fixes a number of checkpatch warnings: "WARNING: please, no spaces at the start of a line". Suggested-by: Thomas Zimmermann <[email protected]> Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Use SPDX tag for MIT license in via_3d_reg headerSam Ravnborg1-19/+1
The license for the via_3d_reg header is MIT - so use the shorter SPDX tag to identify the license. Suggested-by: Thomas Zimmermann <[email protected]> Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Update to the latest via_3d_reg headerSam Ravnborg1-91/+304
Updated the 3d_reg header file to match what is used by the openchrome driver. This verifies that the two drivers can use the same header file. The file is a verbatim copy from the openchrome repo - a few style issues will be fixed in following commits. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_drv.h in via_dri1Sam Ravnborg2-266/+228
With this change the driver is now a signle file driver. The only remaning heder file describes the HW and can be shared with the new openchrome driver. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_verifier in via_dri1Sam Ravnborg5-1175/+1099
Embed the header file in via_drv.h and the code in via_dri1. All functions are made static as there are no more external users. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_dmablit in via_dri1Sam Ravnborg5-956/+835
Embed some of the header file in via_drv.h and the rest in via_dri1.c While embedding deleted extra empty lines and functions that has no external users are made static. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_irq in via_dri1Sam Ravnborg4-398/+348
All functions are made static as there are no more external users. The file had new copyrights that are kept. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_video in via_dri1Sam Ravnborg4-100/+66
All functions are made static as there are no more external users. The file had a new copyright that is kept. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_mm in via_dri1Sam Ravnborg4-251/+209
All functions was made static as there are no external users. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_map in via_dri1Sam Ravnborg4-137/+103
A few functions has no external use and are made static. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Embed via_dma in via_dri1Sam Ravnborg4-749/+703
Moved the copyright notices so all copyrights are kept. A few variables was made static as there are no more users outside this file. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-16drm/via: Rename via_drv to via_dri1Sam Ravnborg2-1/+1
The via driver implements the DRI1 interface, and we have a new implementation of the via driver coming that supports atomic modesetting. It is not acceptable just to replace the existing driver so this is first step to make it a single-file implementation allowing it to stay without interfering with the new driver. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Cc: Kevin Brace <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-07-15drm/nouveau/bios: set info only when the return is not 0Tom Rix1-4/+1
clang static analysis reports drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c:68:17: warning: The right operand of '*' is a garbage value [core.UndefinedBinaryOperatorResult] switch (!!data * *ver) { ^ ~~~~ A switch statement with only a default should be reduced to an if. If nvbios_pmuEp() returns 0, via the data variable, the output info parameter is not used. So set info only when data is not 0. The struct nvbios_pmuE only has the type and data elements. Since both of these are explicitly set, memset is not needed. So remove it. Signed-off-by: Tom Rix <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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