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That has never proven useful in any way. Just remove it.
Signed-off-by: Felipe Balbi <[email protected]>
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This patch simply renames two functions to more descriptive names so
that it's easier to understand what they're doing.
Cleanup only, no functional changes.
Signed-off-by: Felipe Balbi <[email protected]>
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Instead of constantly calling kick transfer everything some event
shows up, let's just rely on the fact that we send Update Transfer
every time a new request is queued.
Signed-off-by: Felipe Balbi <[email protected]>
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Now that we're making sure we don't have XferComplete events, we can
rename this function to what it actually handles:
dwc3_gadget_endpoint_transfer_in_progress()
Signed-off-by: Felipe Balbi <[email protected]>
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XferComplete is enabled only for the default control pipe, let's make
that clear in the code.
Signed-off-by: Felipe Balbi <[email protected]>
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We don't use XferNotReady for anything other than Default Control
Pipe, which is handled in ep0.c, and Isochronous endpoints. Let's make
that clear in the code.
Signed-off-by: Felipe Balbi <[email protected]>
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Interrupt endpoints behave much like Bulk endpoints with the exception
that they are periodic. We can pre-issue Start Transfer exactly as we
do for Bulk endpoints.
While at that, remove one trailing blank line which is unnecessary.
Signed-off-by: Felipe Balbi <[email protected]>
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The present code correctly fetches the req which were previously not
queued from the started_list but fails to continue queuing from the sg
where it previously stopped queuing (because of the unavailable TRB's).
This patch correct's the code to continue queuing from the correct sg
present in the sglist.
For example, consider 5 sgs in req. Because of limited TRB's among the
5 sgs only 3 got queued. This patch corrects the code to start queuing
from correct sg i.e 4th sg when the TRBs are available.
Signed-off-by: Anurag Kumar Vulisha <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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The code logic in dwc3_prepare_one_trb() incorrectly uses the address
and length fields present in req packet for mapping TRB's instead of
using the address and length fields of scattergather lists. This patch
correct's the code to use sg->address and sg->length when scattergather
lists are present.
Signed-off-by: Anurag Kumar Vulisha <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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extcon device is used to detect host/device connection. Since extcon
OF property is deprecated, alternative method should be added.
This method uses OF graph bindings to locate extcon.
Signed-off-by: Andrzej Hajda <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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It is not a good idea to directly modify the resource of a platform
device. Modify its local copy, and pass it to devm_ioremap_resource()
so that we do not need to restore it in the failure path and the remove
hook.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Masami Hiramatsu <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support
runtime PM to reduce PHY power consumption during bus_suspend.
Add changes to let core auto-suspend PHYs on host bus-suspend
using GUSB2PHYCFG register if needed for a platform. Also perform
PHYs runtime suspend/resume and let platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
Some of its uses are described below resulting in need to
have a separate glue driver instead of using dwc3-of-simple:
- It exposes register interface to override vbus-override
and lane0-pwr-present signals going to hardware. These
must be updated in peripheral mode for DWC3 if vbus lines
are not connected to hardware block. Otherwise RX termination
in SS mode or DP pull-up is not applied by device controller.
- pwr_events_irq_stat support to check if USB2 PHY is in L2 state
before glue driver proceeds with suspend.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Add compatible string to use this generic glue layer to support
Allwinner H6 platform's dwc3 controller.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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This is a requirement which has always existed but, somehow, wasn't
reflected in the documentation and problems weren't found until now
when Tuba Yavuz found a possible deadlock happening between dwc3 and
f_hid. She described the situation as follows:
spin_lock_irqsave(&hidg->write_spinlock, flags); // first acquire
/* we our function has been disabled by host */
if (!hidg->req) {
free_ep_req(hidg->in_ep, hidg->req);
goto try_again;
}
[...]
status = usb_ep_queue(hidg->in_ep, hidg->req, GFP_ATOMIC);
=>
[...]
=> usb_gadget_giveback_request
=>
f_hidg_req_complete
=>
spin_lock_irqsave(&hidg->write_spinlock, flags); // second acquire
Note that this happens because dwc3 would call ->complete() on a
failed usb_ep_queue() due to failed Start Transfer command. This is,
anyway, a theoretical situation because dwc3 currently uses "No
Response Update Transfer" command for Bulk and Interrupt endpoints.
It's still good to make this case impossible to happen even if the "No
Reponse Update Transfer" command is changed.
Reported-by: Tuba Yavuz <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing
Felipe writes:
usb: changes for v4.17 merge window
Quite a lot happened in this cycle, with a total of 95 non-merge
commits. The most interesting parts are listed below:
Synopsys has been adding better support for USB 3.1 to dwc3. The same
series also sets g_mass_storage's max speed to SSP.
Roger Quadros (TI) added support for dual-role using the OTG block
available in some dwc3 implementations, this makes sure that AM437x
can swap roles in runtime.
We have a new SoC supported in dwc3 now - Amlogic Meson GX - thanks to
the work of Martin Blumenstingl.
We also have a ton of changes in dwc2 (51% of all changes, in
fact). The most interesting part there is the support for
Hibernation (a Synopsys PM feature).
Apart from these, we have our regular set of non-critical fixes all
over the place.
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On TI's AM437x, the DWC3 controller looses state after a
system suspend/resume. We are re-initializing the controller
but we miss restoring the PRTCAP register. This causes
USB host to break on AM437x after a system suspend/resume.
Fix this by restoring the PRTCAP register on system resume.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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DWC_usb3 speed can only be set up to SuperSpeed. Limit the setting to
SuperSpeed only should the value be higher. Otherwise, the controller
will read an invalid speed value and set the device to an incorrect
speed.
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Dump LSP and BMU debug info.
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new fields to store these threshold configurations.
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register
fields for DWC_usb31 is as follows:
+-------+--------------------------+-----------------------------------+
| BITS | Name | Description |
+=======+==========================+===================================+
| 31:27 | reserved | |
| 26 | UsbTxPktCntSel | Async ESS transmit packet |
| | | threshold enable |
| 25:21 | UsbTxPktCnt | Async ESS transmit packet |
| | | threshold count |
| 20:16 | UsbMaxTxBurstSize | Async ESS Max transmit burst size |
| 15 | UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic |
| | | transmit packet threshold enable |
| 14:13 | UsbTxThrNumPkt_HS_Prd | HS high bandwidth periodic |
| | | transmit packet threshold count |
| 12:11 | reserved | |
| 10 | UsbTxThrNumPktSel_Prd | Periodic ESS transmit packet |
| | | threshold enable |
| 9:5 | UsbTxThrNumPkt_Prd | Periodic ESS transmit packet |
| | | threshold count |
| 4:0 | UsbMaxTxBurstSize_Prd | Max periodic ESS TX burst size |
+-------+--------------------------+-----------------------------------+
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register
fields for DWC_usb31 is as follows:
+-------+--------------------------+----------------------------------+
| BITS | Name | Description |
+=======+==========================+==================================+
| 31:27 | reserved | |
| 26 | UsbRxPktCntSel | Async ESS receive packet |
| | | threshold enable |
| 25:21 | UsbRxPktCnt | Async ESS receive packet |
| | | threshold count |
| 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size |
| 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic |
| | | receive packet threshold enable |
| 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic |
| | | receive packet threshold count |
| 12:11 | reserved | |
| 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet |
| | | threshold enable |
| 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet |
| | | threshold count |
| 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size |
+-------+--------------------------+----------------------------------+
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.
The GTXFIFOSIZ register for DWC_usb31 is as follows:
+-------+-----------+----------------------------------+
| BITS | Name | Description |
+=======+===========+==================================+
| 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address |
| 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO |
| 14:0 | TXFDEP | TXFIFO Depth |
+-------+-----------+----------------------------------+
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Platform device is allocated before adding resources. Make sure to
properly cleanup on error case.
Cc: <[email protected]>
Fixes: f1c7e7108109 ("usb: dwc3: convert to pcim_enable_device()")
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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If building a kernel without FTRACE but with TRACING, dwc3.ko fails to
link due to missing trace events. Fix this by using the correct
Kconfig symbol on Makefile.
Reported-by: Randy Dunlap <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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In
dwc3_request *r = NULL;
r = A;
the first assignment has no effect. Remove it.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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In the following test we get stuck by sleeping forever in _dwc3_set_mode()
after which dual-role switching doesn't work.
On dra7-evm's dual-role port,
- Load g_zero gadget driver and enumerate to host
- suspend to mem
- disconnect USB cable to host and connect otg cable with Pen drive in it.
- resume system
- we sleep indefinitely in _dwc3_set_mode due to.
dwc3_gadget_exit()->usb_del_gadget_udc()->udc_stop()->
dwc3_gadget_stop()->wait_event_lock_irq()
To fix this instead of waiting indefinitely with wait_event_lock_irq()
we use wait_event_interruptible_lock_irq_timeout() and print
and error message if there was a timeout.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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This is useful on platforms (e.g. TI AM437x) that don't
have ID available on a GPIO but do have the OTG block.
We can obtain the ID state via the OTG block and use it
for dual-role switching.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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We don't support PRTCAP == OTG yet, so prevent user from
setting it via debugfs.
Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly")
Cc: <[email protected]> # v4.12+
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Add OTG and GHWPARAMS6 register definitions
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB
controller. To use this controller a clock has to be enabled and a reset
line has to be pulsed.
Enabling the clock works identical to other SoCs. However, the reset
line has to be pulsed (using reset_control_reset) instead of using a
level reset (reset_control_{assert,deassert}).
Signed-off-by: Martin Blumenstingl <[email protected]>
Tested-by: Yixun Lan <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Some SoCs (such as Amlogic Meson GXL for example) share the reset line
with other components (in case of the Meson GXL example there's a shared
reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller).
Additionally SoC implementations may prefer a reset pulse over level
resets.
For now this falls back to the old defaults, which are:
- reset lines are exclusive
- level resets are being used
Signed-off-by: Martin Blumenstingl <[email protected]>
Tested-by: Yixun Lan <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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...instead of open coding file operations followed by custom ->open()
callbacks per each attribute.
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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To reproduce the lock up do the following
- connect otg host adapter and a USB device to the dual-role port
so that it is in host mode.
- suspend to mem.
- disconnect otg adapter.
- resume the system.
If we call dwc3_host_exit() before tasks are thawed
xhci_plat_remove() seems to lock up at the second usb_remove_hcd() call.
To work around this we queue the _dwc3_set_mode() work on
the system_freezable_wq.
Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly")
Cc: <[email protected]> # v4.12+
Suggested-by: Manu Gautam <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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suspend/resume
In order for ULPI PHYs to work, dwc3_phy_setup() and dwc3_ulpi_init()
must be doene before dwc3_core_get_phy().
commit 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys")
broke this.
The other issue is that dwc3_core_get_phy() and dwc3_ulpi_init() should
be called only once during the life cycle of the driver. However,
as dwc3_core_init() is called during system suspend/resume it will
result in multiple calls to dwc3_core_get_phy() and dwc3_ulpi_init()
which is wrong.
Fix this by moving dwc3_ulpi_init() out of dwc3_phy_setup()
into dwc3_core_ulpi_init(). Use a flag 'ulpi_ready' to ensure that
dwc3_core_ulpi_init() is called only once from dwc3_core_init().
Use another flag 'phys_ready' to call dwc3_core_get_phy() only once from
dwc3_core_init().
Fixes: 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys")
Fixes: f54edb539c11 ("usb: dwc3: core: initialize ULPI before trying to get the PHY")
Cc: linux-stable <[email protected]> # >= v4.13
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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The FIFO/Queue type values are incorrect. Correct them according to
DWC_usb3 programming guide section 1.2.27 (or DWC_usb31 section 1.2.25).
Additionally, this patch includes ProtocolStatusQ and AuxEventQ types.
Fixes: cf6d867d3b57 ("usb: dwc3: core: add fifo space helper")
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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The USB cable state can change during suspend/resume
so be sure to check and update the extcon state.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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Commit 689bf72c6e0d ("usb: dwc3: Don't reinitialize core during
host bus-suspend/resume") updated suspend/resume routines to not
power_off and reinit PHYs/core for host mode.
It broke platforms that rely on DWC3 core to power_off PHYs to
enter low power state on system suspend.
Perform dwc3_core_exit/init only during host mode system_suspend/
resume to addresses power regression from above mentioned patch
and also allow USB session to stay connected across
runtime_suspend/resume in host mode. While at it also replace
existing checks for HOST only dr_mode with current_dr_role to
have similar core driver behavior for both Host-only and DRD+Host
configurations.
Fixes: 689bf72c6e0d ("usb: dwc3: Don't reinitialize core during host bus-suspend/resume")
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Manu Gautam <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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In this function, we init the USB2 and USB3 PHYs, but if soft reset
times out, we don't unwind this.
Noticed by inspection.
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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DWC3 tracks TRB counter for each ep0 direction separately. In control
read transfer completion handler, the driver needs to reset the TRB
enqueue counter for ep0 IN direction. Currently the driver only resets
the TRB counter for control OUT endpoint. Check for the data direction
and properly reset the TRB counter from correct control endpoint.
Cc: [email protected]
Fixes: c2da2ff00606 ("usb: dwc3: ep0: don't use ep0in for transfers")
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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There are 2 control endpoint structures for DWC3. However, the driver
only updates the OUT direction control endpoint structure during
ConnectDone event. DWC3 driver needs to update the endpoint max packet
size for control IN endpoint as well. If the max packet size is not
properly set, then the driver will incorrectly calculate the data
transfer size and fail to send ZLP for HS/FS 3-stage control read
transfer.
The fix is simply to update the max packet size for the ep0 IN direction
during ConnectDone event.
Cc: [email protected]
Fixes: 72246da40f37 ("usb: Introduce DesignWare USB3 DRD Driver")
Signed-off-by: Thinh Nguyen <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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dwc3_of_simple_dev_pm_ops has never been used since commit a0d8c4cfdf31
("usb: dwc3: of-simple: set dev_pm_ops"), but this commit has brought
and oops when unbind the device due this sequence:
dwc3_of_simple_remove
-> clk_disable ...
-> pm_runtime_put_sync
-> dwc3_of_simple_runtime_suspend
-> clk_disable (again)
This double call to clk_core_disable causes a kernel oops like this:
WARNING: CPU: 1 PID: 4022 at drivers/clk/clk.c:656 clk_core_disable+0x78/0x80
CPU: 1 PID: 4022 Comm: bash Not tainted 4.15.0-rc4+ #44
Hardware name: Google Kevin (DT)
pstate: 80000085 (Nzcv daIf -PAN -UAO)
pc : clk_core_disable+0x78/0x80
lr : clk_core_disable_lock+0x20/0x38
sp : ffff00000bbf3a90
...
Call trace:
clk_core_disable+0x78/0x80
clk_disable+0x1c/0x30
dwc3_of_simple_runtime_suspend+0x30/0x50
pm_generic_runtime_suspend+0x28/0x40
This patch fixes the unbalanced clk disable call by setting the num_clocks
variable to zero once the clocks were disabled.
Fixes: a0d8c4cfdf31 ("usb: dwc3: of-simple: set dev_pm_ops")
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
phy: for 4.16
*) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3
*) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working
*) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled
to save power
*) Fix in Broadcom USB PHY to prevent abort in DRD mode
*) Fix in Broadcom USB PHY to use the correct dt properties
*) Fix in Mediatek PHY to detect device connection
*) Make getting resource optional for Mediatek V1 TPHY
*) Cleanup in Mediatek PHY
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes:
usb: changes for v4.16 merge window
Not many changes here, the most important being an improvement for TI's
AM57xx and DRA7xx devices which allows them to disable a metastability
workaround in situations where we know what's going on.
Other than that, we have a set of changes on Renesas UDC to make the
code a little easier to read and maintain while also better supporting
extcon framework.
The u_serial adaptation layer learned to use kfifo instead of cooking
its own FIFO implementation.
DWC3 learned to decode a few more USB requests on the trace output.
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Adding phy calibration sequence for USB 3.0 DRD PHY present on
Exynos5420/5800 systems.
This calibration facilitates setting certain PHY parameters viz.
the Loss-of-Signal (LOS) Detector Threshold Level, as well as
Tx-Vboost-Level for Super-Speed operations.
Additionally we also set proper time to wait for RxDetect measurement,
for desired PHY reference clock, so as to solve issue with enumeration
of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive
on the controller.
We are using CR_port for this purpose to send required data
to override the LOS values.
On testing with USB 3.0 devices on USB 3.0 port present on
SMDK5420, and peach-pit boards should see following message:
usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
and without this patch, should see below shown message:
usb 1-1: new high-speed USB device number 2 using xhci-hcd
[Also removed unnecessary extra lines in the register macro definitions]
Signed-off-by: Vivek Gautam <[email protected]>
[adapted to use phy_calibrate as entry point]
Signed-off-by: Andrzej Pietrasiewicz <[email protected]>
Acked-by: Felipe Balbi <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble
with the metastability workaround as it supports only
a High-Speed PHY and the PHY can enter into an Erratic state [1]
when the controller is set in SuperSpeed mode as part of
the metastability workaround.
This causes upto 2 seconds delay in enumeration on DRA7's USB2
instance in gadget mode.
If these platforms can be better off without the workaround,
provide a device tree property to suggest that so the workaround
is avoided.
[1] Device mode enumeration trace showing PHY Erratic Error.
irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0]
irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0]
irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0]
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
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