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path: root/drivers/usb/dwc3/core.h
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2018-03-22usb: dwc3: Dump LSP and BMU debug infoThinh Nguyen1-0/+5
Dump LSP and BMU debug info. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-22usb: dwc3: Check for ESS TX/RX threshold configThinh Nguyen1-0/+8
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure with new fields to store these threshold configurations. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-22usb: dwc3: Add DWC_usb31 GTXTHRCFG reg fieldsThinh Nguyen1-0/+10
Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+-----------------------------------+ | BITS | Name | Description | +=======+==========================+===================================+ | 31:27 | reserved | | | 26 | UsbTxPktCntSel | Async ESS transmit packet | | | | threshold enable | | 25:21 | UsbTxPktCnt | Async ESS transmit packet | | | | threshold count | | 20:16 | UsbMaxTxBurstSize | Async ESS Max transmit burst size | | 15 | UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold enable | | 14:13 | UsbTxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold count | | 12:11 | reserved | | | 10 | UsbTxThrNumPktSel_Prd | Periodic ESS transmit packet | | | | threshold enable | | 9:5 | UsbTxThrNumPkt_Prd | Periodic ESS transmit packet | | | | threshold count | | 4:0 | UsbMaxTxBurstSize_Prd | Max periodic ESS TX burst size | +-------+--------------------------+-----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-22usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fieldsThinh Nguyen1-0/+10
Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+----------------------------------+ | BITS | Name | Description | +=======+==========================+==================================+ | 31:27 | reserved | | | 26 | UsbRxPktCntSel | Async ESS receive packet | | | | threshold enable | | 25:21 | UsbRxPktCnt | Async ESS receive packet | | | | threshold count | | 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size | | 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold enable | | 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold count | | 12:11 | reserved | | | 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet | | | | threshold enable | | 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet | | | | threshold count | | 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size | +-------+--------------------------+----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-22usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fieldsThinh Nguyen1-0/+2
Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM. The GTXFIFOSIZ register for DWC_usb31 is as follows: +-------+-----------+----------------------------------+ | BITS | Name | Description | +=======+===========+==================================+ | 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address | | 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO | | 14:0 | TXFDEP | TXFIFO Depth | +-------+-----------+----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-13usb: dwc3: add dual role support using OTG blockRoger Quadros1-0/+29
This is useful on platforms (e.g. TI AM437x) that don't have ID available on a GPIO but do have the OTG block. We can obtain the ID state via the OTG block and use it for dual-role switching. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-13usb: dwc3: core.h: add some register definitionsRoger Quadros1-0/+82
Add OTG and GHWPARAMS6 register definitions Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15usb: dwc3: core: Fix ULPI PHYs and prevent phy_get/ulpi_init during ↵Roger Quadros1-0/+5
suspend/resume In order for ULPI PHYs to work, dwc3_phy_setup() and dwc3_ulpi_init() must be doene before dwc3_core_get_phy(). commit 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") broke this. The other issue is that dwc3_core_get_phy() and dwc3_ulpi_init() should be called only once during the life cycle of the driver. However, as dwc3_core_init() is called during system suspend/resume it will result in multiple calls to dwc3_core_get_phy() and dwc3_ulpi_init() which is wrong. Fix this by moving dwc3_ulpi_init() out of dwc3_phy_setup() into dwc3_core_ulpi_init(). Use a flag 'ulpi_ready' to ensure that dwc3_core_ulpi_init() is called only once from dwc3_core_init(). Use another flag 'phys_ready' to call dwc3_core_get_phy() only once from dwc3_core_init(). Fixes: 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") Fixes: f54edb539c11 ("usb: dwc3: core: initialize ULPI before trying to get the PHY") Cc: linux-stable <stable@vger.kernel.org> # >= v4.13 Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-12usb: dwc3: Fix GDBGFIFOSPACE_TYPE valuesThinh Nguyen1-7/+9
The FIFO/Queue type values are incorrect. Correct them according to DWC_usb3 programming guide section 1.2.27 (or DWC_usb31 section 1.2.25). Additionally, this patch includes ProtocolStatusQ and AuxEventQ types. Fixes: cf6d867d3b57 ("usb: dwc3: core: add fifo space helper") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-12-11usb: dwc3: Allow disabling of metastability workaroundRoger Quadros1-0/+3
Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble with the metastability workaround as it supports only a High-Speed PHY and the PHY can enter into an Erratic state [1] when the controller is set in SuperSpeed mode as part of the metastability workaround. This causes upto 2 seconds delay in enumeration on DRA7's USB2 instance in gadget mode. If these platforms can be better off without the workaround, provide a device tree property to suggest that so the workaround is avoided. [1] Device mode enumeration trace showing PHY Erratic Error. irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-12-11usb: dwc3: ep0: use gadget->isoch_delay for isoch_delay valueFelipe Balbi1-2/+0
Instead of keeping our own isoch_delay, let's make use of the newly introduced isoch_delay member in struct usb_gadget. The benefit here is that we would be using a generic "API" which other UDCs can use, resulting in a common setup for gadget drivers who may be interested in Isoch Delay value. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-11-07USB: dwc3: Remove redundant license textGreg Kroah-Hartman1-9/+0
Now that the SPDX tag is in all USB files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Patrice Chotard <patrice.chotard@st.com> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-04USB: add SPDX identifiers to all remaining files in drivers/usb/Greg Kroah-Hartman1-0/+1
It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/usb/ and include/linux/usb* files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Acked-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-19usb: dwc3: gadget: cache frame number in struct dwc3_epFelipe Balbi1-0/+2
This is in preparation to simplifying prototype of __dwc3_gadget_kick_transfer(). Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-06-02usb: dwc3: update documentationFelipe Balbi1-20/+24
No functional changes, just making sure we can use these for ReST docs later. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-05-17usb: dwc3: add disable u2mac linestate check quirkWilliam Wu1-0/+4
This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: Add dual-role supportRoger Quadros1-0/+14
If dr_mode is "otg" then support dual role mode of operation. Currently this mode is only supported when an extcon handle is present in the dwc3 device tree node. This is needed to get the ID status events of the port. We're using a workqueue to manage the dual-role state transitions as the extcon notifier (dwc3_drd_notifier) is called in an atomic context by extcon_sync() and this doesn't go well with usb_del_gadget_udc() causing a lockdep and softirq warning. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: core: make dwc3_set_mode() work properlyRoger Quadros1-1/+6
We can't have both Host and Peripheral roles active at the same time because of one detail on DWC3: it shares the same memory area for both Host and Peripheral registers. When swapping roles we must reinitialize the new role every time. Let's make sure this works for our debugfs interface. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: core: add current_dr_role memberRoger Quadros1-0/+2
We're going to use this member to track which role we're currently playing, that way we can more easily implement dual-role swap in upcoming patches. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: simplify ZLP handlingFelipe Balbi1-3/+1
It's much simpler to just add one extra TRB chained to previous TRB to handle ZLP. This helps us reduce pointless allocations and simplifies the code a little bit. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: ep0: improve handling of unaligned OUT requestsFelipe Balbi1-5/+1
Just like we did for all other endpoint types, let's rely on a chained TRB pointing to ep0_bounce_addr in order to align transfer size. This will make the code simpler. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: ep0: use immediate SETUP on TRBFelipe Balbi1-4/+0
If we pass TRB's own address on bpl/bph fields, we can get our SETUP packet as immediate data on the TRB itself, without having to allocate extra memory for it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: use BIT() macro where possibleRoger Quadros1-97/+98
To avoid checkpatch warnings with new patches let's start using the BIT() macro wherever possible. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: refactor gadget endpoint count calculationBryan O'Donoghue1-4/+2
- DWC_USB3_NUM indicates the number of Device mode single directional endpoints, including OUT and IN endpoint 0. - DWC_USB3_NUM_IN_EPS indicates the maximum number of Device mode IN endpoints active at any time, including control endpoint 0. It's possible to configure RTL such that DWC_USB3_NUM_EPS is equal to DWC_USB3_NUM_IN_EPS. dwc3-core calculates the number of OUT endpoints as DWC_USB3_NUM minus DWC_USB3_NUM_IN_EPS. If RTL has been configured with DWC_USB3_NUM_IN_EPS equal to DWC_USB3_NUM then dwc3-core will calculate the number of OUT endpoints as zero. For example a from dwc3_core_num_eps() shows: [ 1.565000] /usb0@f01d0000: found 8 IN and 0 OUT endpoints This patch refactors the endpoint calculation down to one variable dwc->num_eps taking care to maintain the current mapping of endpoints for fixed FPGA configurations as described in Table 4-7 of version 2.60a of the DWC USB3 databook. The endpoint mapping will then be EP-OUT, EP-IN etc, up to DWC_USB3_NUM. If DWC_USB3_NUM is odd then OUT will take the extra endpoint. Suggested-by: Felipe Balbi <balbi@kernel.org> Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-11usb: dwc3: make macros safe to expression argumentsRoger Quadros1-13/+13
We must make sure that our macros are safe against expressions passed as arguments. We have seen one problem where GTXFIFOSIZ(n) was failing when passed the expression (epnum >> 1) as argument. The problem was caused by operator precedence between >> and *. To make sure macros are safe, we just wrap argument with () when using it. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-03-27usb: dwc3: make sure UX_EXIT_PX is clearedFelipe Balbi1-0/+1
This bit is only supposed to be used with known buggy PHYs, however some platforms might erroneously set it. In order to avoid it, let's make sure this bit is always cleared. If some PHY needs this, we will need to add a quirk flag. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-01-24usb: dwc3: gadget: align transfers to wMaxPacketSizeFelipe Balbi1-0/+2
Instead of passing quirk_ep_out_aligned_size, we can use one extra TRB to align transfer to wMaxPacketSize. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-01-24usb: dwc3: gadget: allocate bounce buffer for unaligned xfersFelipe Balbi1-0/+3
Allocate a coherent buffer of 1024 bytes (size of a single superspeed bulk packet) to serve as bounce buffer for an extra TRB needed to align transfers to wMaxPacketSize. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-01-03usb: dwc3: gadget: Fix full speed modeRoger Quadros1-4/+2
DCFG.DEVSPD == 0x3 is not valid and we need to set DCFG.DEVSPD to 0x1 for full speed mode. Same goes for DSTS.CONNECTSPD. Old databooks had 0x3 for full speed in 48MHz mode for USB1.1 transceivers which was never supported. Newer databooks don't mention 0x3 at all. Cc: John Youn <John.Youn@synopsys.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-01-02usb: dwc3: core: avoid Overflow eventsFelipe Balbi1-3/+1
Now that we're handling so many transfers at a time and for some dwc3 revisions LPM events *must* be enabled, we can fall into a situation where too many events fire and we start receiving Overflow events. Let's do what XHCI does and allocate a full page for the Event Ring, this will avoid any future issues. Cc: <stable@vger.kernel.org> # v4.9 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc3: use bus->sysdev for DMA configurationArnd Bergmann1-0/+3
The dma ops for dwc3 devices are not set properly. So, use a physical device sysdev, which will be inherited from parent, to set the hardware / firmware parameters like dma. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Tested-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc3: Implement interrupt moderationJohn Youn1-0/+15
Implement interrupt moderation which allows the interrupt rate to be throttled. To enable this feature the dwc->imod_interval must be set to 1 or greater. This value specifies the minimum inter-interrupt interval, in 250 ns increments. A value of 0 disables interrupt moderation. This applies for DWC_usb3 version 3.00a and higher and for DWC_usb31 version 1.20a and higher. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc3: core: add a event buffer cacheJohn Youn1-0/+2
This extra buffer will be used so we can copy triggered events from our event buffer to this cache and process all of them later in bottom half handler. We need this in order to implement a workaround for a known erratum in recent DWC3 release. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc3: Add a check for the DWC_usb3 coreJohn Youn1-0/+6
Add a helper function to check if we are running on a DWC_usb3 core. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc3: gadget: Remove descriptor arguments to ep_enableJohn Youn1-1/+0
The __dwc3_gadget_endpoint_enable() function has access to the endpoint descriptors via the usb_ep. So we don't need to pass them in as arguments. The descriptors should be set by the caller prior to calling usb_ep_enable(). Signed-off-by: John Youn <johnyoun@synopsys.com> [felipe.balbi@linux.intel.com : minor improvements] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: gadget: tracking per-TRB remaining bytesFelipe Balbi1-0/+2
This will give us a simpler way of figuring out how many bytes were left in each TRB. It's useful for cases where we queue only part of an SG-list due to amount of available TRBs at the time of kicking the transfer. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: gadget: cope with XferNotReady before usb_ep_queue()Felipe Balbi1-0/+1
If XferNotReady comes before usb_ep_queue() we will set our PENDING request flag and wait for a request. However, originally, we were assuming usb_ep_queue() would always happen before our first XferNotReady and that causes a corner case where we could try to issue ENDTRANSFER command before STARTTRANSFER. Let's fix that by tracking endpoints which have been started. Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: gadget: wait for End Transfer to completeBaolin Wang1-0/+8
Instead of just delaying for 100us, we should actually wait for End Transfer Command Complete interrupt before moving on. Note that this should only be done if we're dealing with one of the core revisions that actually require the interrupt before moving on. [ felipe.balbi@linux.intel.com: minor improvements ] Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: gadget: don't clear RUN/STOP when it's invalid to do soBaolin Wang1-0/+3
When we change the USB function with configfs dynamically, we possibly met this situation: one core is doing the control transfer, another core is trying to unregister the USB gadget from userspace, we must wait for completing this control tranfer, or it will hang the controller to set the DEVCTRLHLT flag. [ felipe.balbi@linux.intel.com: several fixes to the patch - call complete() before starting following SETUP transfer - add a macro for ep0_in_setup's timeout - change commit subject slightly - break lines at 72 characters (git adds an 8-character tab) - avoid changes to dwc3_gadget_run_stop() ] Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: Add support for device L1 exitJohn Youn1-0/+4
For the usb31 IP and from version 2.90a of the usb3 IP, the core supports HW exit from L1 in HS. Enable it, otherwise the controller may never exit from LPM to do a transfer. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: remove unused struct member dwc3->memLu Baolu1-3/+0
Member @mem in struct dwc3 is not used in any places. Clean up it. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-03usb: dwc3: gadget: remove unused 'first_trb_index'Felipe Balbi1-2/+0
Recent changes have turned this field obsolete. Remove it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-10-31usb: dwc3: debug: decode control endpoint phase tooFelipe Balbi1-0/+1
DWC3 can tell us which phase of a setup transfer we're getting into. Let's decode it from the event to make it easier to debug. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-10-31usb: dwc3: gadget: properly check ep cmdFelipe Balbi1-0/+2
The cmd argument we pass to dwc3_send_gadget_ep_cmd() could contain extra arguments embedded. When checking for StartTransfer command, we need to make sure to match only lower 4 bits which contain the actual command and ignore the rest. Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-09-07usb: dwc3: Fix dr_mode validationThinh Nguyen1-1/+4
This patch follows the similar fix in dwc2. See commit 5268ed9d2e3b ("usb: dwc2: Fix dr_mode validation") Currently, the dr_mode is only checked against the module configuration. It also needs to be checked against the hardware capablities. The driver now checks if both the module configuration and hardware are capable of the dr_mode value. If not, then it will issue a warning and fall back to a supported value. If it is unable to fall back to a suitable value, then the probe will fail. Behavior summary: module : actual HW config dr_mode : dr_mode --------------------------------- host host any : host host dev any : INVALID host otg any : host dev host any : INVALID dev dev any : dev dev otg any : dev otg host any : host otg dev any : dev otg otg any : dr_mode Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-08-25usb: dwc3: Add ENDXFER command pollingJohn Youn1-0/+4
ENDXFER polling is available on version 3.10a and later of the DWC_usb3 (USB 3.0) controller. With this feature, the software can poll the CMDACT bit in the DEPCMD register after issuing an ENDXFER command. This feature is enabled by writing GUCTL2[14]. This feature is NOT available on the DWC_usb31 (USB 3.1) IP. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-08-25usb: dwc3: Add revision numbers for the USB 3.0 IPJohn Youn1-0/+2
Add revision number constants for the 3.00a and 3.10a releases. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-08-25usb: dwc3: add dis_del_phy_power_chg_quirkWilliam Wu1-0/+3
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-08-25usb: dwc3: make usb2 phy utmi interface configurableWilliam Wu1-0/+12
Support to configure the UTMI+ PHY with an 8- or 16-bit interface via DT. The UTMI+ PHY interface is a hardware capability, and it's platform dependent. Normally, the PHYIF can be configured during coreconsultant. But for some specific USB cores(e.g. rk3399 SoC DWC3), the default PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-08-25usb: dwc3: add dis_u2_freeclk_exists_quirkWilliam Wu1-0/+5
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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