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path: root/drivers/usb/dwc3/core.h
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2020-10-28usb: fix kernel-doc markupsMauro Carvalho Chehab1-1/+1
There is a common comment marked, instead, with kernel-doc notation. Also, some identifiers have different names between their prototypes and the kernel-doc markup. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Acked-by: Felipe Balbi <[email protected]> Link: https://lore.kernel.org/r/0b964be3884def04fcd20ea5c12cb90d0014871c.1603469755.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-02usb: dwc3: Add splitdisable quirk for Hisilicon Kirin SocYu Chen1-0/+7
SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core of Hisilicon Kirin Soc when dwc3 core act as host. [mchehab: dropped a dev_dbg() as only traces are now allowwed on this driver] Signed-off-by: Yu Chen <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: allocate gadget structure dynamicallyPeter Chen1-1/+1
The current code uses commit fac323471df6 ("usb: udc: allow adding and removing the same gadget device") as the workaround to let the gadget device is re-used, but it is not allowed from driver core point. In this commit, we allocate gadget structure dynamically, and free it at its release function. Since the gadget device's driver_data has already occupied by usb_composite_dev structure, we have to use gadget device's platform data to store dwc3 structure. Cc: Greg Kroah-Hartman <[email protected]> Cc: Alan Stern <[email protected]> Reviewed-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Peter Chen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: core: fix checkpatch warningsFelipe Balbi1-18/+19
no functional changes Signed-off-by: Felipe Balbi <[email protected]>
2020-09-24usb: dwc3: gadget: END_TRANSFER before CLEAR_STALL commandThinh Nguyen1-0/+1
According the programming guide (for all DWC3 IPs), when the driver handles ClearFeature(halt) request, it should issue CLEAR_STALL command _after_ the END_TRANSFER command completes. The END_TRANSFER command may take some time to complete. So, delay the ClearFeature(halt) request control status stage and wait for END_TRANSFER command completion interrupt. Only after END_TRANSFER command completes that the driver may issue CLEAR_STALL command. Cc: [email protected] Fixes: cb11ea56f37a ("usb: dwc3: gadget: Properly handle ClearFeature(halt)") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-07-15usb: dwc3: Replace HTTP links with HTTPS onesAlexander A. Klimov1-1/+1
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-05-25usb: dwc3: gadget: Use SET_EP_PRIME for NoStreamThinh Nguyen1-0/+3
DWC_usb32 v1.00a and later can use SET_EP_PRIME command to reinitiate a stream. Use the command to handle NoStream rejection instead of ending and restarting the endpoint. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-25usb: dwc3: gadget: Handle stream transfersThinh Nguyen1-0/+8
Overview of stream transfer requirement: * A transfer will have a set of TRBs of the same stream ID. * A transfer is started with a stream ID in START_TRANSFER command. * A new stream will only start when the previous completes. Overview of stream events: * A "prime" from host indicates that its endpoints are active (buffers prepared and ready to receive/transmit data). The controller automatically initiates stream if it sees this. * A "NoStream" rejection event indicates that the host isn't ready. Host will put the endpoint back to idle state. Device may need to reinitiate the stream to start transfer again. * A Stream Found event means host accepted device initiated stream. Nothing needs to be done from driver. To initiate a stream, the driver will issue START_TRANSFER command with a stream ID. To reinitiate the stream, the driver must issue END_TRANSFER and restart the transfer with START_TRANSFER command with the same stream ID. This implementation handles device-initated streams (e.g. UASP driver). It also handles some hosts' quirky behavior where they only prime each endpoint once. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-25usb: dwc3: gadget: Wait for transfer completionThinh Nguyen1-0/+1
If a transfer is in-progress, any new request should not kick off another transfer. The driver needs to wait for the current transfer to complete before starting off the next transfer. Introduce a new flag DWC3_EP_WAIT_TRANSFER_COMPLETE for this. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-25usb: dwc3: Get MDWIDTH for DWC_usb32Thinh Nguyen1-0/+3
DWC_usb32 supports MDWIDTH value larger than 255 and up to 1023. The field HWPARAMS6[9:8] stores the upper 2-bit values of the DWC_usb32's MDWIDTH. Check that parameter and properly get the MDWIDTH for DWC_usb32. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-25usb: dwc3: Add support for DWC_usb32 IPThinh Nguyen1-29/+37
Synopsys introduces a new controller DWC_usb32. It supports dual-lane and speed up to 20 Gbps, and the DWC3 driver will drive this controller. Currently the driver uses a single field dwc->revision to ID both DWC_usb3 and DWC_usb31 and their version number. This was sufficient for two IPs, but this method doesn't work with additional IPs. As a result, let's separate the dwc->revision field to 2 separate fields: ip and revision. The ip field now stores the ID of the controller's IP while the revision field stores the controller's version number. This new scheme enforces DWC3 to compare the revision within the same IP only. As a result, we must update all the revision check of the controller to check its corresponding IP. To help with this enforcement, we create a few macros to help with the common version checks: DWC3_IP_IS(IP) DWC3_VER_IS(IP, VERSION) DWC3_VER_IS_PRIOR(IP, VERSION) DWC3_VER_IS_WITHIN(IP, LOWER_VERSION, UPPER_VERSION) DWC3_VER_TYPE_IS_WITHIN(IP, VERSION, LOWER_VERSION_TYPE, UPPER_VERSION_TYPE) The DWC_usb32 controller operates using the same programming model and with very similar configurations as its previous controllers. Please note that the various IP and revision checks in this patch match the current checks for DWC_usb31 version 1.90a. Additional configurations that are unique to DWC_usb32 are applied separately. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-05USB: dwc3: Use the correct style for SPDX License IdentifierNishad Kamdar1-1/+1
This patch corrects the SPDX License Identifier style in header files related to DesignWare USB3 DRD Core Support. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <[email protected]> Signed-off-by: Nishad Kamdar <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-04-16usb: dwc3: gadget: Properly set maxpacket limitThinh Nguyen1-0/+4
Currently the calculation of max packet size limit for IN endpoints is too restrictive. This prevents a matching of a capable hardware endpoint during configuration. Below is the minimum recommended HW configuration to support a particular endpoint setup from the databook: For OUT endpoints, the databook recommended the minimum RxFIFO size to be at least 3x MaxPacketSize + 3x setup packets size (8 bytes each) + clock crossing margin (16 bytes). For IN endpoints, the databook recommended the minimum TxFIFO size to be at least 3x MaxPacketSize for endpoints that support burst. If the endpoint doesn't support burst or when the device is operating in USB 2.0 mode, a minimum TxFIFO size of 2x MaxPacketSize is recommended. Base on these recommendations, we can calculate the MaxPacketSize limit of each endpoint. This patch revises the IN endpoint MaxPacketSize limit and also sets the MaxPacketSize limit for OUT endpoints. Reference: Databook 3.30a section 3.2.2 and 3.2.3 Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-04-16usb: dwc3: Fix GTXFIFOSIZ.TXFDEP macro nameThinh Nguyen1-2/+2
Change the macro name DWC3_GTXFIFOSIZ_TXFDEF to DWC3_GTXFIFOSIZ_TXFDEP to match with the register name GTXFIFOSIZ.TXFDEP. Fixes: 457e84b6624b ("usb: dwc3: gadget: dynamically re-size TxFifos") Fixes: 0cab8d26d6e5 ("usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: Add support for role-switch-default-mode bindingJohn Stultz1-0/+3
Support the new role-switch-default-mode binding for configuring the default role the controller assumes as when the usb role is USB_ROLE_NONE This patch was split out from a larger patch originally by Yu Chen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> CC: ShuFan Lee <[email protected]> Cc: Heikki Krogerus <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Chunfeng Yun <[email protected]> Cc: Yu Chen <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Hans de Goede <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Jun Li <[email protected]> Cc: Valentin Schneider <[email protected]> Cc: Guillaume Gardet <[email protected]> Cc: Bryan O'Donoghue <[email protected]> Cc: Jack Pham <[email protected]> Cc: [email protected] Cc: [email protected] Tested-by: Bryan O'Donoghue <[email protected]> Signed-off-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: Registering a role switch in the DRD code.Yu Chen1-0/+3
The Type-C drivers use USB role switch API to inform the system about the negotiated data role, so registering a role switch in the DRD code in order to support platforms with USB Type-C connectors. Cc: Greg Kroah-Hartman <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> CC: ShuFan Lee <[email protected]> Cc: Heikki Krogerus <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Chunfeng Yun <[email protected]> Cc: Yu Chen <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Hans de Goede <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Jun Li <[email protected]> Cc: Valentin Schneider <[email protected]> Cc: Guillaume Gardet <[email protected]> Cc: Jack Pham <[email protected]> Cc: Bryan O'Donoghue <[email protected]> Cc: [email protected] Cc: [email protected] Suggested-by: Heikki Krogerus <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Yu Chen <[email protected]> Signed-off-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: core: add support for disabling SS instances in park modeNeil Armstrong1-0/+4
In certain circumstances, the XHCI SuperSpeed instance in park mode can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high load on the single XHCI SuperSpeed instance, the controller can crash like: xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. xhci-hcd xhci-hcd.0.auto: Host halt failed, -110 xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. hub 2-1.1:1.0: hub_ext_port_status failed (err = -22) xhci-hcd xhci-hcd.0.auto: HC died; cleaning up usb 2-1.1-port1: cannot reset (err = -22) Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates the issue. The bit is described as : "When this bit is set to '1' all SS bus instances in park mode are disabled" Synopsys explains: The GUCTL1.PARKMODE_DISABLE_SS is only available in dwc_usb3 controller running in host mode. This should not be set for other IPs. This can be disabled by default based on IP, but I recommend to have a property to enable this feature for devices that need this. CC: Dongjin Kim <[email protected]> Cc: Jianxin Pan <[email protected]> Cc: Thinh Nguyen <[email protected]> Cc: Jun Li <[email protected]> Reported-by: Tim <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-01-15usb: dwc3: gadget: Delay starting transferThinh Nguyen1-0/+1
If the END_TRANSFER command hasn't completed yet, then don't send the START_TRANSFER command. The controller may not be able to start if that's the case. Some controller revisions depend on this. See commit 76a638f8ac0d ("usb: dwc3: gadget: wait for End Transfer to complete"). Let's only send START_TRANSFER command after the END_TRANSFER command had completed. Fixes: 3aec99154db3 ("usb: dwc3: gadget: remove DWC3_EP_END_TRANSFER_PENDING") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-01-15usb: dwc3: gadget: Check END_TRANSFER completionThinh Nguyen1-0/+1
While the END_TRANSFER command is sent but not completed, any request dequeue during this time will cause the driver to issue the END_TRANSFER command. The driver needs to submit the command only once to stop the controller from processing further. The controller may take more time to process the same command multiple times unnecessarily. Let's add a flag DWC3_EP_END_TRANSFER_PENDING to check for this condition. Fixes: 3aec99154db3 ("usb: dwc3: gadget: remove DWC3_EP_END_TRANSFER_PENDING") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-08-09usb: dwc3: Update soft-reset wait polling rateThinh Nguyen1-0/+2
Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit will not be cleared until after all the internal clocks are synchronized during soft-reset. This may take a little more than 50ms. Set the polling rate at 20ms instead. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-06-20usb: dwc3: remove unused @lock member of dwc3_ep structChunfeng Yun1-2/+0
The member @lock of dwc3_ep struct is only initialized, and not used elsewhere, so remove it. Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-06-18usb: dwc3: gadget: Add support for disabling U1 and U2 entriesAnurag Kumar Vulisha1-0/+4
Gadget applications may have a requirement to disable the U1 and U2 entry based on the usecase. Below are few usecases where the disabling U1/U2 entries may be possible. Usecase 1: When combining dwc3 with an redriver for a USB Type-C device solution, it sometimes have problems with leaving U1/U2 for certain hosts, resulting in link training errors and reconnects. For this U1/U2 state entries may be avoided. Usecase 2: When performing performance benchmarking on mass storage gadget the U1 and U2 entries can be disabled. Usecase 3: When periodic transfers like ISOC transfers are used with bInterval of 1 which doesn't require the link to enter into U1 or U2 state entry (since ping is issued from host for every uframe interval). In this case the U1 and U2 entry can be disabled. Disablement of U1/U2 can be done by setting U1DevExitLat and U2DevExitLat values to 0 in the BOS descriptor. Host on seeing 0 value for U1DevExitLat and U2DevExitLat, it doesn't send SET_SEL requests to the gadget. There may be some hosts which may send SET_SEL requests even after seeing 0 in the UxDevExitLat of BOS descriptor. To aviod U1/U2 entries for these type of hosts, dwc3 controller can be programmed to reject those U1/U2 requests by not enabling ACCEPTUxENA bits in DCTL register. This patch updates the same. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Claus H. Stovgaard <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc3: Rename DWC3_DCTL_LPM_ERRATAThinh Nguyen1-2/+1
The macro name DWC3_DCTL_LPM_ERRATA is uninformative and does not do masking. Remove DWC3_DCTL_LPM_ERRATA_MASK and rename DWC3_DCTL_LPM_ERRATA to DWC3_DCTL_NYET_THRES with proper masking. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-02-04usb: dwc3: gadget: remove DWC3_EP_END_TRANSFER_PENDINGFelipe Balbi1-1/+0
Now that we modified the code to fix a race condition, it's clear that DWC3_EP_END_TRANSFER_PENDING is unnecessary, considering that DWC3_EP_TRANSFER_STARTED will remain set until End Transfer completes. Tested-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-01-28usb: dwc3: gadget: remove req->started flagFelipe Balbi1-2/+0
Now that we have req->status, we don't need this extra flag anymore. It's safe to remove it. Signed-off-by: Felipe Balbi <[email protected]>
2019-01-28usb: dwc3: gadget: add dwc3_request status trackingFelipe Balbi1-0/+9
This patch starts tracking dwc3_request status. A following patch will build on top of this to prevent a request from being queued twice. Signed-off-by: Felipe Balbi <[email protected]>
2018-12-05usb: dwc3: gadget: Report isoc transfer frame numberThinh Nguyen1-0/+1
Implement the new frame_number API to report the isochronous interval frame number. This patch checks and reports the interval in which the isoc transfer was transmitted or received via the Isoc-First TRB SOF number field. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-27usb: dwc3: gadget: check if dep->frame_number is still validFelipe Balbi1-0/+1
Gadget driver may take an unbounded amount of time to queue requests after XferNotReady. This is important for isochronous endpoints which need to be started for a specific (micro-)frame. If we fail to start a transfer for isochronous endpoint, let's try queueing to a future interval and see if that helps. We will stop trying if we fail a start transfer for 5 intervals in the future. Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: gadget: remove wait_end_transferFelipe Balbi1-3/+0
Now that we have a list of cancelled requests, we can skip over TRBs when END_TRANSFER command completes. Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: gadget: introduce cancelled_listFelipe Balbi1-0/+2
This list will host cancelled requests who still have TRBs being processed. Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: gadget: track number of TRBs per requestFelipe Balbi1-0/+3
This will help us remove the wait_event() from our ->dequeue(). Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: gadget: combine unaligned and zero flagsFelipe Balbi1-4/+3
Both flags are used for the same purpose in dwc3: appending an extra TRB at the end to deal with controller requirements. By combining both flags into one, we make it clear that the situation is the same and that they should be treated equally. Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Add workaround for isoc start transfer failureThinh Nguyen1-0/+13
In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the XferNotReady event are invalid. The driver uses this number to schedule the isochronous transfer and passes it to the START TRANSFER command. Because this number is invalid, the command may fail. If BIT[15:14] matches the internal 16-bit microframe, the START TRANSFER command will pass and the transfer will start at the scheduled time, if it is off by 1, the command will still pass, but the transfer will start 2 seconds in the future. For all other conditions, the START TRANSFER command will fail with bus-expiry. In order to workaround this issue, we can test for the correct combination of BIT[15:14] by sending START TRANSFER commands with different values of BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. As the result, within the 4 possible combinations for BIT[15:14], there will be 2 successful and 2 failure START COMMAND status. One of the 2 successful command status will result in a 2-second delay start. The smaller BIT[15:14] value is the correct combination. Since there are only 4 outcomes and the results are ordered, we can simply test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to deduce the smaller successful combination. Let test0 = test status for combination 'b00 and test1 = test status for 'b01 of BIT[15:14]. The correct combination is as follow: if test0 fails and test1 passes, BIT[15:14] is 'b01 if test0 fails and test1 fails, BIT[15:14] is 'b10 if test0 passes and test1 fails, BIT[15:14] is 'b11 if test0 passes and test1 passes, BIT[15:14] is 'b00 Synopsys STAR 9001202023: Wrong microframe number for isochronous IN endpoints. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Track DWC_usb31 VERSIONTYPEThinh Nguyen1-0/+10
Add a new field to dwc3 structure to track VERSIONTYPE. The VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register. In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE such as "ea01" and "ea02". Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Set default mode for DWC_usb3 v3.30a and higherThinh Nguyen1-0/+1
DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG mode. If the controller supports DRD but the dr_mode is not specified or set to OTG, then set the mode to peripheral. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Support option to disable USB2 LPMThinh Nguyen1-0/+2
Support the option to disable USB2 LPM. Set xhci "usb2-lpm-disable" property via "snps,usb2-lpm-disable" property. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: debugfs: Dump internal LSP and ep registersThinh Nguyen1-0/+13
To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: debugfs: Properly name Tx/RxFIFOThinh Nguyen1-2/+2
The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc3: core: Enable AutoRetry feature in the controllerAnurag Kumar Vulisha1-0/+3
By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc3: Enable undefined length INCR burst typePengbo Mu1-0/+3
Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Changming Huang <[email protected]> Signed-off-by: Ran Wang <[email protected]> Signed-off-by: Pengbo Mu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc3: add global soc bus configuration reg0Pengbo Mu1-0/+11
Add the macro definition for global soc bus configuration register 0 Signed-off-by: Changming Huang <[email protected]> Signed-off-by: Ran Wang <[email protected]> Signed-off-by: Pengbo Mu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: remove duplicated missed isoc handlingFelipe Balbi1-1/+0
Now, this part of the code is duplicated and brings no extra value to the driver. Let's remove it. Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: check for Missed Isoc from event statusFelipe Balbi1-2/+3
In case we get an event with status set to Missed Isoc, this means we have missed an isochronous interval and should issue End Transfer command and wait for the following XferNotReady. Let's do that early, rather than late. Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: remove DWC3_EP_BUSY flagFelipe Balbi1-2/+1
It has no use anymore. Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: remove allocated/queued request trackingFelipe Balbi1-4/+0
That has never proven useful in any way. Just remove it. Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: Correct the logic for queuing sgsAnurag Kumar Vulisha1-0/+2
The present code correctly fetches the req which were previously not queued from the started_list but fails to continue queuing from the sg where it previously stopped queuing (because of the unavailable TRB's). This patch correct's the code to continue queuing from the correct sg present in the sglist. For example, consider 5 sgs in req. Because of limited TRB's among the 5 sgs only 3 got queued. This patch corrects the code to start queuing from correct sg i.e 4th sg when the TRBs are available. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc3: gadget: Correct handling of scattergather listsAnurag Kumar Vulisha1-0/+2
The code logic in dwc3_prepare_one_trb() incorrectly uses the address and length fields present in req packet for mapping TRB's instead of using the address and length fields of scattergather lists. This patch correct's the code to use sg->address and sg->length when scattergather lists are present. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-16usb: dwc3: support clocks and resets for DWC3 coreMasahiro Yamada1-0/+8
Historically, the clocks and resets are handled on the glue layer side instead of the DWC3 core. For simple cases, dwc3-of-simple.c takes care of arbitrary number of clocks and resets. The DT node structure typically looks like as follows: dwc3-glue { compatible = "foo,dwc3"; clocks = ...; resets = ...; ... dwc3 { compatible = "snps,dwc3"; ... }; } By supporting the clocks and the reset in the dwc3/core.c, it will be turned into a single node: dwc3 { compatible = "foo,dwc3", "snps,dwc3"; clocks = ...; resets = ...; ... } This commit adds the binding of clocks and resets specific to this IP. The number of clocks should generally be the same across SoCs, it is just some SoCs either tie clocks together or do not provide software control of some of the clocks. I took the clock names from the Synopsys datasheet: "ref" (ref_clk), "bus_early" (bus_clk_early), and "suspend" (suspend_clk). I found only one reset line in the datasheet, hence the reset-names property is omitted. Those clocks are required for new platforms. Enforcing the new binding breaks existing platforms since they specify clocks (and resets) in their glue layer node, but nothing in the core node. I listed such exceptional cases in the DT binding. The driver code has been relaxed to accept no clock. This change is based on the discussion [1]. I inserted reset_control_deassert() and clk_bulk_enable() before the first register access, i.e. dwc3_cache_hwparams(). [1] https://patchwork.kernel.org/patch/10284265/ Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-22usb: dwc3: Dump LSP and BMU debug infoThinh Nguyen1-0/+5
Dump LSP and BMU debug info. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-22usb: dwc3: Check for ESS TX/RX threshold configThinh Nguyen1-0/+8
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure with new fields to store these threshold configurations. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>