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path: root/drivers/usb/dwc3/core.c
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2018-07-30usb: dwc3: Enable undefined length INCR burst typePengbo Mu1-0/+94
Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Changming Huang <[email protected]> Signed-off-by: Ran Wang <[email protected]> Signed-off-by: Pengbo Mu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-06-18usb: dwc3: Only call clk_bulk_get() on devicetree instantiated devicesHans de Goede1-10/+13
Commit fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core") adds support for handling clocks and resets in the DWC3 core, so that for platforms following the standard devicetree bindings this does not need to be duplicated in all the different glue layers. These changes intended for devicetree based platforms introduce an uncoditional clk_bulk_get() in the core probe path. This leads to the following error being logged on x86/ACPI systems: [ 26.276783] dwc3 dwc3.3.auto: Failed to get clk 'ref': -2 This commits wraps the clk_bulk_get() in an if (dev->of_node) check so that it only is done on devicetree instantiated devices, fixing this error. Cc: Masahiro Yamada <[email protected]> Reviewed-by: Masahiro Yamada <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-16usb: dwc3: support clocks and resets for DWC3 coreMasahiro Yamada1-2/+86
Historically, the clocks and resets are handled on the glue layer side instead of the DWC3 core. For simple cases, dwc3-of-simple.c takes care of arbitrary number of clocks and resets. The DT node structure typically looks like as follows: dwc3-glue { compatible = "foo,dwc3"; clocks = ...; resets = ...; ... dwc3 { compatible = "snps,dwc3"; ... }; } By supporting the clocks and the reset in the dwc3/core.c, it will be turned into a single node: dwc3 { compatible = "foo,dwc3", "snps,dwc3"; clocks = ...; resets = ...; ... } This commit adds the binding of clocks and resets specific to this IP. The number of clocks should generally be the same across SoCs, it is just some SoCs either tie clocks together or do not provide software control of some of the clocks. I took the clock names from the Synopsys datasheet: "ref" (ref_clk), "bus_early" (bus_clk_early), and "suspend" (suspend_clk). I found only one reset line in the datasheet, hence the reset-names property is omitted. Those clocks are required for new platforms. Enforcing the new binding breaks existing platforms since they specify clocks (and resets) in their glue layer node, but nothing in the core node. I listed such exceptional cases in the DT binding. The driver code has been relaxed to accept no clock. This change is based on the discussion [1]. I inserted reset_control_deassert() and clk_bulk_enable() before the first register access, i.e. dwc3_cache_hwparams(). [1] https://patchwork.kernel.org/patch/10284265/ Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-15usb: dwc3: use local copy of resource to fix-up register offsetMasahiro Yamada1-24/+8
It is not a good idea to directly modify the resource of a platform device. Modify its local copy, and pass it to devm_ioremap_resource() so that we do not need to restore it in the failure path and the remove hook. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Masami Hiramatsu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-15usb: dwc3: core: Suspend PHYs on runtime suspend in host modeManu Gautam1-3/+33
Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support runtime PM to reduce PHY power consumption during bus_suspend. Add changes to let core auto-suspend PHYs on host bus-suspend using GUSB2PHYCFG register if needed for a platform. Also perform PHYs runtime suspend/resume and let platform glue drivers e.g. dwc3-qcom handle remote wakeup during bus suspend by waking up devices on receiving wakeup event from PHY. Signed-off-by: Manu Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-23Merge tag 'usb-for-v4.17' of ↵Greg Kroah-Hartman1-8/+126
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing Felipe writes: usb: changes for v4.17 merge window Quite a lot happened in this cycle, with a total of 95 non-merge commits. The most interesting parts are listed below: Synopsys has been adding better support for USB 3.1 to dwc3. The same series also sets g_mass_storage's max speed to SSP. Roger Quadros (TI) added support for dual-role using the OTG block available in some dwc3 implementations, this makes sure that AM437x can swap roles in runtime. We have a new SoC supported in dwc3 now - Amlogic Meson GX - thanks to the work of Martin Blumenstingl. We also have a ton of changes in dwc2 (51% of all changes, in fact). The most interesting part there is the support for Hibernation (a Synopsys PM feature). Apart from these, we have our regular set of non-critical fixes all over the place.
2018-03-22usb: dwc3: core: Fix broken system suspend/resume on AM437xRoger Quadros1-0/+2
On TI's AM437x, the DWC3 controller looses state after a system suspend/resume. We are re-initializing the controller but we miss restoring the PRTCAP register. This causes USB host to break on AM437x after a system suspend/resume. Fix this by restoring the PRTCAP register on system resume. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-22usb: dwc3: Check for ESS TX/RX threshold configThinh Nguyen1-0/+55
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure with new fields to store these threshold configurations. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-22usb: dwc3: Add SoftReset PHY synchonization delayThinh Nguyen1-1/+12
From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST bit is cleared, we must wait at least 50ms before accessing the PHY domain (synchronization delay). Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-13usb: dwc3: add dual role support using OTG blockRoger Quadros1-10/+57
This is useful on platforms (e.g. TI AM437x) that don't have ID available on a GPIO but do have the OTG block. We can obtain the ID state via the OTG block and use it for dual-role switching. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-03-13usb: dwc3: prevent setting PRTCAP to OTG from debugfsRoger Quadros1-0/+3
We don't support PRTCAP == OTG yet, so prevent user from setting it via debugfs. Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly") Cc: <[email protected]> # v4.12+ Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-02-28usb: dwc3: Fix lock-up on ID change during system suspend/resumeRoger Quadros1-1/+1
To reproduce the lock up do the following - connect otg host adapter and a USB device to the dual-role port so that it is in host mode. - suspend to mem. - disconnect otg adapter. - resume the system. If we call dwc3_host_exit() before tasks are thawed xhci_plat_remove() seems to lock up at the second usb_remove_hcd() call. To work around this we queue the _dwc3_set_mode() work on the system_freezable_wq. Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly") Cc: <[email protected]> # v4.12+ Suggested-by: Manu Gautam <[email protected]> Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-02-15usb: dwc3: core: Fix ULPI PHYs and prevent phy_get/ulpi_init during ↵Roger Quadros1-11/+36
suspend/resume In order for ULPI PHYs to work, dwc3_phy_setup() and dwc3_ulpi_init() must be doene before dwc3_core_get_phy(). commit 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") broke this. The other issue is that dwc3_core_get_phy() and dwc3_ulpi_init() should be called only once during the life cycle of the driver. However, as dwc3_core_init() is called during system suspend/resume it will result in multiple calls to dwc3_core_get_phy() and dwc3_ulpi_init() which is wrong. Fix this by moving dwc3_ulpi_init() out of dwc3_phy_setup() into dwc3_core_ulpi_init(). Use a flag 'ulpi_ready' to ensure that dwc3_core_ulpi_init() is called only once from dwc3_core_init(). Use another flag 'phys_ready' to call dwc3_core_get_phy() only once from dwc3_core_init(). Fixes: 541768b08a40 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") Fixes: f54edb539c11 ("usb: dwc3: core: initialize ULPI before trying to get the PHY") Cc: linux-stable <[email protected]> # >= v4.13 Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-02-12usb: dwc3: core: Power-off core/PHYs on system_suspend in host modeManu Gautam1-14/+22
Commit 689bf72c6e0d ("usb: dwc3: Don't reinitialize core during host bus-suspend/resume") updated suspend/resume routines to not power_off and reinit PHYs/core for host mode. It broke platforms that rely on DWC3 core to power_off PHYs to enter low power state on system suspend. Perform dwc3_core_exit/init only during host mode system_suspend/ resume to addresses power regression from above mentioned patch and also allow USB session to stay connected across runtime_suspend/resume in host mode. While at it also replace existing checks for HOST only dr_mode with current_dr_role to have similar core driver behavior for both Host-only and DRD+Host configurations. Fixes: 689bf72c6e0d ("usb: dwc3: Don't reinitialize core during host bus-suspend/resume") Reviewed-by: Roger Quadros <[email protected]> Signed-off-by: Manu Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-02-12usb: dwc3: Undo PHY init if soft reset failsBrian Norris1-0/+3
In this function, we init the USB2 and USB3 PHYs, but if soft reset times out, we don't unwind this. Noticed by inspection. Signed-off-by: Brian Norris <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-01-08Merge tag 'phy-for-4.16' of ↵Greg Kroah-Hartman1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.16 *) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3 *) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working *) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled to save power *) Fix in Broadcom USB PHY to prevent abort in DRD mode *) Fix in Broadcom USB PHY to use the correct dt properties *) Fix in Mediatek PHY to detect device connection *) Make getting resource optional for Mediatek V1 TPHY *) Cleanup in Mediatek PHY Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2017-12-29phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800Vivek Gautam1-0/+2
Adding phy calibration sequence for USB 3.0 DRD PHY present on Exynos5420/5800 systems. This calibration facilitates setting certain PHY parameters viz. the Loss-of-Signal (LOS) Detector Threshold Level, as well as Tx-Vboost-Level for Super-Speed operations. Additionally we also set proper time to wait for RxDetect measurement, for desired PHY reference clock, so as to solve issue with enumeration of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive on the controller. We are using CR_port for this purpose to send required data to override the LOS values. On testing with USB 3.0 devices on USB 3.0 port present on SMDK5420, and peach-pit boards should see following message: usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd and without this patch, should see below shown message: usb 1-1: new high-speed USB device number 2 using xhci-hcd [Also removed unnecessary extra lines in the register macro definitions] Signed-off-by: Vivek Gautam <[email protected]> [adapted to use phy_calibrate as entry point] Signed-off-by: Andrzej Pietrasiewicz <[email protected]> Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2017-12-11usb: dwc3: Allow disabling of metastability workaroundRoger Quadros1-0/+3
Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble with the metastability workaround as it supports only a High-Speed PHY and the PHY can enter into an Erratic state [1] when the controller is set in SuperSpeed mode as part of the metastability workaround. This causes upto 2 seconds delay in enumeration on DRA7's USB2 instance in gadget mode. If these platforms can be better off without the workaround, provide a device tree property to suggest that so the workaround is avoided. [1] Device mode enumeration trace showing PHY Erratic Error. irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-11-07USB: dwc3: Remove redundant license textGreg Kroah-Hartman1-12/+0
Now that the SPDX tag is in all USB files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Kukjin Kim <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: Patrice Chotard <[email protected]> Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-11-04USB: add SPDX identifiers to all remaining files in drivers/usb/Greg Kroah-Hartman1-0/+1
It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/usb/ and include/linux/usb* files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Thomas Gleixner <[email protected]> Cc: Kate Stewart <[email protected]> Cc: Philippe Ombredanne <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> Acked-by: Felipe Balbi <[email protected]> Acked-by: Johan Hovold <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-10-24usb: dwc3: core: Notify current USB mode to USB3 PHY as wellManu Gautam1-9/+8
Driver currently notifies only USB2 PHY on USB mode change. Extend this to USB3 PHY so that PHY drivers based on the mode can release system resources - clocks, regulators etc. Additionally Qualcomm QMP and QUSB2 PHY drivers need to override VBUS signal in PHY wrapper in device mode as USB VBUS line is not connected to PHYs. Also, remove NULL checks for PHY when calling phy_set_mode as PHY ops already check this. Signed-off-by: Manu Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-10-24usb: dwc3: pci: Runtime resume child device from wqManu Gautam1-1/+0
Driver currently resumes and increments pm usage_count of its child device (dwc3 main) from its runtime_resume handler. This requires dwc3 runtime_resume to perform pm_runtime_put to decrement the pm usage_count. However runtime_put from dwc3 happens for non pci drivers (e.g. dwc3-if-simple.c) as well which results in dwc3 pm usage_count becoming negative after couple of runtime suspend resume iterations. Fix this by performing runtime_get/put from dwc3-pci driver only using workqueue. Signed-off-by: Manu Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-10-24usb: dwc3: Don't reinitialize core during host bus-suspend/resumeManu Gautam1-23/+20
Driver powers-off PHYs and reinitializes DWC3 core and gadget on resume. While this works fine for gadget mode but in host mode there is not re-initialization of host stack. Also, resetting bus as part of bus_suspend/resume is not correct which could affect (or disconnect) connected devices. Fix this by not reinitializing core on suspend/resume in host mode for HOST only and OTG/drd configurations. Signed-off-by: Manu Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-07-17usb: dwc3: core: Call dwc3_core_get_phy() before initializing physVignesh R1-3/+3
commit f54edb539c116 ("usb: dwc3: core: initialize ULPI before trying to get the PHY") moved call to dwc3_core_get_phy() from dwc3_probe() to dwc3_core_init() after dwc3_core_soft_reset(). But dwc3_core_soft_reset() calls phy_init(), therefore dwc3_core_get_phy() needs to be called before dwc3_core_soft_reset(). Fix this by moving call to dwc3_core_get_phy() before dwc3_core_soft_reset(). This fixes the following abort seen on DRA7xx platforms [ 24.769118] usb usb2: SerialNumber: xhci-hcd.1.auto [ 24.781144] hub 2-0:1.0: USB hub found [ 24.787836] hub 2-0:1.0: 1 port detected [ 24.809939] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 Reported-by: Carlos Hernandez <[email protected]> Signed-off-by: Vignesh R <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-06-13usb: dwc3: core: program PHY for proper DRD modesFelipe Balbi1-1/+26
If PHY is entering Host mode, we need to enable VBUS. Signed-off-by: Felipe Balbi <[email protected]>
2017-06-13usb: dwc3: core: initialize ULPI before trying to get the PHYFelipe Balbi1-4/+6
If don't reorder initialization like this, we will never be able to get a reference to ULPI PHYs. Signed-off-by: Felipe Balbi <[email protected]>
2017-05-17usb: dwc3: add disable u2mac linestate check quirkWilliam Wu1-6/+14
This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Acked-by: Rob Herring <[email protected]> Reviewed-by: Guenter Roeck <[email protected]> Signed-off-by: William Wu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-04-11usb: dwc3: Add dual-role supportRoger Quadros1-4/+7
If dr_mode is "otg" then support dual role mode of operation. Currently this mode is only supported when an extcon handle is present in the dwc3 device tree node. This is needed to get the ID status events of the port. We're using a workqueue to manage the dual-role state transitions as the extcon notifier (dwc3_drd_notifier) is called in an atomic context by extcon_sync() and this doesn't go well with usb_del_gadget_udc() causing a lockdep and softirq warning. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-04-11usb: dwc3: core: make dwc3_set_mode() work properlyRoger Quadros1-31/+72
We can't have both Host and Peripheral roles active at the same time because of one detail on DWC3: it shares the same memory area for both Host and Peripheral registers. When swapping roles we must reinitialize the new role every time. Let's make sure this works for our debugfs interface. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-04-11usb: dwc3: core: add current_dr_role memberRoger Quadros1-0/+2
We're going to use this member to track which role we're currently playing, that way we can more easily implement dual-role swap in upcoming patches. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-04-11usb: dwc3: refactor gadget endpoint count calculationBryan O'Donoghue1-2/+1
- DWC_USB3_NUM indicates the number of Device mode single directional endpoints, including OUT and IN endpoint 0. - DWC_USB3_NUM_IN_EPS indicates the maximum number of Device mode IN endpoints active at any time, including control endpoint 0. It's possible to configure RTL such that DWC_USB3_NUM_EPS is equal to DWC_USB3_NUM_IN_EPS. dwc3-core calculates the number of OUT endpoints as DWC_USB3_NUM minus DWC_USB3_NUM_IN_EPS. If RTL has been configured with DWC_USB3_NUM_IN_EPS equal to DWC_USB3_NUM then dwc3-core will calculate the number of OUT endpoints as zero. For example a from dwc3_core_num_eps() shows: [ 1.565000] /usb0@f01d0000: found 8 IN and 0 OUT endpoints This patch refactors the endpoint calculation down to one variable dwc->num_eps taking care to maintain the current mapping of endpoints for fixed FPGA configurations as described in Table 4-7 of version 2.60a of the DWC USB3 databook. The endpoint mapping will then be EP-OUT, EP-IN etc, up to DWC_USB3_NUM. If DWC_USB3_NUM is odd then OUT will take the extra endpoint. Suggested-by: Felipe Balbi <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2017-03-27usb: dwc3: make sure UX_EXIT_PX is clearedFelipe Balbi1-0/+6
This bit is only supposed to be used with known buggy PHYs, however some platforms might erroneously set it. In order to avoid it, let's make sure this bit is always cleared. If some PHY needs this, we will need to add a quirk flag. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18Merge tag 'usb-for-v4.10' of ↵Greg Kroah-Hartman1-168/+190
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: patches for v4.10 merge window One big merge this time with a total of 166 non-merge commits. Most of the work, by far, is on dwc2 this time (68.2%) with dwc3 a far second (22.5%). The remaining 9.3% are scattered on gadget drivers. The most important changes for dwc2 are the peripheral side DMA support implemented by Synopsys folks and support for the new IOT dwc2 compatible core from Synopsys. In dwc3 land we have support for high-bandwidth, high-speed isochronous endpoints and some non-critical fixes for large scatter lists. Apart from these, we have our usual set of cleanups, non-critical fixes, etc.
2016-11-18usb: dwc3: use bus->sysdev for DMA configurationArnd Bergmann1-13/+14
The dma ops for dwc3 devices are not set properly. So, use a physical device sysdev, which will be inherited from parent, to set the hardware / firmware parameters like dma. Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Sriram Dash <[email protected]> Tested-by: Baolin Wang <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18usb: dwc3: Workaround for irq mask issueJohn Youn1-0/+11
This is a workaround for STAR 9000961433 which affects only version 3.00a of the DWC_usb3 core. This prevents the controller interrupt from being masked while handling events. Enabling interrupt moderation allows us to work around this issue because once the GEVNTCOUNT.count is written the IRQ is immediately deasserted and won't be asserted again until GEVNTCOUNT.EHB is cleared. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18usb: dwc3: Implement interrupt moderationJohn Youn1-0/+16
Implement interrupt moderation which allows the interrupt rate to be throttled. To enable this feature the dwc->imod_interval must be set to 1 or greater. This value specifies the minimum inter-interrupt interval, in 250 ns increments. A value of 0 disables interrupt moderation. This applies for DWC_usb3 version 3.00a and higher and for DWC_usb31 version 1.20a and higher. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18usb: dwc3: core: add a event buffer cacheJohn Youn1-0/+4
This extra buffer will be used so we can copy triggered events from our event buffer to this cache and process all of them later in bottom half handler. We need this in order to implement a workaround for a known erratum in recent DWC3 release. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18usb: dwc3: core: remove dwc3_soft_reset()Felipe Balbi1-39/+0
dwc3_soft_reset() is doing the same thing as dwc3_core_soft_reset(). Let's remove dwc3_soft_reset() since that's not needed anymore. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-18usb: dwc3: Add a function to check propertiesJohn Youn1-26/+33
Add a function to check properties and call it from probe. This will allow us to add check code without bloating the probe function. This needs to be done after dwc3_get_properties() and dwc3_core_init() so that all the properties and hardware configs are available. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-08usb: dwc3: trace: purge dwc3_trace()Felipe Balbi1-12/+3
Finally get rid of dwc3_trace() hack. If any other message is truly needed, we should add proper tracepoints for them instead of hacking around with dwc3_trace() or similar. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: core: add dwc3_get_properties()Felipe Balbi1-41/+49
This helper will be responsible for reading and parsing our properties. No functional changes in this patch, cleanup only. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: core: remove unnecessary alignmentFelipe Balbi1-6/+2
Kernel will give us page aligned memory anyway. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: core: introduce dwc3_core_setup_global_control()Felipe Balbi1-42/+48
This little helper will be used to setup anything related to GCTL register. There are no functional changes, this is a cleanup only patch. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: core: introduce dwc3_core_is_valid()Felipe Balbi1-10/+22
This little helper will be used to make sure we're dealing with a valid Synopsys DWC3 or DWC3.1 core. Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: Add support for device L1 exitJohn Youn1-0/+10
For the usb31 IP and from version 2.90a of the usb3 IP, the core supports HW exit from L1 in HS. Enable it, otherwise the controller may never exit from LPM to do a transfer. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-11-03usb: dwc3: remove unused struct member dwc3->memLu Baolu1-1/+0
Member @mem in struct dwc3 is not used in any places. Clean up it. Signed-off-by: Lu Baolu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-10-31usb: dwc3: Fix error handling for core initVivek Gautam1-3/+2
Fixing the sequence of events in dwc3_core_init() error exit path. dwc3_core_exit() call is also removed from the error path since, whatever it's doing is already done. Fixes: c499ff7 usb: dwc3: core: re-factor init and exit paths Cc: Felipe Balbi <[email protected]> Cc: Greg KH <[email protected]> Cc: Stable <[email protected]> # 4.8+ Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-09-14Merge tag 'usb-for-v4.9' of ↵Greg Kroah-Hartman1-14/+108
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: patches for v4.9 merge window This time around we have 92 non-merge commits. Most of the changes are in drivers/usb/gadget (40.3%) with drivers/usb/gadget/function being the most active directory (27.2%). As for UDC drivers, only dwc3 (26.5%) and dwc2 (12.7%) have really been active. The most important changes for dwc3 are better support for scatterlist and, again, throughput improvements. While on dwc2 got some minor stability fixes related to soft reset and FIFO usage. Felipe Tonello has done some good work fixing up our f_midi gadget and Tal Shorer has implemented a nice API change for our ULPI bus. Apart from these, we have our usual set of non-critical fixes, spelling fixes, build warning fixes, etc.
2016-09-07usb: dwc3: Fix dr_mode validationThinh Nguyen1-11/+54
This patch follows the similar fix in dwc2. See commit 5268ed9d2e3b ("usb: dwc2: Fix dr_mode validation") Currently, the dr_mode is only checked against the module configuration. It also needs to be checked against the hardware capablities. The driver now checks if both the module configuration and hardware are capable of the dr_mode value. If not, then it will issue a warning and fall back to a supported value. If it is unable to fall back to a suitable value, then the probe will fail. Behavior summary: module : actual HW config dr_mode : dr_mode --------------------------------- host host any : host host dev any : INVALID host otg any : host dev host any : INVALID dev dev any : dev dev otg any : dev otg host any : host otg dev any : dev otg otg any : dr_mode Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2016-08-25usb: dwc3: Add ENDXFER command pollingJohn Youn1-0/+11
ENDXFER polling is available on version 3.10a and later of the DWC_usb3 (USB 3.0) controller. With this feature, the software can poll the CMDACT bit in the DEPCMD register after issuing an ENDXFER command. This feature is enabled by writing GUCTL2[14]. This feature is NOT available on the DWC_usb31 (USB 3.1) IP. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
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