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path: root/drivers/usb/dwc3/core.c
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2021-03-23usb: dwc3: gadget: Remove invalid low-speed settingThinh Nguyen1-1/+0
None of the DWC_usb3x IPs (and all their versions) supports low-speed setting in device mode. In the early days, our "Early Adopter Edition" DWC_usb3 databook shows that the controller may be configured to operate in low-speed, but it was revised on release. Let's remove this invalid speed setting to avoid any confusion. Signed-off-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/258b1c7fbb966454f4c4c2c1367508998498fc30.1615509438.git.Thinh.Nguyen@synopsys.com Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-03-10usb: dwc3: Fix dereferencing of null dwc->usb_psyColin Ian King1-2/+2
Currently the null check logic on dwc->usb_psy is inverted as it allows calls to power_supply_put with a null dwc->usb_psy causing a null pointer dereference. Fix this by removing the ! operator. Addresses-Coverity: ("Dereference after null check") Fixes: 59fa3def35de ("usb: dwc3: add a power supply for current control") Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-03-10usb: dwc3: add a power supply for current controlRay Chi1-0/+15
Currently, VBUS draw callback does no action when the generic PHYs are used. This patch adds an additional path to control charging current through power supply interface. Signed-off-by: Ray Chi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-08Merge 5.11-rc7 into usb-nextGreg Kroah-Hartman1-1/+1
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-06usb: dwc3: core: Check maximum_speed SSP genXxYThinh Nguyen1-0/+37
The DWC_usb32 controller supports dual-lane SuperSpeed Plus. Check the maximum_speed property for any limitation in the HW to initialize and validate the maximum number of lanes and speed the device will operate. Currently the controller has no visibility into the HW parameter to determine the maximum number of lanes the HW supports. If the number of lanes is not specified for SSP, then set the default rate to gen2x2 for DWC_usb32 and gen2x1 for DWC_usb31. Signed-off-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/08d43f2a99198bed84895c272340449a6d03710e.1611106162.git.Thinh.Nguyen@synopsys.com Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-05usb: dwc3: fix clock issue during resume in OTG modeGary Bisson1-1/+1
Commit fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core") introduced clock support and a new function named dwc3_core_init_for_resume() which enables the clock before calling dwc3_core_init() during resume as clocks get disabled during suspend. Unfortunately in this commit the DWC3_GCTL_PRTCAP_OTG case was forgotten and therefore during resume, a platform could call dwc3_core_init() without re-enabling the clocks first, preventing to resume properly. So update the resume path to call dwc3_core_init_for_resume() as it should. Fixes: fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core") Cc: [email protected] Signed-off-by: Gary Bisson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-12usb: dwc3: Simplify with dev_err_probe()Andy Shevchenko1-33/+11
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-12usb: dwc3: core: Replace devm_reset_control_array_get()Yejune Deng1-1/+1
devm_reset_control_array_get_optional_shared() looks more readable Reviewed-by: Dmitry Osipenko <[email protected]> Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Yejune Deng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-28usb: fix kernel-doc markupsMauro Carvalho Chehab1-1/+1
There is a common comment marked, instead, with kernel-doc notation. Also, some identifiers have different names between their prototypes and the kernel-doc markup. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Acked-by: Felipe Balbi <[email protected]> Link: https://lore.kernel.org/r/0b964be3884def04fcd20ea5c12cb90d0014871c.1603469755.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-02usb: dwc3: Add splitdisable quirk for Hisilicon Kirin SocYu Chen1-0/+25
SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core of Hisilicon Kirin Soc when dwc3 core act as host. [mchehab: dropped a dev_dbg() as only traces are now allowwed on this driver] Signed-off-by: Yu Chen <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: core: add phy cleanup for probe error handlingLi Jun1-0/+11
Add the phy cleanup if dwc3 mode init fail, which is the missing part of de-init for dwc3 core init. Fixes: c499ff71ff2a ("usb: dwc3: core: re-factor init and exit paths") Cc: <[email protected]> Signed-off-by: Li Jun <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: core: don't trigger runtime pm when remove driverLi Jun1-2/+2
No need to trigger runtime pm in driver removal, otherwise if user disable auto suspend via sys file, runtime suspend may be entered, which will call dwc3_core_exit() again and there will be clock disable not balance warning: [ 2026.820154] xhci-hcd xhci-hcd.0.auto: remove, state 4 [ 2026.825268] usb usb2: USB disconnect, device number 1 [ 2026.831017] xhci-hcd xhci-hcd.0.auto: USB bus 2 deregistered [ 2026.836806] xhci-hcd xhci-hcd.0.auto: remove, state 4 [ 2026.842029] usb usb1: USB disconnect, device number 1 [ 2026.848029] xhci-hcd xhci-hcd.0.auto: USB bus 1 deregistered [ 2026.865889] ------------[ cut here ]------------ [ 2026.870506] usb2_ctrl_root_clk already disabled [ 2026.875082] WARNING: CPU: 0 PID: 731 at drivers/clk/clk.c:958 clk_core_disable+0xa0/0xa8 [ 2026.883170] Modules linked in: dwc3(-) phy_fsl_imx8mq_usb [last unloaded: dwc3] [ 2026.890488] CPU: 0 PID: 731 Comm: rmmod Not tainted 5.8.0-rc7-00280-g9d08cca-dirty #245 [ 2026.898489] Hardware name: NXP i.MX8MQ EVK (DT) [ 2026.903020] pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) [ 2026.908594] pc : clk_core_disable+0xa0/0xa8 [ 2026.912777] lr : clk_core_disable+0xa0/0xa8 [ 2026.916958] sp : ffff8000121b39a0 [ 2026.920271] x29: ffff8000121b39a0 x28: ffff0000b11f3700 [ 2026.925583] x27: 0000000000000000 x26: ffff0000b539c700 [ 2026.930895] x25: 000001d7e44e1232 x24: ffff0000b76fa800 [ 2026.936208] x23: ffff0000b76fa6f8 x22: ffff800008d01040 [ 2026.941520] x21: ffff0000b539ce00 x20: ffff0000b7105000 [ 2026.946832] x19: ffff0000b7105000 x18: 0000000000000010 [ 2026.952144] x17: 0000000000000001 x16: 0000000000000000 [ 2026.957456] x15: ffff0000b11f3b70 x14: ffffffffffffffff [ 2026.962768] x13: ffff8000921b36f7 x12: ffff8000121b36ff [ 2026.968080] x11: ffff8000119e1000 x10: ffff800011bf26d0 [ 2026.973392] x9 : 0000000000000000 x8 : ffff800011bf3000 [ 2026.978704] x7 : ffff800010695d68 x6 : 0000000000000252 [ 2026.984016] x5 : ffff0000bb9881f0 x4 : 0000000000000000 [ 2026.989327] x3 : 0000000000000027 x2 : 0000000000000023 [ 2026.994639] x1 : ac2fa471aa7cab00 x0 : 0000000000000000 [ 2026.999951] Call trace: [ 2027.002401] clk_core_disable+0xa0/0xa8 [ 2027.006238] clk_core_disable_lock+0x20/0x38 [ 2027.010508] clk_disable+0x1c/0x28 [ 2027.013911] clk_bulk_disable+0x34/0x50 [ 2027.017758] dwc3_core_exit+0xec/0x110 [dwc3] [ 2027.022122] dwc3_suspend_common+0x84/0x188 [dwc3] [ 2027.026919] dwc3_runtime_suspend+0x74/0x9c [dwc3] [ 2027.031712] pm_generic_runtime_suspend+0x28/0x40 [ 2027.036419] genpd_runtime_suspend+0xa0/0x258 [ 2027.040777] __rpm_callback+0x88/0x140 [ 2027.044526] rpm_callback+0x20/0x80 [ 2027.048015] rpm_suspend+0xd0/0x418 [ 2027.051503] __pm_runtime_suspend+0x58/0xa0 [ 2027.055693] dwc3_runtime_idle+0x7c/0x90 [dwc3] [ 2027.060224] __rpm_callback+0x88/0x140 [ 2027.063973] rpm_idle+0x78/0x150 [ 2027.067201] __pm_runtime_idle+0x58/0xa0 [ 2027.071130] dwc3_remove+0x64/0xc0 [dwc3] [ 2027.075140] platform_drv_remove+0x28/0x48 [ 2027.079239] device_release_driver_internal+0xf4/0x1c0 [ 2027.084377] driver_detach+0x4c/0xd8 [ 2027.087954] bus_remove_driver+0x54/0xa8 [ 2027.091877] driver_unregister+0x2c/0x58 [ 2027.095799] platform_driver_unregister+0x10/0x18 [ 2027.100509] dwc3_driver_exit+0x14/0x1408 [dwc3] [ 2027.105129] __arm64_sys_delete_module+0x178/0x218 [ 2027.109922] el0_svc_common.constprop.0+0x68/0x160 [ 2027.114714] do_el0_svc+0x20/0x80 [ 2027.118031] el0_sync_handler+0x88/0x190 [ 2027.121953] el0_sync+0x140/0x180 [ 2027.125267] ---[ end trace 027f4f8189958f1f ]--- [ 2027.129976] ------------[ cut here ]------------ Fixes: fc8bb91bc83e ("usb: dwc3: implement runtime PM") Cc: <[email protected]> Signed-off-by: Li Jun <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: core: do not queue work if dr_mode is not USB_DR_MODE_OTGLi Jun1-3/+3
Do not try to queue a drd work if dr_mode is not USB_DR_MODE_OTG because the work is not inited, this may be triggered by user try to change mode file of debugfs on a single role port, which will cause below kernel dump: [ 60.115529] ------------[ cut here ]------------ [ 60.120166] WARNING: CPU: 1 PID: 627 at kernel/workqueue.c:1473 __queue_work+0x46c/0x520 [ 60.128254] Modules linked in: [ 60.131313] CPU: 1 PID: 627 Comm: sh Not tainted 5.7.0-rc4-00022-g914a586-dirty #135 [ 60.139054] Hardware name: NXP i.MX8MQ EVK (DT) [ 60.143585] pstate: a0000085 (NzCv daIf -PAN -UAO) [ 60.148376] pc : __queue_work+0x46c/0x520 [ 60.152385] lr : __queue_work+0x314/0x520 [ 60.156393] sp : ffff8000124ebc40 [ 60.159705] x29: ffff8000124ebc40 x28: ffff800011808018 [ 60.165018] x27: ffff800011819ef8 x26: ffff800011d39980 [ 60.170331] x25: ffff800011808018 x24: 0000000000000100 [ 60.175643] x23: 0000000000000013 x22: 0000000000000001 [ 60.180955] x21: ffff0000b7c08e00 x20: ffff0000b6c31080 [ 60.186267] x19: ffff0000bb99bc00 x18: 0000000000000000 [ 60.191579] x17: 0000000000000000 x16: 0000000000000000 [ 60.196891] x15: 0000000000000000 x14: 0000000000000000 [ 60.202202] x13: 0000000000000000 x12: 0000000000000000 [ 60.207515] x11: 0000000000000000 x10: 0000000000000040 [ 60.212827] x9 : ffff800011d55460 x8 : ffff800011d55458 [ 60.218138] x7 : ffff0000b7800028 x6 : 0000000000000000 [ 60.223450] x5 : ffff0000b7800000 x4 : 0000000000000000 [ 60.228762] x3 : ffff0000bb997cc0 x2 : 0000000000000001 [ 60.234074] x1 : 0000000000000000 x0 : ffff0000b6c31088 [ 60.239386] Call trace: [ 60.241834] __queue_work+0x46c/0x520 [ 60.245496] queue_work_on+0x6c/0x90 [ 60.249075] dwc3_set_mode+0x48/0x58 [ 60.252651] dwc3_mode_write+0xf8/0x150 [ 60.256489] full_proxy_write+0x5c/0xa8 [ 60.260327] __vfs_write+0x18/0x40 [ 60.263729] vfs_write+0xdc/0x1c8 [ 60.267045] ksys_write+0x68/0xf0 [ 60.270360] __arm64_sys_write+0x18/0x20 [ 60.274286] el0_svc_common.constprop.0+0x68/0x160 [ 60.279077] do_el0_svc+0x20/0x80 [ 60.282394] el0_sync_handler+0x10c/0x178 [ 60.286403] el0_sync+0x140/0x180 [ 60.289716] ---[ end trace 70b155582e2b7988 ]--- Signed-off-by: Li Jun <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-09-24usb: dwc3: core: Print warning on unsupported speedThinh Nguyen1-0/+9
The user may have more information to override the HW parameter to specify the maximum_speed. However, if the user specifies a maximum_speed that the controller doesn't support, print out a warning. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-09-24usb: dwc3: core: Properly default unspecified speedThinh Nguyen1-17/+18
If the maximum_speed is not specified, default the device speed base on its HW capability. Don't prematurely check HW capability before validating the maximum_speed device property. The device property takes precedence in dwc->maximum_speed. Fixes: 0e1e5c47f7a9 ("usb: dwc3: add support for USB 2.0-only core configuration") Reported-by: Chunfeng Yun <[email protected]> Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-3/+2
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <[email protected]>
2020-07-15usb: dwc3: Replace HTTP links with HTTPS onesAlexander A. Klimov1-1/+1
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-05-25usb: dwc3: Add support for DWC_usb32 IPThinh Nguyen1-27/+22
Synopsys introduces a new controller DWC_usb32. It supports dual-lane and speed up to 20 Gbps, and the DWC3 driver will drive this controller. Currently the driver uses a single field dwc->revision to ID both DWC_usb3 and DWC_usb31 and their version number. This was sufficient for two IPs, but this method doesn't work with additional IPs. As a result, let's separate the dwc->revision field to 2 separate fields: ip and revision. The ip field now stores the ID of the controller's IP while the revision field stores the controller's version number. This new scheme enforces DWC3 to compare the revision within the same IP only. As a result, we must update all the revision check of the controller to check its corresponding IP. To help with this enforcement, we create a few macros to help with the common version checks: DWC3_IP_IS(IP) DWC3_VER_IS(IP, VERSION) DWC3_VER_IS_PRIOR(IP, VERSION) DWC3_VER_IS_WITHIN(IP, LOWER_VERSION, UPPER_VERSION) DWC3_VER_TYPE_IS_WITHIN(IP, VERSION, LOWER_VERSION_TYPE, UPPER_VERSION_TYPE) The DWC_usb32 controller operates using the same programming model and with very similar configurations as its previous controllers. Please note that the various IP and revision checks in this patch match the current checks for DWC_usb31 version 1.90a. Additional configurations that are unique to DWC_usb32 are applied separately. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-05usb: dwc3: core: Use role-switch default dr_modeThinh Nguyen1-0/+2
If the driver is configured to use DRD role-switch, let the drd code path decide the default dr_mode. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-05usb: dwc3: support continuous runtime PM with dual roleMartin Kepplinger1-3/+8
The DRD module calls dwc3_set_mode() on role switches, i.e. when a device is being plugged in. In order to support continuous runtime power management when plugging in / unplugging a cable, we need to call pm_runtime_get_sync() in this path. Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: core: don't do suspend for device mode if already suspendedLi Jun1-0/+2
If dwc->dev in device mode already runtime suspended, don't do it again for system suspend. Signed-off-by: Li Jun <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: Rework resets initialization to be more flexibleJohn Stultz1-1/+1
The dwc3 core binding specifies one reset. However some variants of the hardware may have more. Previously this was handled by using the dwc3-of-simple glue driver, but that resulted in a proliferation of bindings for for every variant, when the only difference was the clocks and resets lists. So this patch reworks the reading of the resets to fetch all the resets specified in the dts together. This patch was recommended by Rob Herring <[email protected]> as an alternative to creating multiple bindings for each variant of hardware. Cc: Greg Kroah-Hartman <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> CC: ShuFan Lee <[email protected]> Cc: Heikki Krogerus <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Chunfeng Yun <[email protected]> Cc: Yu Chen <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Hans de Goede <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Jun Li <[email protected]> Cc: Valentin Schneider <[email protected]> Cc: Guillaume Gardet <[email protected]> Cc: Jack Pham <[email protected]> Cc: [email protected] Cc: [email protected] Suggested-by: Rob Herring <[email protected]> Signed-off-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: Rework clock initialization to be more flexibleJohn Stultz1-15/+5
The dwc3 core binding specifies three clocks: ref, bus_early, and suspend which are all controlled in the driver together. However some variants of the hardware my not have all three clks, or some may have more. Usually this was handled by using the dwc3-of-simple glue driver, but that resulted in a proliferation of bindings for for every variant, when the only difference was the clocks and resets lists. So this patch reworks the reading of the clks from the dts to use devm_clk_bulk_get_all() will will fetch all the clocks specified in the dts together. This patch was recommended by Rob Herring <[email protected]> as an alternative to creating multiple bindings for each variant of hardware. Cc: Greg Kroah-Hartman <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> CC: ShuFan Lee <[email protected]> Cc: Heikki Krogerus <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Chunfeng Yun <[email protected]> Cc: Yu Chen <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Hans de Goede <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Jun Li <[email protected]> Cc: Valentin Schneider <[email protected]> Cc: Guillaume Gardet <[email protected]> Cc: Jack Pham <[email protected]> Cc: [email protected] Cc: [email protected] Suggested-by: Rob Herring <[email protected]> Signed-off-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc3: core: add support for disabling SS instances in park modeNeil Armstrong1-0/+5
In certain circumstances, the XHCI SuperSpeed instance in park mode can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high load on the single XHCI SuperSpeed instance, the controller can crash like: xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. xhci-hcd xhci-hcd.0.auto: Host halt failed, -110 xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. hub 2-1.1:1.0: hub_ext_port_status failed (err = -22) xhci-hcd xhci-hcd.0.auto: HC died; cleaning up usb 2-1.1-port1: cannot reset (err = -22) Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates the issue. The bit is described as : "When this bit is set to '1' all SS bus instances in park mode are disabled" Synopsys explains: The GUCTL1.PARKMODE_DISABLE_SS is only available in dwc_usb3 controller running in host mode. This should not be set for other IPs. This can be disabled by default based on IP, but I recommend to have a property to enable this feature for devices that need this. CC: Dongjin Kim <[email protected]> Cc: Jianxin Pan <[email protected]> Cc: Thinh Nguyen <[email protected]> Cc: Jun Li <[email protected]> Reported-by: Tim <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-01-15usb: dwc3: turn off VBUS when leaving host modeBin Liu1-0/+3
VBUS should be turned off when leaving the host mode. Set GCTL_PRTCAP to device mode in teardown to de-assert DRVVBUS pin to turn off VBUS power. Fixes: 5f94adfeed97 ("usb: dwc3: core: refactor mode initialization to its own function") Cc: [email protected] Signed-off-by: Bin Liu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-11-18Merge tag 'usb-for-v5.5' of ↵Greg Kroah-Hartman1-0/+37
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: USB: changes for v5.5 We have TI's glue layer for the Cadence USB3 controller going upstream. Tegra's XUDC driver is also going upstream with this pull request. Apart from these two big features, we have a bunch of patches switching over to devm_platform_ioremap_resource() in order to simplify code a little; and a non-critical fix for DWC3 usage via kexec. * tag 'usb-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (44 commits) usb: dwc3: of-simple: add a shutdown usb: cdns3: Add TI specific wrapper driver dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller usb: mtu3: fix race condition about delayed_status usb: gadget: Add UDC driver for tegra XUSB device mode controller usb: dwc3: debug: Remove newline printout usb: dwc2: use a longer core rest timeout in dwc2_core_reset() usb: gadget: udc: lpc32xx: Use devm_platform_ioremap_resource() in lpc32xx_udc_probe() USB: gadget: udc: clean up an indentation issue usb: gadget: Quieten gadget config message phy: renesas: rcar-gen3-usb2: Use platform_get_irq_optional() for optional irq usb: gadget: Remove set but not used variable 'opts' in msg_do_config usb: gadget: Remove set but not used variable 'opts' in acm_ms_do_config usb: mtu3: add a new function to do status stage usb: gadget: configfs: fix concurrent issue between composite APIs usb: gadget: f_tcm: Provide support to get alternate setting in tcm function usb: gadget: Correct NULL pointer checking in fsl gadget usb: fsl: Remove unused variable USB: dummy-hcd: use usb_urb_dir_in instead of usb_pipein USB: dummy-hcd: increase max number of devices to 32 ...
2019-10-27usb: dwc3: remove the call trace of USBx_GFLADJYinbo Zhu1-2/+1
layerscape board sometimes reported some usb call trace, that is due to kernel sent LPM tokerns automatically when it has no pending transfers and think that the link is idle enough to enter L1, which procedure will ask usb register has a recovery,then kernel will compare USBx_GFLADJ and set GFLADJ_30MHZ, GFLADJ_30MHZ_REG until GFLADJ_30MHZ is equal 0x20, if the conditions were met then issue occur, but whatever the conditions whether were met that usb is all need keep GFLADJ_30MHZ of value is 0x20 (xhci spec ask use GFLADJ_30MHZ to adjust any offset from clock source that generates the clock that drives the SOF counter, 0x20 is default value of it)That is normal logic, so need remove the call trace. Signed-off-by: Yinbo Zhu <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-10-22usb: dwc3: Disable phy suspend after power-on resetThinh Nguyen1-0/+37
For DRD controllers, the programming guide recommended that GUSB3PIPECTL.SUSPENDABLE and GUSB2PHYCFG.SUSPHY to be cleared after power-on reset and only set after the controller initialization is completed. This can be done after device soft-reset in dwc3_core_init(). This patch makes sure to clear GUSB3PIPECTL.SUSPENDABLE and GUSB2PHYCFG.SUSPHY before core initialization and only set them after the device soft-reset is completed. Reference: DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 1.2.49 and 1.2.45 Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-09-03usb: dwc3: remove generic PHY calibrate() callsMarek Szyprowski1-2/+0
Calls to USB2 generic PHY calibrate() method has been moved to HCD core, which now successfully handles generic PHYs and their calibration after every HCD reset. This fixes all the timing issues related to PHY calibration done directly from DWC3 driver: incorrect operation after system suspend/resume or USB3.0 detection failure when XHCI-plat driver compiled as separate module. Signed-off-by: Marek Szyprowski <[email protected]> Tested-by: Anand Moon <[email protected]> Tested-by: Jochen Sprickerhof <[email protected]> Acked-by: Felipe Balbi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-08-28usb: dwc3: Separate field holding multiple propertiesThinh Nguyen1-2/+1
dwc->hird_threshold field should store "snps,hird_threshold" property only and not a combination of multiple properties. Remove the value of "snps,is-utmi-l1-suspend" property from the field dwc->hird_threshold. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-08-09usb: dwc3: Use clk_bulk_prepare_enable()Andrey Smirnov1-18/+5
Use clk_bulk_prepare_enable() and clk_bulk_disable_unprepare() to simplify code a bit. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Chris Healy <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Felipe Balbi <[email protected]>
2019-08-09usb: dwc3: Use devres to get clocksAndrey Smirnov1-5/+2
Use devres to get clocks and drop explicit clock freeing. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Chris Healy <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Felipe Balbi <[email protected]>
2019-08-09usb: dwc3: Update soft-reset wait polling rateThinh Nguyen1-5/+18
Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit will not be cleared until after all the internal clocks are synchronized during soft-reset. This may take a little more than 50ms. Set the polling rate at 20ms instead. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-08-09usb: dwc3: Switch to use device_property_count_u32()Andy Shevchenko1-2/+1
Use use device_property_count_u32() directly, that makes code neater. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-06-18usb: dwc3: gadget: Add support for disabling U1 and U2 entriesAnurag Kumar Vulisha1-0/+4
Gadget applications may have a requirement to disable the U1 and U2 entry based on the usecase. Below are few usecases where the disabling U1/U2 entries may be possible. Usecase 1: When combining dwc3 with an redriver for a USB Type-C device solution, it sometimes have problems with leaving U1/U2 for certain hosts, resulting in link training errors and reconnects. For this U1/U2 state entries may be avoided. Usecase 2: When performing performance benchmarking on mass storage gadget the U1 and U2 entries can be disabled. Usecase 3: When periodic transfers like ISOC transfers are used with bInterval of 1 which doesn't require the link to enter into U1 or U2 state entry (since ping is issued from host for every uframe interval). In this case the U1 and U2 entry can be disabled. Disablement of U1/U2 can be done by setting U1DevExitLat and U2DevExitLat values to 0 in the BOS descriptor. Host on seeing 0 value for U1DevExitLat and U2DevExitLat, it doesn't send SET_SEL requests to the gadget. There may be some hosts which may send SET_SEL requests even after seeing 0 in the UxDevExitLat of BOS descriptor. To aviod U1/U2 entries for these type of hosts, dwc3 controller can be programmed to reject those U1/U2 requests by not enabling ACCEPTUxENA bits in DCTL register. This patch updates the same. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Claus H. Stovgaard <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-06-18usb: dwc3: Fix core validation in probe, move after clocks are enabledEnric Balletbo i Serra1-5/+7
The required clocks needs to be enabled before the first register access. After commit fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core"), this happens when the dwc3_core_is_valid function is called, but the mentioned commit adds that call in the wrong place, before the clocks are enabled. So, move that call after the clk_bulk_enable() to ensure the clocks are enabled and the reset deasserted. I detected this while, as experiment, I tried to move the clocks and resets from the glue layer to the DWC3 core on a Samsung Chromebook Plus. That was not detected before because, in most cases, the glue layer initializes SoC-specific things and then populates the child "snps,dwc3" with those clocks already enabled. Fixes: b873e2d0ea1ef ("usb: dwc3: Do core validation early on probe") Signed-off-by: Enric Balletbo i Serra <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc3: Fix default lpm_nyet_threshold valueThinh Nguyen1-1/+1
The max possible value for DCTL.LPM_NYET_THRES is 15 and not 255. Change the default value to 15. Cc: [email protected] Fixes: 80caf7d21adc ("usb: dwc3: add lpm erratum support") Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc3: Do core validation early on probeThinh Nguyen1-6/+5
The setting of the dr_mode may need to check the controller's revision. The revision is set in the dwc3_core_is_valid(), which comes after dr_mode setting. Let's move it closer to the start of the dwc3_probe() function and before calling dwc3_get_dr_mode(). Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc3: move synchronize_irq() out of the spinlock protected blockMarek Szyprowski1-0/+2
dwc3_gadget_suspend() is called under dwc->lock spinlock. In such context calling synchronize_irq() is not allowed. Move the problematic call out of the protected block to fix the following kernel BUG during system suspend: BUG: sleeping function called from invalid context at kernel/irq/manage.c:112 in_atomic(): 1, irqs_disabled(): 128, pid: 1601, name: rtcwake 6 locks held by rtcwake/1601: #0: f70ac2a2 (sb_writers#7){.+.+}, at: vfs_write+0x130/0x16c #1: b5fe1270 (&of->mutex){+.+.}, at: kernfs_fop_write+0xc0/0x1e4 #2: 7e597705 (kn->count#60){.+.+}, at: kernfs_fop_write+0xc8/0x1e4 #3: 8b3527d0 (system_transition_mutex){+.+.}, at: pm_suspend+0xc4/0xc04 #4: fc7f1c42 (&dev->mutex){....}, at: __device_suspend+0xd8/0x74c #5: 4b36507e (&(&dwc->lock)->rlock){....}, at: dwc3_gadget_suspend+0x24/0x3c irq event stamp: 11252 hardirqs last enabled at (11251): [<c09c54a4>] _raw_spin_unlock_irqrestore+0x6c/0x74 hardirqs last disabled at (11252): [<c09c4d44>] _raw_spin_lock_irqsave+0x1c/0x5c softirqs last enabled at (9744): [<c0102564>] __do_softirq+0x3a4/0x66c softirqs last disabled at (9737): [<c0128528>] irq_exit+0x140/0x168 Preemption disabled at: [<00000000>] (null) CPU: 7 PID: 1601 Comm: rtcwake Not tainted 5.0.0-rc3-next-20190122-00039-ga3f4ee4f8a52 #5252 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [<c01110f0>] (unwind_backtrace) from [<c010d120>] (show_stack+0x10/0x14) [<c010d120>] (show_stack) from [<c09a4d04>] (dump_stack+0x90/0xc8) [<c09a4d04>] (dump_stack) from [<c014c700>] (___might_sleep+0x22c/0x2c8) [<c014c700>] (___might_sleep) from [<c0189d68>] (synchronize_irq+0x28/0x84) [<c0189d68>] (synchronize_irq) from [<c05cbbf8>] (dwc3_gadget_suspend+0x34/0x3c) [<c05cbbf8>] (dwc3_gadget_suspend) from [<c05bd020>] (dwc3_suspend_common+0x154/0x410) [<c05bd020>] (dwc3_suspend_common) from [<c05bd34c>] (dwc3_suspend+0x14/0x2c) [<c05bd34c>] (dwc3_suspend) from [<c051c730>] (platform_pm_suspend+0x2c/0x54) [<c051c730>] (platform_pm_suspend) from [<c05285d4>] (dpm_run_callback+0xa4/0x3dc) [<c05285d4>] (dpm_run_callback) from [<c0528a40>] (__device_suspend+0x134/0x74c) [<c0528a40>] (__device_suspend) from [<c052c508>] (dpm_suspend+0x174/0x588) [<c052c508>] (dpm_suspend) from [<c0182134>] (suspend_devices_and_enter+0xc0/0xe74) [<c0182134>] (suspend_devices_and_enter) from [<c0183658>] (pm_suspend+0x770/0xc04) [<c0183658>] (pm_suspend) from [<c0180ddc>] (state_store+0x6c/0xcc) [<c0180ddc>] (state_store) from [<c09a9a70>] (kobj_attr_store+0x14/0x20) [<c09a9a70>] (kobj_attr_store) from [<c02d6800>] (sysfs_kf_write+0x4c/0x50) [<c02d6800>] (sysfs_kf_write) from [<c02d594c>] (kernfs_fop_write+0xfc/0x1e4) [<c02d594c>] (kernfs_fop_write) from [<c02593d8>] (__vfs_write+0x2c/0x160) [<c02593d8>] (__vfs_write) from [<c0259694>] (vfs_write+0xa4/0x16c) [<c0259694>] (vfs_write) from [<c0259870>] (ksys_write+0x40/0x8c) [<c0259870>] (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28) Exception stack(0xed55ffa8 to 0xed55fff0) ... Fixes: 01c10880d242 ("usb: dwc3: gadget: synchronize_irq dwc irq in suspend") Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc3: Free resource immediately after useAndy Shevchenko1-0/+3
When we read an array of integers from device properties, the temporary buffer is allocated. However, in case of dwc3_set_incr_burst_type() it's not freed. Free allocated buffer immediately after use. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Add workaround for isoc start transfer failureThinh Nguyen1-0/+2
In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the XferNotReady event are invalid. The driver uses this number to schedule the isochronous transfer and passes it to the START TRANSFER command. Because this number is invalid, the command may fail. If BIT[15:14] matches the internal 16-bit microframe, the START TRANSFER command will pass and the transfer will start at the scheduled time, if it is off by 1, the command will still pass, but the transfer will start 2 seconds in the future. For all other conditions, the START TRANSFER command will fail with bus-expiry. In order to workaround this issue, we can test for the correct combination of BIT[15:14] by sending START TRANSFER commands with different values of BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. As the result, within the 4 possible combinations for BIT[15:14], there will be 2 successful and 2 failure START COMMAND status. One of the 2 successful command status will result in a 2-second delay start. The smaller BIT[15:14] value is the correct combination. Since there are only 4 outcomes and the results are ordered, we can simply test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to deduce the smaller successful combination. Let test0 = test status for combination 'b00 and test1 = test status for 'b01 of BIT[15:14]. The correct combination is as follow: if test0 fails and test1 passes, BIT[15:14] is 'b01 if test0 fails and test1 fails, BIT[15:14] is 'b10 if test0 passes and test1 fails, BIT[15:14] is 'b11 if test0 passes and test1 passes, BIT[15:14] is 'b00 Synopsys STAR 9001202023: Wrong microframe number for isochronous IN endpoints. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Track DWC_usb31 VERSIONTYPEThinh Nguyen1-0/+1
Add a new field to dwc3 structure to track VERSIONTYPE. The VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register. In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE such as "ea01" and "ea02". Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Set default mode for DWC_usb3 v3.30a and higherThinh Nguyen1-4/+5
DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG mode. If the controller supports DRD but the dr_mode is not specified or set to OTG, then set the mode to peripheral. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: don't log probe deferrals; but do log other error codesBrian Norris1-1/+2
It's not very useful to repeat a bunch of probe deferral errors. And it's also not very useful to log "failed" without telling the error code. Signed-off-by: Brian Norris <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Support option to disable USB2 LPMThinh Nguyen1-0/+2
Support the option to disable USB2 LPM. Set xhci "usb2-lpm-disable" property via "snps,usb2-lpm-disable" property. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-26usb: dwc3: Set GUSB2PHYCFG.ENBLSLPMThinh Nguyen1-0/+2
GUSB2PHYCFG.ENBLSLPM enables the controller to assert low power signals to the PHY. Unless disabled via device property, explicitly set GUSB2PHYCFG.ENBLSLPM as it may not be set by default. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-11-06usb: dwc3: core: Clean up ULPI deviceAndy Shevchenko1-0/+1
If dwc3_core_init_mode() fails with deferred probe, next probe fails on sysfs with sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:11.0/dwc3.0.auto/dwc3.0.auto.ulpi' To avoid this failure, clean up ULPI device. Cc: <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-10-02usb: dwc3: Fix spelling of 'optimizations'Faisal Mehmood1-1/+1
'optimizations' was misspelled as 'optmizations'. Fixed it. It is a coding style change which should have no impact on runtime execution of code. Signed-off-by: Faisal Mehmood <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc3: core: Enable AutoRetry feature in the controllerAnurag Kumar Vulisha1-0/+16
By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc3: Set default mode for dwc_usb31Thinh Nguyen1-0/+8
dwc_usb31 does not support OTG mode. If the controller supports DRD but the dr_mode is not specified or set to OTG, then set the mode to peripheral. Signed-off-by: Thinh Nguyen <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>