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Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Fix build errors when CONFIG_PINCTRL is not enabled.
The header file <linux/pinctrl/consumer.h> handles both CONFIG_PINCTRL
enabled and disabled cases.
CC [M] drivers/spi/spi-at91-usart.o
../drivers/spi/spi-at91-usart.c: In function 'at91_usart_spi_runtime_suspend':
../drivers/spi/spi-at91-usart.c:409:2: error: implicit declaration of function 'pinctrl_pm_select_sleep_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_sleep_state(dev);
../drivers/spi/spi-at91-usart.c: In function 'at91_usart_spi_runtime_resume':
../drivers/spi/spi-at91-usart.c:419:2: error: implicit declaration of function 'pinctrl_pm_select_default_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_default_state(dev);
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Radu Pirea <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Signed-off-by: Mark Brown <[email protected]>
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Make everything look intentional by having a C++ comment for the whole
block, not just the SPDX line.
Signed-off-by: Mark Brown <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-4.21
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Commit e82b0b382845 ("spi: bcm2835: Fix race on DMA termination") broke
the build with COMPILE_TEST=y on arches whose cmpxchg() requires 32-bit
operands (xtensa, older arm ISAs).
Fix by changing the dma_pending flag's type from bool to unsigned int.
Fixes: e82b0b382845 ("spi: bcm2835: Fix race on DMA termination")
Signed-off-by: Lukas Wunner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A few driver specific fixes here, nothing big or that stands out for
anyone other than the driver users.
The omap2-mcspi fix is for issues that started showing up with a
change in defconfig in this release to make cpuidle get turned on by
default"
* tag 'spi-fix-v4.20-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: omap2-mcspi: Add missing suspend and resume calls
spi: mediatek: use correct mata->xfer_len when in fifo transfer
spi: uniphier: fix incorrect property items
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When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <[email protected]>
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Document the driver's data structure to lower the barrier to entry for
contributors.
Signed-off-by: Lukas Wunner <[email protected]>
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Commit a30a555d7435 ("spi: bcm2835: transform native-cs to gpio-cs on
first spi_setup") disabled the use of hardware-controlled native Chip
Select in favour of software-controlled GPIO Chip Select but left code
to support the former untouched. Remove it to simplify the driver and
ease the addition of new features and further optimizations.
Signed-off-by: Lukas Wunner <[email protected]>
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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If a DMA transfer finishes orderly right when spi_transfer_one_message()
determines that it has timed out, the callbacks bcm2835_spi_dma_done()
and bcm2835_spi_handle_err() race to call dmaengine_terminate_all(),
potentially leading to double termination.
Prevent by atomically changing the dma_pending flag before calling
dmaengine_terminate_all().
Signed-off-by: Lukas Wunner <[email protected]>
Fixes: 3ecd37edaa2a ("spi: bcm2835: enable dma modes for transfers meeting certain conditions")
Cc: [email protected] # v4.2+
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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If submission of a DMA TX transfer succeeds but submission of the
corresponding RX transfer does not, the BCM2835 SPI driver terminates
the TX transfer but neglects to reset the dma_pending flag to false.
Thus, if the next transfer uses interrupt mode (because it is shorter
than BCM2835_SPI_DMA_MIN_LENGTH) and runs into a timeout,
dmaengine_terminate_all() will be called both for TX (once more) and
for RX (which was never started in the first place). Fix it.
Signed-off-by: Lukas Wunner <[email protected]>
Fixes: 3ecd37edaa2a ("spi: bcm2835: enable dma modes for transfers meeting certain conditions")
Cc: [email protected] # v4.2+
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The IRQ handler bcm2835_spi_interrupt() first reads as much as possible
from the RX FIFO, then writes as much as possible to the TX FIFO.
Afterwards it decides whether the transfer is finished by checking if
the TX FIFO is empty.
If very few bytes were written to the TX FIFO, they may already have
been transmitted by the time the FIFO's emptiness is checked. As a
result, the transfer will be declared finished and the chip will be
reset without reading the corresponding received bytes from the RX FIFO.
The odds of this happening increase with a high clock frequency (such
that the TX FIFO drains quickly) and either passing "threadirqs" on the
command line or enabling CONFIG_PREEMPT_RT_BASE (such that the IRQ
handler may be preempted between filling the TX FIFO and checking its
emptiness).
Fix by instead checking whether rx_len has reached zero, which means
that the transfer has been received in full. This is also more
efficient as it avoids one bus read access per interrupt. Note that
bcm2835_spi_transfer_one_poll() likewise uses rx_len to determine
whether the transfer has finished.
Signed-off-by: Lukas Wunner <[email protected]>
Fixes: e34ff011c70e ("spi: bcm2835: move to the transfer_one driver model")
Cc: [email protected] # v4.1+
Cc: Mathias Duckeck <[email protected]>
Cc: Frank Pavlic <[email protected]>
Cc: Martin Sperl <[email protected]>
Cc: Noralf Trønnes <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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this patch add support for mt7629 IC.
Signed-off-by: Leilk Liu <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This patch implements power management callback function for USART as
SPI driver.
Signed-off-by: Radu Pirea <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The compiler has no way to know that rsize 1 or 2 are the only valid
values. Also simplify the code a bit with early return.
The warning was:
drivers/spi/spi-npcm-pspi.c:215:6: warning: 'val' may be used uninitialized in this function [-Wmaybe-uninitialized]
Signed-off-by: Olof Johansson <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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There is an IS_ERR() vs PTR_ERR() typo here. The current code returns 1
but we want to return the negative error code.
Fixes: 2a22f1b30cee ("spi: npcm: add NPCM PSPI controller driver")
Signed-off-by: Dan Carpenter <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Address remaining comments from original driver patch series
* Move RD_FIFO_CFG to be ordered corretly
* Expand spinlock comment
Signed-off-by: Ryan Case <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Most modern SPI controllers can directly map a SPI memory (or a portion
of the SPI memory) in the CPU address space. Most of the time this
brings significant performance improvements as it automates the whole
process of sending SPI memory operations every time a new region is
accessed.
This new API allows SPI memory drivers to create direct mappings and
then use them to access the memory instead of using spi_mem_exec_op().
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The logic surrounding the ->exec_op() call applies to direct mapping
accessors. Move this code to separate functions to avoid duplicating
code.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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When defining spi_mem_op templates we don't necessarily know the size
that will be passed when the template is actually used, and basing the
supports_op() check on op->data.nbytes to know whether there will be
data transferred for a specific operation is this not possible.
Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base
our checks on op->data.dir instead of op->data.nbytes.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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A careless oversight. Sorry.
Fixes: 0a897143b7c9 ("spi: pxa2xx: Add slave mode support")
Signed-off-by: Lubomir Rintel <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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I've been wondering still about omap2-mcspi related suspend and resume
flakeyness and looks like we're missing calls to spi_master_suspend()
and spi_master_resume(). Adding those and using pm_runtime_force_suspend()
and pm_runtime_force_resume() makes things work for suspend and resume
and allows us to stop using noirq suspend and resume.
And while at it, let's use SET_SYSTEM_SLEEP_PM_OPS to simplify things
further.
Signed-off-by: Tony Lindgren <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The refactoring done as part of adding the core support for handling
waiting for slave transfer dropped a conditional which meant that we
started waiting for completion of all transfers, not just those that the
controller asked for. This caused hangs and massive delays on platforms
that don't need the core delay. Re-add the delay to fix this.
Fixes: 810923f3bf06c11 (spi: Deal with slaves that return from transfer_one() unfinished)
Reported-by: Tony Lindgren <[email protected]>
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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drivers/spi/spi-npcm-pspi.c:470:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Fixes: 2a22f1b30cee ("spi: npcm: add NPCM PSPI controller driver")
CC: Tomer Maimon <[email protected]>
Signed-off-by: kbuild test robot <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The license text is specifying GPL v2 or later but the MODULE_LICENSE
is set to GPL v2 which means GNU Public License v2 only. So choose the
license text as the correct one.
Signed-off-by: Stefan Wahren <[email protected]>
Acked-by: Florian Kauer <[email protected]>
Acked-by: Martin Sperl <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The u32 variable csgpio is being checked for an error return
from the call to of_get_named_gpio, however, since this is unsigned
this comparison will always be false. Fix this by making csgpio an
int and fix up the %u format specifiers to %d accordingly.
Detected by CoverityScan, CID#1475476 ("Unsigned compared against 0")
Fixes: 2a22f1b30cee ("spi: npcm: add NPCM PSPI controller driver")
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add Nuvoton NPCM BMC Peripheral SPI controller driver.
Signed-off-by: Tomer Maimon <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Do not deselect cs when cs_change is set for the last transfer in the
message. In this case, cs_change indicates that cs should stay selected
until the next transfer.
Signed-off-by: Fredrik Ternerot <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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There doesn't seem to be a way to empty TXFIFO on MMP2. The datasheet is
super-secret and the method described in Armada 16x manual won't work:
"The TXFIFO and RXFIFO are cleared to 0b0 when the SSPx port is reset or
disabled (by writing a 0b0 to the <Synchronous Serial Port Enable> field
in the SSP Control Register 0)."
# devmem 0xd4037008 # read SSSR
0x0000F204
# devmem 0xd4037000 32 0x07 # SSE off in SSCR0
# devmem 0xd4037000 32 0x87 # SSE on
# devmem 0xd4037008
0x0000F204
^ TXFIFO level is still 2. Sigh.
The OLPC 1.75 boot firmware leaves two bytes in the TXFIFO. Those are
basically throwaway bytes used in response to the messages from the EC.
The OLPC kernel copes with this by power-cycling the hardware. Perhaps
the firmware should do this instead.
Other than that, there's not much we can do other than complain loudly
until the garbage gets drained and discard the actual data... For the
OLPC EC this will work just fine and pushing more data to TXFIFO would
break further transactions.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Strobe a GPIO line when the slave TX FIFO is filled. This is how the
Embedded Controller on an OLPC XO-1.75 machine, that happens to be a SPI
master, learns that it can initiate a transaction.
Signed-off-by: Lubomir Rintel <[email protected]>
Tested-by: Pavel Machek <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Tested on an OLPC XO-1.75 machine, where the Embedded Controller happens
to be a SPI master.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Some drivers, such as spi-pxa2xx return from the transfer_one callback
immediately, idicating that the transfer will be finished asynchronously.
Normally, spi_transfer_one_message() synchronously waits for the
transfer to finish with wait_for_completion_timeout(). For slaves, we
don't want the transaction to time out as it can complete in a long time
in future. Use wait_for_completion_interruptible() instead.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Some devices such as the TPO TPG110 display panel require
a "high-impedance turn-around", in effect a clock cycle after
switching the line from output to input mode.
Support this in the GPIO driver to begin with. Other driver
may implement it if they can, it is unclear if this can
be achieved with anything else than GPIO bit-banging.
Cc: Andrzej Hajda <[email protected]>
Acked-by: Lorenzo Bianconi <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Enable McSPI driver to be built for K3 platforms, to support McSPI on
AM654 SoC of K3 family.
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Kernel contains QSPI driver strongly tied to MTD and nor-flash memory.
New spi-mem interface allows usage also other memory types, especially
much larger NAND with SPI interface. This driver works as SPI controller
and is not related to MTD, however can work with NAND-flash or other
peripherals using spi-mem interface.
Suggested-by: Boris Brezillon <[email protected]>
Signed-off-by: Piotr Bugalski <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add a driver for Macronix SPI controller IP.
Signed-off-by: Mason Yang <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.
Signed-off-by: Wolfram Sang <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.
Signed-off-by: Wolfram Sang <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.
Signed-off-by: Wolfram Sang <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Re-arrange existing APIs in probe function to
avoid using goto and remove redundant variables.
Signed-off-by: Alok Chauhan <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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fixed the nitpicks.
Signed-off-by: Alok Chauhan <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Some SoC share one irq number between DSPI controllers.
For example, on the LX2160 board, DSPI0 and DSPI1 share one irq number.
In this case, only one DSPI controller can register successfully,
and others will fail.
Signed-off-by: Chuanhua Han <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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this patch add support for mt8183 IC.
Signed-off-by: Leilk Liu <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Intel LPSS private register restoring in spi-pxa2xx.c: pxa2xx_spi_resume()
was added before there was no any other code restoring them. This was
changed after following commits for previous and current LPSS platforms:
c78b0830667a ("ACPI / LPSS: custom power domain for LPSS")
41a3da2b8e16 ("mfd: intel-lpss: Save register context on suspend")
However there is one caveat: There is no LPSS private register context
save/restore for the Intel Lynxpoint in the Linux kernel code.
I did some debugging on one Lynxpoint based device I have and on it the
LPSS register context is not lost over suspend/resume cycle (s2idle).
Which happens for instance on Intel Braswell. I'm speculating but I guess
either firmware does it or the LPSS is kept always on Lynxpoint.
Given that we haven't needed to implement Lynxpoint LPSS I2C or UART
private register context save/restore over four years time I think we are
safe to remove this LPSS private register restoring during resume here.
Signed-off-by: Jarkko Nikula <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add missing support for lsb-first mode.
Signed-off-by: Emil Renner Berthing <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The hardware supports 4, 8 and 16bit spi words,
so add the missing support for 4bit words.
Signed-off-by: Emil Renner Berthing <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Register an interrupt handler to fill/empty the
tx and rx fifos rather than busy-looping.
Signed-off-by: Emil Renner Berthing <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Now that we no longer potentially change spi clock
at runtime we can precompute the rx sample delay
at probe time rather than for each transfer.
Signed-off-by: Emil Renner Berthing <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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