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2019-03-25spi: at91-usart: Remove duplicated checking for spi->bits_per_wordAxel Lin1-7/+1
This checking is already done in __spi_validate_bits_per_word(). Signed-off-by: Axel Lin <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-25spi: atmel-quadspi: Make atmel_qspi_get_name staticYueHaibing1-1/+1
Fix sparse warning: drivers/spi/atmel-quadspi.c:369:12: warning: symbol 'atmel_qspi_get_name' was not declared. Should it be static? Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-21spi: export tracepoint symbols to modulesArnd Bergmann1-0/+2
The newly added tracepoints in the spi-mxs driver cause a link error when the driver is a loadable module: ERROR: "__tracepoint_spi_transfer_stop" [drivers/spi/spi-mxs.ko] undefined! ERROR: "__tracepoint_spi_transfer_start" [drivers/spi/spi-mxs.ko] undefined! I'm not quite sure where to put the export statements, but directly after the inclusion of the header seems as good as any other place. Fixes: f3fdea3af405 ("spi: mxs: add tracing to custom .transfer_one_message callback") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-21spi: lpspi: fix dataloss when SS is inactivated between every wordsClark Wang1-2/+2
If we don't use CONT to keep SS activated or use DMA mode without cs-gpio, SS will be inactivated between every words. The word here means the data sent once which length can be set as 1/2/4 bytes. In the isr function, we read the FSR_RXCOUNT just behind the fsl_lpspi_read_rx_fifo. This causes the value of FSR_RXCOUNT cannot reflect whether there is still data not sent timely. So do this judgement by FSR_TXCOUNT. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-21dmaengine: idma64: Use actual device for DMA transfersAndy Shevchenko1-6/+1
Intel IOMMU, when enabled, tries to find the domain of the device, assuming it's a PCI one, during DMA operations, such as mapping or unmapping. Since we are splitting the actual PCI device to couple of children via MFD framework (see drivers/mfd/intel-lpss.c for details), the DMA device appears to be a platform one, and thus not an actual one that performs DMA. In a such situation IOMMU can't find or allocate a proper domain for its operations. As a result, all DMA operations are failed. In order to fix this, supply parent of the platform device to the DMA engine framework and fix filter functions accordingly. We may rely on the fact that parent is a real PCI device, because no other configuration is present in the wild. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Mark Brown <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> [for tty parts] Signed-off-by: Vinod Koul <[email protected]>
2019-03-20spi: pxa2xx: Debug print DMA burst sizeAndy Shevchenko1-0/+3
It's useful during debug to see what DMA burst size is. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Jarkko Nikula <[email protected]> Reviewed-by: Jarkko Nikula <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-20spi: pxa2xx: Introduce DMA burst size supportAndy Shevchenko3-1/+8
Some masters may have different DMA burst size than hard coded default. In such case respect the value given by DMA burst size provided via platform data. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Jarkko Nikula <[email protected]> Reviewed-by: Jarkko Nikula <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-20spi: dw: Add support for an optional interface clockPhil Edworthy1-0/+12
The Synopsys SSI Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy <[email protected]> Signed-off-by: Gareth Williams <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-20spi: mxic: simplify getting .driver_dataWolfram Sang1-4/+2
We should get 'driver_data' from 'struct device' directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-20spi: spi-mem: stm32-qspi: stm32_qspi_pm_ops can be statickbuild test robot1-1/+1
Fixes: 2e541b64ee52 ("spi: spi-mem: stm32-qspi: add suspend/resume support") Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-19Merge tag 'v5.1-rc1' into spi-5.2Mark Brown1-1/+0
Linux 5.1-rc1
2019-03-19spi: pxa2xx-pci: Drop unused header inclusionAndy Shevchenko1-1/+0
There is nothing in the driver which requires OF specific header to be included. Remove it for good. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Jarkko Nikula <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-19spi: lpspi: fsl_lpspi_runtime_resume() can be statickbuild test robot1-2/+2
Fixes: 944c01a889d9 ("spi: lpspi: enable runtime pm for lpspi") Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: spi-fsl-spi: support use of the SPISEL_BOOT signal on MPC8309Rasmus Villemoes2-5/+37
The MPC8309 has a dedicated signal, SPISEL_BOOT, usually used as chip select for the flash device from which the bootloader is loaded. It is not an ordinary gpio, but is simply controlled via the SPI_CS register in the system configuration. To allow accessing such a spi slave, we need to teach fsl_spi_cs_control() how to control the SPISEL_BOOT signal. To distinguish the gpio-controlled slaves, continue to have those use chip_select values of 0..ngpios-1, and use chip_select == ngpios for the boot flash. I'm not too happy with all the ifdeffery, but it seems to be necessary for guarding the sysdev/fsl_soc.h and use of get_immrbase() (spi-fsl-lib.c already contains similar ifdeffery). Googling suggests that the MPC8306 is similar, with the SPI_CS register at the same offset. Signed-off-by: Rasmus Villemoes <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18drivers: Defer probe if firmware is not readyRajan Vaja1-0/+5
Driver needs ZynqMP firmware interface to call EEMI APIs. In case firmware is not ready, dependent drivers should wait until the firmware is ready. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-03-18spi: orion: Support spi_xfer->word_delay_usecsJan Kundrát1-0/+4
Signed-off-by: Jan Kundrát <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: spidev: Enable control of inter-word delaysJan Kundrát1-1/+3
Commit b7bb367afa4b added support for inserting delays in between individual words within a single SPI transaction. This makes it accessible from userspace. WARNING: This delay is silently ignored unless the SPI controller implements extra support for it. This is similar to how the in-kernel users handle the other existing property, spi_transfer->word_delay. Signed-off-by: Jan Kundrát <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: Code cleanupClark Wang1-1/+1
Delete the extra space. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: Add the missing NULL checkClark Wang1-2/+5
The spi_transfer *t will be used in one transfer whatever. If t is NULL, there has no need to try sending data, so add an error return here. Signed-off-by: Clark Wang <[email protected]> Acked-by: Fugang Duan <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: add dma mode supportClark Wang1-11/+301
Add dma mode support for LPSPI. Any frame longer than half txfifosize will be sent by dma mode. For now, there are some limits: 1. The maximum transfer speed in master mode depends on the slave device, at least 40MHz(tested by spi-nor on 8qm-lpddr4-arm2 base board); 2. The maximum transfer speed in slave mode is 15MHz(imx7ulp), 22MHz(8qm/qxp). In order to reach the maximum speed which is mentioned in datasheet, the load of connect wires between master and slave should be less than 15pF. Signed-off-by: Clark Wang <[email protected]> Acked-by: Fugang Duan <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: use the core way to implement cs-gpio functionClark Wang1-35/+66
Use the default implementation of transfer_one_msg/chipselect/setup functions in spi core to implement cs-gpio control. Use fsl_lpspi_prepare_message to init the cs_gpio pin. Signed-off-by: Clark Wang <[email protected]> Acked-by: Fugang Duan <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: add the error info of transfer speed settingClark Wang1-3/+13
Add a error info when set a speed which greater than half of per-clk of spi module. The minimum SCK period is 2 cycles(CCR[SCKDIV]). So the maximum transfer speed is half of spi per-clk. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: enable runtime pm for lpspiHan Xu1-25/+92
Enable the runtime power management for lpspi module. Do some adaptation work from kernel 4.9 to 4.14. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Han Xu <[email protected]> Reviewed-by: Frank Li <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi: lpspi: Add i.MX8 boards support for lpspiClark Wang1-11/+41
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi : spi-topcliff-pch: Fix to handle empty DMA buffersAditya Pakki1-2/+13
pch_alloc_dma_buf allocated tx, rx DMA buffers which can fail. Further, these buffers are used without a check. The patch checks for these failures and sends the error upstream. Signed-off-by: Aditya Pakki <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: spi-mem: stm32-qspi: add suspend/resume supportLudovic Barre1-4/+35
This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15Merge branch 'spi-5.1' into spi-5.2 for stm32Mark Brown4-30/+26
2019-03-15spi: spi-mem: stm32-qspi: avoid memory corruption at low frequencyLudovic Barre1-3/+1
This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: rspi: Fix sequencer reset during initializationGeert Uytterhoeven1-3/+6
While the sequencer is reset after each SPI message since commit 880c6d114fd79a69 ("spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI"), it was never reset for the first message, thus relying on reset state or bootloader settings. Fix this by initializing it explicitly during configuration. Fixes: 0b2182ddac4b8837 ("spi: add support for Renesas RSPI") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: rspi: Fix register initialization while runtime-suspendedGeert Uytterhoeven1-23/+16
The Renesas RSPI/QSPI driver performs SPI controller register initialization in its spi_operations.setup() callback, without calling pm_runtime_get_sync() first, which may cause spurious failures. So far this went unnoticed, as this SPI controller is typically used with a single SPI NOR FLASH containing the boot loader: 1. If the device's module clock is still enabled (left enabled by the bootloader, and not yet disabled by the clk_disable_unused() late initcall), register initialization succeeds, 2. If the device's module clock is disabled, register writes don't seem to cause lock-ups or crashes. Data received in the first SPI message may be corrupted, though. Subsequent SPI messages seem to be OK. E.g. on r8a7791/koelsch, one bit is lost while receiving the 6th byte of the JEDEC ID for the s25fl512s FLASH, corrupting that byte and all later bytes. But until commit a2126b0a010905e5 ("mtd: spi-nor: refine Spansion S25FL512S ID"), the 6th byte was not considered for FLASH identification. Fix this by moving all initialization from the .setup() to the .prepare_message() callback. The latter is always called after the device has been runtime-resumed by the SPI core. This also makes the driver follow the rule that .setup() must not change global driver state or register values, as that might break a transfer in progress. Fixes: 490c97747d5dc77d ("spi: rspi: Add runtime PM support, using spi core auto_runtime_pm") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-13spi: spi-fsl-qspi: use devm_spi_register_controllerVolker Haspel1-1/+1
The driver does not clearly unregister the spi controller. Therefore calling an unbind and bind again will end up in a Kernel crash. The function devm_spi_register_controller will automatically be unregister the SPI device. Signed-off-by: Volker Haspel <[email protected]> Signed-off-by: John Ogness <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-13spi: imx: stop buffer overflow in RX FIFO flushTrent Piepho1-1/+1
Commit 71abd29057cb ("spi: imx: Add support for SPI Slave mode") added an RX FIFO flush before start of a transfer. In slave mode, the master may have sent more data than expected and this data will still be in the RX FIFO at the start of the next transfer, and so needs to be flushed. However, the code to do the flush was accidentally saving this data into the previous transfer's RX buffer, clobbering the contents of whatever followed that buffer. Change it to empty the FIFO and throw away the data. Every one of the RX functions for the different eCSPI versions and modes reads the RX FIFO data using the same readl() call, so just use that, rather than using the spi_imx->rx function pointer and making sure all the different rx functions have a working "throw away" mode. There is another issue, which affects master mode when switching from DMA to PIO. There can be extra data in the RX FIFO which triggers this flush code, causing memory corruption in the same manner. I don't know why this data is unexpectedly in the FIFO. It's likely there is a different bug or erratum responsible for that. But regardless of that, I think this is proper fix the for bug at hand here. Fixes: 71abd29057cb ("spi: imx: Add support for SPI Slave mode") Cc: Jiada Wang <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Stefan Agner <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Trent Piepho <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-11spi: imx: add module parameter to control DMA useTrent Piepho1-0/+7
Add the boolean module parameter "use_dma" to control the use of DMA by the driver. There are about two dozen other drivers with a "use_dma" parameter of some sort. DMA may allow faster and more efficient transfers than using PIO, but it also adds overhead for small transfers. High speed receive operations may be less likely to have issues with FIFO overflow when using DMA than when using PIO. The eCSPI appears to insert a 4 bit pause after each word in DMA mode, not done in PIO mode, which can make DMA transfers 50% slower than PIO. In some cases DMA may be a net win while in others PIO might be. It depends on the application. So allow DMA to be enabled or disabled at the driver level. The default will be to have it enabled when possible. Signed-off-by: Trent Piepho <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-11spi: Fix zero length xfer bugChris Lesiak1-0/+2
This fixes a bug for messages containing both zero length and unidirectional xfers. The function spi_map_msg will allocate dummy tx and/or rx buffers for use with unidirectional transfers when the hardware can only do a bidirectional transfer. That dummy buffer will be used in place of a NULL buffer even when the xfer length is 0. Then in the function __spi_map_msg, if he hardware can dma, the zero length xfer will have spi_map_buf called on the dummy buffer. Eventually, __sg_alloc_table is called and returns -EINVAL because nents == 0. This fix prevents the error by not using the dummy buffer when the xfer length is zero. Signed-off-by: Chris Lesiak <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-09Merge tag 'pci-v5.1-changes' of ↵Linus Torvalds1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - Use match_string() instead of reimplementing it (Andy Shevchenko) - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada) - Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) - Fix DPC use of uninitialized data (Dongdong Liu) - Probe bridge window attributes only once at enumeration-time to fix device accesses during rescan (Bjorn Helgaas) - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du Changbin) - Use config header type (not class code) identify bridges more reliably (Honghui Zhang) - Work around Intel Denverton incorrect Trace Hub BAR size reporting (Alexander Shishkin) - Reorder pciehp cached state/hardware state updates to avoid missed interrupts (Mika Westerberg) - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann) - Mark expected switch fall-through (Mathieu Malaterre) - Use of_node_name_eq() for node name comparisons (Rob Herring) - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang) - Consolidate Rohm Vendor ID definitions (Andy Shevchenko) - Use u32 (not __u32) for things not exposed to userspace (Logan Gunthorpe) - Fix locking semantics of bus and slot reset interfaces (Alex Williamson) - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang) - Allow portdrv to claim subtractive decode Ports so PCIe services will work for them (Honghui Zhang) - Report PCIe links that become degraded at run-time (Alexandru Gagniuc) - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt hotplug (Mika Westerberg) - Revert runtime PM suspend/resume callbacks that broke PME on network cable plug (Mika Westerberg) - Disable Data Link State Changed interrupts to prevent wakeup immediately after suspend (Mika Westerberg) - Extend altera to support Stratix 10 (Ley Foon Tan) - Allow building altera driver on ARM64 (Ley Foon Tan) - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint maintainer (Lorenzo Pieralisi) - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro) - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) - Configure MPS settings for VMD root ports (Jon Derrick) * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits) PCI: Update PCIEPORTBUS Kconfig help text PCI: Fix "try" semantics of bus and slot reset PCI/LINK: Report degraded links via link bandwidth notification dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 PCI: altera: Enable driver on ARM64 PCI: altera: Add Stratix 10 PCIe support PCI/PME: Fix possible use-after-free on remove PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ...
2019-03-04Merge branch 'spi-5.1' into spi-nextMark Brown30-1141/+4799
2019-03-04Merge branch 'spi-5.0' into spi-linusMark Brown11-76/+91
2019-03-04spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3Geert Uytterhoeven1-1/+7
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support bits-per-word values in the full range 8..32, the variants present in R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32. Obtain the value from family-specific sh_msiof_chipdata to fix this. Reported-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-22spi: sifive: Remove redundant dev_err call in sifive_spi_probe()Wei Yongjun1-1/+0
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-22spi: sifive: Remove spi_master_put in sifive_spi_remove()Wei Yongjun1-1/+0
The call to spi_master_put() in sifive_spi_remove() is redundant since the master is registered using devm_spi_register_master() and no reference hold by using spi_master_get() in sifive_spi_remove(). This is detected by Coccinelle semantic patch. Fixes: 484a9a68d669 ("spi: sifive: Add driver for the SiFive SPI controller") Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-21spi: spi-gpio: fix SPI_CS_HIGH capabilityRussell King1-2/+2
spi-gpio is capable of dealing with active-high chip-selects. Unfortunately, commit 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE support") broke this by setting master->mode_bits, which overrides the setting in the spi-bitbang code. Fix this. [Fixed a trivial conflict with SPI_3WIRE_HIZ support -- broonie] Fixes: 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE support") Signed-off-by: Russell King <[email protected]> Signed-off-by: Mark Brown <[email protected]> Cc: [email protected]
2019-02-20Merge branch 'for-5.0' of ↵Mark Brown10-74/+89
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1
2019-02-20spi: pxa2xx: Setup maximum supported DMA transfer lengthAndy Shevchenko1-0/+1
When the commit b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") switches to SPI core provided DMA helpers, it missed to setup maximum supported DMA transfer length for the controller and thus users mistakenly try to send more data than supported with the following warning: ili9341 spi-PRP0001:01: DMA disabled for transfer length 153600 greater than 65536 Setup maximum supported DMA transfer length in order to make users know the limit. Fixes: b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Mark Brown <[email protected]> Cc: [email protected]
2019-02-19spi: sifive: Add driver for the SiFive SPI controllerYash Shah3-0/+457
Add driver for the SiFive SPI controller on the HiFive Unleashed board. Signed-off-by: Palmer Dabbelt <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Yash Shah <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: Add a prefix for SPI DMA channel macrosBaolin Wang1-21/+21
Add a prefix for SPI DMA channel macros to avoid namespace conflicts, and no functional changes. Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: spi: sprd: Add DMA mode supportLanqing Liu1-3/+290
Add DMA mode support for the Spreadtrum SPI controller, and we will enable SPI interrupt to help to complete the SPI transfer work in DMA mode. Signed-off-by: Lanqing Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: Add the SPI irq function for the SPI DMA modeLanqing Liu1-0/+51
The SPI irq event will use to complete the SPI work in the SPI DMA mode, so this patch is a preparation for the following DMA mode support. Moreover the SPI interrupt can be fired when removing the SPI controller, so we should make sure the SPI controller has stopped the queue in remove function before freeing the SPI irq. Signed-off-by: Lanqing Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-12spi: use gpio[d]_set_value_cansleep for setting chipselect GPIOFelix Fietkau1-2/+3
Sleeping is safe inside spi_transfer_one_message, and some GPIO chips are running on slow busses (such as I2C GPIO expanders) and need to sleep for setting values. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-12spi: gpio: Advertise support for SPI_CS_HIGHJonathan Neuschäfer1-1/+2
The spi-gpio driver already handles different chip select polarities, but so far this was not advertised in master->mode_bits. This patch fixes mmc_spi on top of spi_gpio, which is useful in some testing scenarios. Signed-off-by: Jonathan Neuschäfer <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-08spi: sh-msiof: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+83
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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