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2016-04-25spi: return error if kmap'd buffers passed to spi_map_buf()Vignesh R1-1/+3
Current spi_map_buf() implementation supports creates sg_table for vmalloc'd and kmalloc'd buffers. Therefore return error if kmap'd buffer (or any other buffer) is passed to spi_map_buf(). Signed-off-by: Vignesh R <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-22spi: pic32-sqi: silence array overflow warningDan Carpenter1-1/+1
We read one element beyond the end of the array when we access "rdesc[i + 1]" so it causes a static checker warning. It's harmless because we write over it again on the next line. But let's just silence the warning. Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Purna Chandra Mandal <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-22spi: spi-orion: enable the driver on ARCH_MVEBU platformsThomas Petazzoni1-1/+1
The SPI controller managed by the spi-orion is used on the new ARM64 Marvell Armada 7K/8K SoCs. In order to allow this driver to be built for this platform, we allow it to be selected for ARCH_MVEBU=y configurations. Signed-off-by: Thomas Petazzoni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-20spi: spi-pxa2xx: Remove CLK_IS_ROOTStephen Boyd1-2/+2
This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Daniel Mack <[email protected]> Cc: Haojian Zhuang <[email protected]> Cc: Robert Jarzmik <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-18spi: pic32-sqi: add SPI driver for PIC32 SQI controller.Purna Chandra Mandal3-0/+775
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal <[email protected]> Cc: Mark Brown <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-18spi: bcm53xx: add spi_flash_read callback for MMIO-based readsRafał Miłecki1-2/+76
This implements more efficient reads of SPI-attached flash content. Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-18spi: cadence: mark pm functions __maybe_unusedArnd Bergmann1-2/+2
The newly added runtime PM support for the cadence spi driver causes harmless warnings when PM is disabled: drivers/spi/spi-cadence.c:681:12: warning: 'cnds_runtime_suspend' defined but not used drivers/spi/spi-cadence.c:652:12: warning: 'cnds_runtime_resume' defined but not used This adds __maybe_unused annotations to the respective functions to shut up the warnings, while leaving the code in place for compile testing and avoiding ugly #ifdefs. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-15spi: dln2: Pass of_node to spi masterCrestez Dan Leonard1-0/+3
This allows defining SPI devices connected to a DLN2 using devicetree. This already works for i2c because of a similar patch: 3b10db23: i2c: dln2: set the device tree node of the adapter Signed-off-by: Crestez Dan Leonard <[email protected]> Acked-by: Laurentiu Palcu <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-13dmaengine: dw: rename masters to reflect actual topologyAndy Shevchenko1-4/+4
The source and destination masters are reflecting buses or their layers to where the different devices can be connected. The patch changes the master names to reflect which one is related to which independently on the transfer direction. The outcome of the change is that the memory data width is now always limited by a data width of the master which is dedicated to communicate to memory. The patch will not break anything since all current users have the same data width for all masters. Though it would be nice to revisit avr32 platforms to check what is the actual hardware topology in use there. It seems that it has one bus and two masters on it as stated by Table 8-2, that's why everything works independently on the master in use. The purpose of the sequential patch is to fix the driver for configuration of more than one bus. The change is done in the assumption that src_master and dst_master are reflecting a connection to the memory and peripheral correspondently on avr32 and otherwise on the rest. Acked-by: Hans-Christian Egtvedt <[email protected]> Acked-by: Mark Brown <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2016-04-13spi: spi-ti-qspi: Handle truncated frames properlyBen Hutchings1-12/+20
We clamp frame_len_words to a maximum of 4096, but do not actually limit the number of words written or read through the DATA registers or the length added to spi_message::actual_length. This results in silent data corruption for commands longer than this maximum. Recalculate the length of each transfer, taking frame_len_words into account. Use this length in qspi_{read,write}_msg(), and to increment spi_message::actual_length. Signed-off-by: Ben Hutchings <[email protected]> Signed-off-by: Mark Brown <[email protected]> Cc: [email protected]
2016-04-13spi: spi-ti-qspi: Fix FLEN and WLEN settings if bits_per_word is overriddenBen Hutchings1-6/+9
Each transfer can specify 8, 16 or 32 bits per word independently of the default for the device being addressed. However, currently we calculate the number of words in the frame assuming that the word size is the device default. If multiple transfers in the same message have differing bits_per_word, we bitwise-or the different values in the WLEN register field. Fix both of these. Also rename 'frame_length' to 'frame_len_words' to make clear that it's not a byte count like spi_message::frame_length. Signed-off-by: Ben Hutchings <[email protected]> Signed-off-by: Mark Brown <[email protected]> Cc: [email protected]
2016-04-12spi: let SPI masters ignore their children for PMLinus Walleij1-0/+1
Let all SPI masters ignore their children: when it comes to power management: SPI children have no business doing keeping their parents awake: they are completely autonomous devices that just use their parent to talk, and the latter usecase must be power managed by the host itself on a per-message basis. Reviewed-by: Ulf Hansson <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-12spi: omap2-mcspi: Undo broken fix for dma transfer of vmalloced bufferAkinobu Mita1-17/+45
This reverts commit 3525e0aac91c4de5d20b1f22a6c6e2b39db3cc96. The DMA transfer for RX buffer was not handled correctly in this change. The actual transfer length for DMA RX can be less than xfer->len in the specific condition and the last words will be filled after the DMA completion, but the commit doesn't consider it and the dmaengine is started with rx_sg mapped by spi core. The solution for this at least requires more lines than this commit has inserted. So revert it for now. Signed-off-by: Akinobu Mita <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-06spi: cadence: Fix some checkpatch warningsShubhrajyoti Datta1-2/+4
No functional change. Fixing some style related issues CHECK: multiple assignments should be avoided + new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); CHECK: Alignment should match open parenthesis +static void cdns_spi_config_clock_freq(struct spi_device *spi, + struct spi_transfer *transfer) CHECK: Please use a blank line after function/struct/union/enum declarations +} +static int cdns_prepare_message(struct spi_master *master, Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: spi-fsl-dspi: Fix cs_change handling in message transferAndrey Vostrikov1-2/+2
There are use cases when chip select should be triggered between transfers in single SPI message. Current implementation does this only on last transfer in message ignoring cs_change value provided in current transfer. Signed-off-by: Andrey Vostrikov <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Return the error code for cdns_spi_suspend and cdns_spi_resumeShubhrajyoti Datta1-7/+3
Return the error code for cdns_spi_suspend and cdns_spi_resume. Also fixes a comment where which claims that the error code is returned. Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Remove the clock enable and disable from suspend and resumeShubhrajyoti Datta1-19/+0
Now that the clocks are enabled and disabled per transaction , remove the clock enable and disable from resume and suspend hooks. Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Runtime pm adaptationShubhrajyoti Datta1-2/+68
Currently the clocks are enabled at probe and disabled at remove. This patch moves the clock enable to the start of transaction and disables at the end. Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadance: Fix the DocumentationShubhrajyoti Datta1-1/+1
cdns_spi_chipselect has parameter is_high however the comment describes it as is_on. Also fixes the below warning. drivers/spi/spi-cadence.c:182: warning: No description found for parameter 'is_high' drivers/spi/spi-cadence.c:182: warning: Excess function parameter 'is_on' description in 'cdns_spi_chipselect' Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Fix probe error handlingShubhrajyoti Datta1-2/+2
The clock disabling is missed out in some error cases at probe. Fix the same. Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Remove _MASK and _OFFSET suffixShubhrajyoti Datta1-87/+74
Remove the _MASK and _OFFSET from the macros. It improves readability, removes some checkpatch error for exceeding 80 chars and also prevents some linebreaks. Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-05spi: cadence: Fix a check patch warningShubhrajyoti Datta1-1/+1
CHECK: Comparison to NULL could be written "!master" + if (master == NULL) Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-04-04Merge remote-tracking branches 'spi/fix/omap2' and 'spi/fix/rockchip' into ↵Mark Brown2-51/+27
spi-linus
2016-04-04Merge remote-tracking branch 'spi/fix/imx' into spi-linusMark Brown1-2/+14
2016-04-04Merge remote-tracking branch 'spi/fix/core' into spi-linusMark Brown1-2/+2
2016-04-04spi: spi-pic32: Add PIC32 SPI master driverPurna Chandra Mandal3-0/+895
The PIC32 SPI driver is capable of performing SPI transfers using PIO or external DMA engine. GPIO controlled /CS support is made default in the driver for correct operation of the controller. This can be enabled by adding "cs-gpios" property of the SPI node in board dts file. Signed-off-by: Purna Chandra Mandal <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-31spi: rockchip: fix probe deferral handlingShawn Lin1-5/+9
Use dma_request_chan instead of dma_request_slave_channel, in this case we can check EPROBE_DEFER without static warning. Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Shawn Lin <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi: pxa2xx: Fix cs_change managementChristophe Ricard1-3/+2
Fix cs_change management so that it is in line with other spi drivers. In the spi core api helpers such as spi_bus_lock/unlock and spi_sync_locked or cs_change field in spi_transfer help to manage chip select from the device driver. The driver was setting the chip select to idle if the message queue was empty despite cs_change or other status field set by spi_bus_lock/unlock or spi_sync_locked. Signed-off-by: Christophe Ricard <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi/fsl-espi: avoid infinite loops on fsl_espi_cpu_irq()Nobuteru Hayashi1-1/+9
It brought nearly infinite loops, and was possible to be occurred only if the SPI transaction total size are not alighed with 4. Loops are here at while (tmp--), tmp is unsigned, and set it with minus value. The loops are executed as a result of unexpected RX interrupt occurrence after that. This interrupt may be hardware eratta and is not fixed. Fix mspi->len from minus value to 0 and print warning message. Signed-off-by: Nobuteru Hayashi <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi/fsl-espi: Don't wait transaction completion foreverNobuteru Hayashi1-1/+6
Because the eSPI driver uses wait_for_completion(), any stuck-able phenomenon at half-way transaction progress made worker task hang up. This phenomenon is perhaps caused by eSPI device errata which seems not to be published from vendor site yet. Anyway, we fix hang task by using fixed 2 seconds timeout that is our preferred value for eSPI maximum transaction size. It seems to be better that eSPI driver can detect this stuck and report error (EMSGSIZE) to the upper device driver because the upper device driver can decide to retry or recover. Signed-off-by: Nobuteru Hayashi <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi/fsl-espi: Don't spin forever on SPIE_RXCNTNobuteru Hayashi1-3/+10
Infinite loop on SPIE_RXCNT occurred. while (SPIE_RXCNT(events) < min(4, mspi->len)) { cpu_relax(); events = mpc8xxx_spi_read_reg(&reg_base->event); } We met a soft lockup at fsl_espi_cpu_irq() because of this. Fix it by using spin_event_timeout() so that fsl_espi_cpu_irq() can break loop with timeouts dmesg. Signed-off-by: Nobuteru Hayashi <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi: pxa2xx: Use dummy buffers provided by SPI coreJarkko Nikula3-10/+2
Dummy buffer is used for half duplex transfers that don't have TX or RX buffer set. Instead of own dummy buffer management here let the SPI core to handle it by setting the SPI_MASTER_MUST_RX and SPI_MASTER_MUST_TX flags. Then core makes sure both transfer buffers are set. Signed-off-by: Jarkko Nikula <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi: pxa2xx: Remove rx_/tx_map_len members from struct driver_dataJarkko Nikula2-7/+0
spi-pxa2xx-dma.c DMA engine implementation stopped using PIO for unaligned trailing bytes in the commit 111e0a9dc71e ("spi/pxa2xx: Prevent DMA from transferring too many bytes"). This means there is no need to update tx/rx transfer buffer pointers after DMA completion. These buffer pointers will be set to new buffers when handling the next transfer. Because this buffer pointer update was only remaining use for rx_map_len and tx_map_len members in struct driver_data after removing the legacy PXA DMA implementation they can be removed now. Signed-off-by: Jarkko Nikula <[email protected]> Acked-by: Robert Jarzmik <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-28spi: pxa2xx: handle error of pxa2xx_spi_dma_prepare()Andy Shevchenko2-3/+18
If by some reason pxa2xx_spi_dma_prepare() fails we have not to ignore its error. In such case we abort the transfer and return the error to upper level. Signed-off-by: Andy Shevchenko <[email protected]> [Jarkko: Avoid leaking TX descriptors in case RX descriptor allocation fails. Noted by Robert Jarzmik <[email protected]>. Unmap also buffers in case of failure.] Signed-off-by: Jarkko Nikula <[email protected]> Acked-by: Robert Jarzmik <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-23spi: fsl-dspi: Set max_speed_hz for masterBhuvanchandra DV1-0/+7
Calculate and update max speed from bus clock for SoCs using DSPI IP. The bus clock factor's are taken from the data sheets of respective SoCs. Signed-off-by: Bhuvanchandra DV <[email protected]> Acked-by: Stefan Agner <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-23spi: omap2-mcspi: fix dma transfer for vmalloced bufferAkinobu Mita1-45/+17
Currently omap2-mcspi cannot handle dma transfer for vmalloced buffer. I hit this problem when using mtdblock on spi-nor. This lets the SPI core handle the page mapping for dma transfer buffer. Signed-off-by: Akinobu Mita <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-23spi: xlp: Enable SPI driver for Broadcom Vulcan ARM64Kamlakant Patel1-1/+1
- Vulcan spi controller is compatible with netlogic,xlp832-spi. - Add depends on ARCH_VULCAN to Kconfig to enable spi controller driver for Broadcom Vulcan ARM64 SoCs. Signed-off-by: Kamlakant Patel <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-21spi: octeon: Convert to use devm_ioremap_resourceAxel Lin1-11/+6
Signed-off-by: Axel Lin <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-18spi: fix possible deadlock between internal bus locks and bus_lock_flagHeiko Stübner1-2/+2
External users may use spi_bus_lock to get exclusive access. This will also grab the bus_lock_mutex and may therefore result in a deadlock if __spi_pump_messages also tries to get the mutex. Therefore adapt spi_pump_messages as well as spi_sync to preset the bus_locked parameter according to the master->bus_lock_flag. Fixes: 49023d2e4ead ("spi: core: Fix deadlock when sending messages") Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-17Merge tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-2/+10
Pull dmaengine updates from Vinod Koul: "This is smallish update with minor changes to core and new driver and usual updates. Nothing super exciting here.. - We have made slave address as physical to enable driver to do the mapping. - We now expose the maxburst for slave dma as new capability so clients can know this and program accordingly - addition of device synchronize callbacks on omap and edma. - pl330 updates to support DMAFLUSHP for Rockchip platforms. - Updates and improved sg handling in Xilinx VDMA driver. - New hidma qualcomm dma driver, though some bits are still in progress" * tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits) dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platforms dmaengine: add Qualcomm Technologies HIDMA channel driver dmaengine: add Qualcomm Technologies HIDMA management driver dmaengine: hidma: Add Device Tree binding dmaengine: qcom_bam_dma: move to qcom directory dmaengine: tegra: Move of_device_id table near to its user dmaengine: xilinx_vdma: Remove unnecessary variable initializations dmaengine: sirf: use __maybe_unused to hide pm functions dmaengine: rcar-dmac: clear pertinence number of channels dmaengine: sh: shdmac: don't open code of_device_get_match_data() dmaengine: tegra: don't open code of_device_get_match_data() dmaengine: qcom_bam_dma: Make driver work for BE dmaengine: sun4i: support module autoloading dma/mic_x100_dma: IS_ERR() vs PTR_ERR() typo dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's dmaengine: xilinx_vdma: Simplify spin lock handling dmaengine: xilinx_vdma: Fix issues with non-parking mode dmaengine: xilinx_vdma: Improve SG engine handling dmaengine: pl330: fix to support the burst mode dmaengine: make slave address physical ...
2016-03-17spi: imx: Fix possible NULL pointer derefSascha Hauer1-1/+5
transfer could be NULL in spi_imx_can_dma() when it's called from spi_imx_setupxfer() with a NULL transfer. Test for a NULL pointer before dereferencing it. Signed-off-by: Sascha Hauer <[email protected]> Cc: Dan Carpenter <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-17spi: imx: only do necessary changes to ECSPIx_CONFIGREGKnut Wohlrab1-1/+9
If the SPI chip select (CS) for a dedicated channel is done manually by the used higher device driver, the CS may be active while writing to ECSPIx_CONFIGREG. To prevent unwanted clock edges when selecting the clock mode, only do the necessary changes to the i.MX SPI configuration register and leave not selected channels untouched. To prevent unwanted clock edges on first use, an empty dummy transmission shall be done by the initialization procedure of the device driver of this channel. This will set the clock mode to the correct state. Signed-off-by: Knut Wohlrab <[email protected]> Signed-off-by: Dirk Behme <[email protected]> Acked-by: Sascha Hauer <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-15spi: rockchip: Spelling s/divsor/divisor/Geert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2016-03-11Merge remote-tracking branches 'spi/topic/res', 'spi/topic/rockchip', ↵Mark Brown3-53/+148
'spi/topic/sh', 'spi/topic/ti-qspi' and 'spi/topic/xilinx' into spi-next
2016-03-11Merge remote-tracking branches 'spi/topic/lp8841', 'spi/topic/msg', ↵Mark Brown9-96/+730
'spi/topic/pl022' and 'spi/topic/pxa2xx' into spi-next
2016-03-11Merge remote-tracking branches 'spi/topic/doc', 'spi/topic/dw' and ↵Mark Brown3-19/+19
'spi/topic/flash' into spi-next
2016-03-11Merge remote-tracking branches 'spi/topic/acpi', 'spi/topic/axi-engine', ↵Mark Brown6-63/+701
'spi/topic/bcm2835' and 'spi/topic/bcm2835aux' into spi-next
2016-03-11Merge remote-tracking branch 'spi/topic/imx' into spi-nextMark Brown1-158/+183
2016-03-11Merge remote-tracking branch 'spi/topic/dma' into spi-nextMark Brown1-3/+3
2016-03-11Merge remote-tracking branch 'spi/topic/core' into spi-nextMark Brown1-0/+48
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