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spi: Provide SPI_CS_WORD
This provides a SPI operation mode which changes chip select after every
word, used by some devices such as ADCs and DACs.
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This adds a default software implementation for the SPI_CS_WORD flag for
controllers that don't have such a feature.
The SPI_CS_WORD flag indicates that the CS line should be toggled
between each word sent, not just between each transfer. The
implementation works by using existing functions to split transfers into
one-word-sized transfers and sets the cs_change bit for each of the
new transfers.
Signed-off-by: David Lechner <[email protected]>
Acked-by: Jonathan Cameron <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Mark writes:
"spi: Fixes for v4.19
As well as one driver fix there's a couple of fixes here which address
issues with the use of IDRs for allocation of dynamic bus numbers,
ensuring that dynamic bus numbers interact well with static bus numbers
assigned via DT and otherwise."
* tag 'spi-fix-v4.19-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi-fsl-dspi: fix broken DSPI_EOQ_MODE
spi: Fix double IDR allocation with DT aliases
spi: fix IDR collision on systems with both fixed and dynamic SPI bus numbers
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Almost all spi drivers assign spi master->dev.of_node from
its parent platform device without additional refcounting.
It seems of_node_get() in pic32_sqi_probe() is unnecessary
and there is no corresponding of_node_put().
Found by Linux Driver Verification project (linuxtesting.org)
Signed-off-by: Alexey Khoroshilov <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/spi/spi-davinci.c: In function 'davinci_spi_setup':
drivers/spi/spi-davinci.c:422:36: warning:
variable 'pdata' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The DaVinci SPI can use either:
- Internal chip selects (inside the SPI host)
- External chip selects (using GPIO)
- External chip selects passed in pdata
The last way of passing external chip selects through
platform data is not used in the kernel. Delete it to make
the code simpler when refactoring GPIO.
Cc: Sekhar Nori <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Michele Dionisio <[email protected]>
Cc: Frode Isaksen <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Suggested-by: Radu Nicolae Pirea <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
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We need that to adjust the len of the 2nd transfer (called data in
spi-mem) if it's too long to fit in a SPI message or SPI transfer.
Fixes: c36ff266dc82 ("spi: Extend the core to ease integration of SPI memory controllers")
Cc: <[email protected]>
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This is the driver for at91-usart in spi mode. The USART IP can be configured
to work in many modes and one of them is SPI.
The driver was tested on sama5d3-xplained and sama5d4-xplained boards with
enc28j60 ethernet controller as slave.
Signed-off-by: Radu Pirea <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviwed-by: Mark Brown <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
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There is a logical problem in spi-gpio with host just
assigning a MOSI line and no MISO: this is interpreted
as the host cannot do RX and the host is flagged with
SPI_MASTER_NO_RX.
This is wrong: since GPIO lines can switch direction,
in 3WIRE operation the host will simply reverse the
direction of the GPIO line and start reading from it,
there is even code for doing this in the driver, but
it went unnoticed because it was tested by using a
master with 4 wires but a device using just 3 wires.
Remove the offending flag.
Cc: Andrzej Hajda <[email protected]>
Cc: Lorenzo Bianconi <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Almost all spi drivers assign spi master->dev.of_node from
its parent platform device without additional refcounting.
It seems of_node_get() in pic32_spi_probe() is unnecessary
and there is no corresponding of_node_put().
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/spi/spi-pl022.c: In function 'do_polling_transfer':
drivers/spi/spi-pl022.c:1493:20: warning:
variable 'chip' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/spi/spi-gpio.c: In function 'spi_gpio_remove':
drivers/spi/spi-gpio.c:450:33: warning:
variable 'pdata' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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When interrupted, wait_event_interruptible_timeout() returns
-ERESTARTSYS, and the SPI transfer in progress will fail, as expected:
m25p80 spi0.0: SPI transfer failed: -512
spi_master spi0: failed to transfer one message from queue
However, as the underlying DMA transfers may not have completed, all
subsequent SPI transfers may start to fail:
spi_master spi0: receive timeout
qspi_transfer_out_in() returned -110
m25p80 spi0.0: SPI transfer failed: -110
spi_master spi0: failed to transfer one message from queue
Fix this by calling dmaengine_terminate_all() not only for timeouts, but
also for errors.
This can be reproduced on r8a7991/koelsch, using "hd /dev/mtd0" followed
by CTRL-C.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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If the SPI queue is running during system suspend, the system may lock
up.
Fix this by stopping/restarting the queue during system suspend/resume,
by calling spi_master_suspend()/spi_master_resume() from the PM
callbacks. In-kernel users will receive an -ESHUTDOWN error while
system suspend/resume is in progress.
Based on a patch for sh-msiof by Gaku Inami.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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This patch changes writing to the SISTR register according to the H/W
user's manual.
The TDREQ bit and RDREQ bits of SISTR are read-only, and must be written
their initial values of zero.
Signed-off-by: Hiromitsu Yamasaki <[email protected]>
[geert: reword]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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If the SPI queue is running during system suspend, the system may lock
up.
Fix this by stopping/restarting the queue during system suspend/resume
by calling spi_master_suspend()/spi_master_resume() from the PM
callbacks. In-kernel users will receive an -ESHUTDOWN error while
system suspend/resume is in progress.
Signed-off-by: Gaku Inami <[email protected]>
Signed-off-by: Hiromitsu Yamasaki <[email protected]>
[geert: Cleanup, reword]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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spi_controller_{suspend,resume}() already prints an error message on
failure, so there is no need to repeat this in individual drivers.
Note: spi_master_{suspend,resume}() is an alias for
spi_controller_{suspend,resume}().
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Alexandre Belloni <[email protected]>
Reviewed-by: Daniel Mack <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This fixes an embarrassing copy-and-paste error in the
errorpath of spi_gpio_request(): we were checking the wrong
struct member for error code right after retrieveing the
sck GPIO.
Fixes: 9b00bc7b901ff672 ("spi: spi-gpio: Rewrite to use GPIO descriptors")
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This change increases the source code readability.
Instead of using `spi->child[cs].direct_access.XXX` use `dir_acc->XXX`.
Instead of using `orion_spi->child[cs].direct_access.vaddr` use `vaddr`.
Signed-off-by: Kosta Zertsekel <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Jan Kundrát <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Depending on the SPI instance one may get an interrupt storm upon
requesting resp. interrupt unless the clock is explicitly enabled
beforehand. This has been observed trying to bring up instance 4 on
T20.
Signed-off-by: Marcel Ziswiler <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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Define a mask for the IF_SI_OWNER field.
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/spi/spi-davinci.c: In function 'davinci_spi_chipselect':
drivers/spi/spi-davinci.c:211:36: warning:
variable 'pdata' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Unfortunately, the Jaguar2 CPU_SYSTEM_CTRL register set has a different
layout than the Ocelot one. Handle that while keeping most of the code
common.
Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This patch adds the SPI controller driver for Spreadtrum SC9860 platform.
Signed-off-by: Lanqing Liu <[email protected]>
Signed-off-by: Baolin Wang <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This patch fixes the dspi_eoq_write function used by the
ColdFire mcf5441x family. The 16 bit cmd part must be re-set at
each data transfer.
Also, now that fifo_size variables are used for eoq_read/write,
a proper fifo size must be set (16 slots for the ColdFire dspi
module version).
Signed-off-by: Angelo Dureghello <[email protected]>
Acked-by: Esben Haabendal <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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If the SPI bus number is provided by a DT alias, idr_alloc() is called
twice, leading to:
WARNING: CPU: 1 PID: 1 at drivers/spi/spi.c:2179 spi_register_controller+0x11c/0x5d8
couldn't get idr
Fix this by moving the handling of fixed SPI bus numbers up, before the
DT handling code fills in ctlr->bus_num.
Fixes: 1a4327fbf4554d5b ("spi: fix IDR collision on systems with both fixed and dynamic SPI bus numbers")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Pull hwspinlock updates from Bjorn Andersson:
"This introduces devres helpers and an API to request a lock by name,
then migrates the sprd SPI driver to use these"
* tag 'hwlock-v4.19' of git://github.com/andersson/remoteproc:
hwspinlock: Fix incorrect return pointers
spi: sprd: Change to use devm_hwspin_lock_request_specific()
spi: sprd: Replace of_hwspin_lock_get_id() with of_hwspin_lock_get_id_byname()
hwspinlock: Fix one comment mistake
hwspinlock: Remove redundant config
hwspinlock: Add devm_xxx() APIs to register/unregister one hwlock controller
hwspinlock: Add devm_xxx() APIs to request/free hwlock
hwspinlock: Add one new API to support getting a specific hwlock by the name
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On systems where some controllers get a dynamic ID assigned and some have
a fixed number (e.g. from ACPI tables), the current implementation might
run into an IDR collision: in case of a fixed bus number is gotten by a
driver (but not marked busy in IDR tree) and a driver with dynamic bus
number gets the same ID and predictably fails.
Fix this by means of checking-in fixed IDsin IDR as far as dynamic ones
at the moment of the controller registration.
Fixes: 9b61e302210e (spi: Pick spi bus number from Linux idr or spi alias)
Signed-off-by: Kirill Kapranov <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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On non-OF systems spi->controlled_data may be NULL. This causes a NULL
pointer derefence on dm365-evm.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
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When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility with the old drivers naming scheme, a name
field is added to struct spi_mem and a hook is added to let controller
drivers set a custom name for the memory device.
Example for the FSL QSPI driver:
Name with the old driver: 21e0000.qspi,
or with multiple devices: 21e0000.qspi-0, 21e0000.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Suggested-by: Boris Brezillon <[email protected]>
Signed-off-by: Frieder Schrempf <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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This commit removed include headers of linux/of.h and linux/of_platform.h,
because they are not used.
Signed-off-by: Keiji Hayashibara <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add SPI_3WIRE support to spi-gpio controller introducing
set_line_direction function pointer in spi_bitbang data structure.
Spi-gpio controller has been tested using hts221 temp/rh iio sensor
running in 3wire mode and lsm6dsm running in 4wire mode
Signed-off-by: Lorenzo Bianconi <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add the capability to specify the flag parameter used in
bitbang_txrx_be_cpha{0,1} through the txrx_word function pointers of
spi_bitbang data structure. That feature will be used to add spi-3wire
support to the spi-gpio controller
Signed-off-by: Lorenzo Bianconi <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Add SPI controller driver implemented in Socionext UniPhier SoCs.
UniPhier SoCs have two types SPI controllers; SCSSI supports a
single channel, and MCSSI supports multiple channels.
This driver supports SCSSI only.
This controller has 32bit TX/RX FIFO with depth of eight entry,
and supports the SPI master mode only.
This commit is implemented in PIO transfer mode, not DMA transfer.
Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Keiji Hayashibara <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Even if the chip select line is not controlled by the SPFI
hardware, the device select bits need to be set to specify
the chip select line in use for the hardware to know what
parameters to use for the current transfer.
Signed-off-by: Ionela Voinescu <[email protected]>
Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Variable count, l, mcspi and spi_cntrl are being assigned but are
never used hence they are redundant and can be removed.
Cleans up clang warnings:
warning: variable 'count' set but not used [-Wunused-but-set-variable]
warning: variable 'l' set but not used [-Wunused-but-set-variable]
warning: variable 'mcspi' set but not used [-Wunused-but-set-variable]
warning: variable 'spi_cntrl' set but not used [-Wunused-but-set-variable]
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Because the SPI controller deasserts the chip select when the TX fifo is
empty (which may happen in the middle of a transfer), the CS should be
handled by linux. Unfortunately, some or all of the first four chip
selects are not muxable as GPIOs, depending on the SoC.
There is a way to bitbang those pins by using the SPI boot controller so
use it to set the chip selects.
At init time, it is also necessary to give control of the SPI interface to
the Designware IP.
Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Export dw_spi_set_cs so it can be used from the various IP integration
modules.
Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Log RX and TX fifo counters when a transfer is done and these are not
zero.
Signed-off-by: Tiago Brusamarello <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Dynamic burst mode allows to group together multiple words and send them
in one continuous burst. When the number of bytes to be sent is not a
strict multiple of the FIFO entry size (32 bits), the controller expects
the non aligned bits to be sent first.
This commit adds support for this particular constraint, avoiding the
need to send the non-aligned bytes one by one at the end of the
transfer, speeding-up transfer speed in that case.
With this method, a transfer is divided into multiple bursts, limited in
size by the maximum amount of data that the controller can transfer in
one continuous burst (which is 512 bytes).
The non-512 byte part of the transfer is sent first. The remaining bytes
to be transferred in the current burst is stored in the 'remainder'
field.
With this method, the read_u32 field is no longer necessary, and is
removed.
This was tested on imx6 solo and imx6 quad.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The spi_imx_can_dma function computes the watermark level so that
the transfer will fit in exactly N bursts (without a remainder).
The smallest watermark level possible being one FIFO entry per burst, we
can't never have a case where the transfer size isn't divsiible by 1.
Remove the extra check for the wml being different than 0.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The SPI core enforces that we always use the next power-of-two number of
bytes to store words. As a result, a 24 bits word will be stored in 4
bytes.
This commit fixes the spi_imx_bytes_per_word function to return the
correct number of bytes.
This also allows to get rid of unnecessary checks in the can_dma
function, since the SPI core validates that we always have a transfer
length that is a multiple of the number of bytes per word.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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The dynamic bursts mode allows to group together multiple words into a
single burst. To do so, it's necessary that words can be packed into the
32-bits FIFO entries, so we can't allow using this mode with bit_per_words
different to 8, 16 or 32.
This prevents shitfing out extra clock ticks for transfers with
bit_per_word values not aligned on 8 bits.
With that , we are sure that only the correct number of bits is
shifted out at each transfer, so we don't need to mask out the remaining
parts of the words.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Some fields in struct spi_imx_data are assigned a different value twice
in a row, in spi_imx_setupxfer.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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