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2020-09-17spi: fsi: Fix use of the bneq+ sequencer instructionBrad Bishop1-3/+25
All of the switches in N2_count_control in the counter configuration are required to make the branch if not equal and increment command work. Set them when using bneq+. A side effect of this mode requires a dummy write to TDR when both transmitting and receiving otherwise the controller won't start shifting receive data. It is likely not possible to avoid TDR underrun errors in this mode and they are harmless, so do not check for them. Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Brad Bishop <[email protected]> Signed-off-by: Eddie James <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-17spi: fsi: Fix clock running too fastBrad Bishop1-1/+1
Use a clock divider tuned to a 200MHz FSI bus frequency (the maximum). Use of the previous divider at 200MHz results in corrupt data from endpoint devices. Ideally the clock divider would be calculated from the FSI clock, but that would require some significant work on the FSI driver. With FSI frequencies slower than 200MHz, the SPI clock will simply run slower, but safely. Signed-off-by: Brad Bishop <[email protected]> Signed-off-by: Eddie James <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-17spi: fsi: Handle 9 to 15 byte transfers lengthsBrad Bishop1-3/+3
The trailing <len> - 8 bytes of transfer data in this size range is no longer ignored. Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Brad Bishop <[email protected]> Signed-off-by: Eddie James <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-15spi: bcm2835: Make polling_limit_us staticJason Yan1-1/+1
This eliminates the following sparse warning: drivers/spi/spi-bcm2835.c:78:14: warning: symbol 'polling_limit_us' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: sprd: Simplify with dev_err_probe()Krzysztof Kozlowski2-16/+6
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chunyan Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: spi-geni-qcom: Don't wait to start 1st transfer if transmittingDouglas Anderson1-81/+86
If we're sending bytes over SPI, we know the FIFO is empty at the start of the transfer. There's no reason to wait for the interrupt telling us to start--we can just start right away. Then if we transmit everything in one swell foop we don't even need to bother listening for TX interrupts. In a test of "flashrom -p ec -r /tmp/foo.bin" interrupts were reduced from ~30560 to ~29730, about a 3% savings. This patch looks bigger than it is because I moved a few functions rather than adding a forward declaration. The only actual change to geni_spi_handle_tx() was to make it return a bool indicating if there is more to tx. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Akash Asthana <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20200912111716.1.Ied5e843fad0d6b733a1fb8bcfb364dd2fa889eb3@changeid Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: bcm2835: Make polling_limit_us staticJason Yan1-1/+1
This eliminates the following sparse warning: drivers/spi/spi-bcm2835.c:78:14: warning: symbol 'polling_limit_us' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: spi-fsl-dspi: use XSPI mode instead of DMA for DPAA2 SoCsVladimir Oltean1-3/+3
The arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi device tree lacks DMA channels for DSPI, so naturally, the driver fails to probe: [ 2.945302] fsl-dspi 2100000.spi: rx dma channel not available [ 2.951134] fsl-dspi 2100000.spi: can't get dma channels In retrospect, this should have been obvious, because LS2080A, LS2085A LS2088A and LX2160A don't appear to have an eDMA module at all. Looking again at their datasheets, the CTARE register (which is specific to XSPI functionality) seems to be documented, so switch them to XSPI mode instead. Fixes: 0feaf8f5afe0 ("spi: spi-fsl-dspi: Convert the instantiations that support it to DMA") Reported-by: Qiang Zhao <[email protected]> Tested-by: Qiang Zhao <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: spi-geni-qcom: Don't program CS_TOGGLE again and againDouglas Anderson1-5/+7
We always toggle the chip select manually in spi-geni-qcom so that we can properly implement the Linux API. There's no reason to program this to the hardware on every transfer. Program it once at init and be done with it. This saves some part of a microsecond of overhead on each transfer. While not really noticeable on any real world benchmarks, we might as well save the time. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20200912140730.2.I33e571179986850b4ec17042e813d0b08fb1b9c1@changeid Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: spi-geni-qcom: Use the FIFO even moreDouglas Anderson1-1/+1
In commit 902481a78ee4 ("spi: spi-geni-qcom: Actually use our FIFO") I explained that the maximum size we could program the FIFO was "mas->tx_fifo_depth - 3" but that I chose "mas->tx_fifo_depth()" because I was worried about decreased bandwidth. Since that time: * All the interconnect patches have landed, making things run at the proper speed. * I've done more measurements. This lets me confirm that there's really no downside of using the FIFO more. Specifically I did "flashrom -p ec -r /tmp/foo.bin" on a Chromebook and averaged over several runs. Before: It took 6.66 seconds and 59669 interrupts fired. After: It took 6.66 seconds and 47992 interrupts fired. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20200912140730.1.Ie67fa32009b94702d56232c064f1d89065ee8836@changeid Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: spi-qcom-qspi: replace spin_lock_irqsave by spin_lock in hard IRQBarry Song1-3/+2
It is redundant to do irqsave and irqrestore in hardIRQ context. Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Signed-off-by: Barry Song <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: bcm-qspi: Clean up 7425, 7429, and 7435 settingsRay Jui1-12/+0
The Broadcom QSPI driver now falls back to no MSPI_DEV support as the default setting in the generic compatible string, explicit settings for STB chips 7425, 7429, and 7435 can be removed. Signed-off-by: Ray Jui <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: bcm-qspi: Fix probe regression on iProc platformsRay Jui1-1/+1
iProc chips have QSPI controller that does not have the MSPI_REV offset. Reading from that offset will cause a bus error. Fix it by having MSPI_REV query disabled in the generic compatible string. Fixes: 3a01f04d74ef ("spi: bcm-qspi: Handle lack of MSPI_REV offset") Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#u Signed-off-by: Ray Jui <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: bcm-qspi: Add compatible string for BRCMSTB 7445 SoCsRay Jui1-0/+5
Add compatible string for BRCMSTB 7445 SoCs and indicate it has MSPI rev support. Signed-off-by: Ray Jui <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-14spi: qup: remove redundant assignment to variable retColin Ian King1-1/+1
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-13Merge tag 'samsung-soc-s3c-5.10' of ↵Olof Johansson6-162/+46
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc Samsung S3C24xx and S3C64xx machine code cleanup for v5.10 Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it also touches files shared with S5Pv210 and Exynos. This is mostly Arnd Bergmann work which Krzysztof Kozlowski took over, rebased and polished. The goal is to cleanup, merge and finally make the Samsung S3C24xx and S3C64xx architectures multiplatform. The multiplatform did not happen yet here - just cleaning up and merging into one arch/arm/mach-s3c directory. However this is step forward for multiplatform or at least to keep this code still maintainable. This pulls also branch with changes for Samsung SoC sound drivers from broonie/sound because the cleanups there were part of this series and all further patches depend on them. * tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (62 commits) ARM: s3c: Avoid naming clash of S3C24xx and S3C64xx timer setup ARM: s3c: Cleanup from old plat-samsung include ARM: s3c: make headers local if possible ARM: s3c: move into a common directory ARM: s3c24xx: stop including mach/hardware.h from mach/io.h cpufreq: s3c24xx: move low-level clk reg access into platform code cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh ARM: s3c: remove cpufreq header dependencies cpufreq: s3c24xx: split out registers fbdev: s3c2410fb: remove mach header dependency ARM: s3c24xx: bast: avoid irq_desc array usage ARM: s3c24xx: spi: avoid hardcoding fiq number in driver ARM: s3c24xx: include mach/irqs.h where needed ARM: s3c24xx: move s3cmci pinctrl handling into board files ARM: s3c24xx: move iis pinctrl config into boards ARM: s3c24xx: move spi fiq handler into platform ARM: s3c: adc: move header to linux/soc/samsung ARM: s3c24xx: move irqchip driver back into platform ARM: s3c24xx: move regs-spi.h into spi driver ARM: s3c64xx: remove mach/hardware.h ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-09-11Merge tag 'spi-fix-v5.9-rc4' of ↵Linus Torvalds4-8/+28
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "There's some driver specific fixes here plus one core fix for memory leaks that could be triggered by a potential race condition when cleaning up after we have split transfers to fit into what the controller can support" * tag 'spi-fix-v5.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: stm32: fix pm_runtime_get_sync() error checking spi: Fix memory leak on splited transfers spi: spi-cadence-quadspi: Fix mapping of buffers for DMA reads spi: stm32: Rate-limit the 'Communication suspended' message spi: spi-loopback-test: Fix out-of-bounds read spi: spi-cadence-quadspi: Populate get_name() interface MAINTAINERS: add myself as maintainer for spi-fsl-dspi driver
2020-09-11spi: spi-fsl-dspi: use XSPI mode instead of DMA for DPAA2 SoCsVladimir Oltean1-3/+3
The arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi device tree lacks DMA channels for DSPI, so naturally, the driver fails to probe: [ 2.945302] fsl-dspi 2100000.spi: rx dma channel not available [ 2.951134] fsl-dspi 2100000.spi: can't get dma channels In retrospect, this should have been obvious, because LS2080A, LS2085A LS2088A and LX2160A don't appear to have an eDMA module at all. Looking again at their datasheets, the CTARE register (which is specific to XSPI functionality) seems to be documented, so switch them to XSPI mode instead. Fixes: 0feaf8f5afe0 ("spi: spi-fsl-dspi: Convert the instantiations that support it to DMA") Reported-by: Qiang Zhao <[email protected]> Tested-by: Qiang Zhao <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-09Merge series "opp: Unconditionally call dev_pm_opp_of_remove_table()" from ↵Mark Brown5-22/+16
Viresh Kumar <[email protected]>: Hello, This cleans up some of the user code around calls to dev_pm_opp_of_remove_table(). All the patches can be picked by respective maintainers directly except for the last patch, which needs the previous two to get merged first. These are based for 5.9-rc1. Rajendra, Since most of these changes are related to qcom stuff, it would be great if you can give them a try. I wasn't able to test them due to lack of hardware. Ulf, I had to revise the sdhci patch, sorry about that. Please pick this one. Diff between V1 and V2 is mentioned in each of the patches separately. Viresh Kumar (8): cpufreq: imx6q: Unconditionally call dev_pm_opp_of_remove_table() drm/lima: Unconditionally call dev_pm_opp_of_remove_table() drm/msm: Unconditionally call dev_pm_opp_of_remove_table() mmc: sdhci-msm: Unconditionally call dev_pm_opp_of_remove_table() spi: spi-geni-qcom: Unconditionally call dev_pm_opp_of_remove_table() spi: spi-qcom-qspi: Unconditionally call dev_pm_opp_of_remove_table() tty: serial: qcom_geni_serial: Unconditionally call dev_pm_opp_of_remove_table() qcom-geni-se: remove has_opp_table drivers/cpufreq/imx6q-cpufreq.c | 10 ++-------- drivers/gpu/drm/lima/lima_devfreq.c | 6 +----- drivers/gpu/drm/lima/lima_devfreq.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++------ drivers/mmc/host/sdhci-msm.c | 14 +++++--------- drivers/spi/spi-geni-qcom.c | 13 +++++-------- drivers/spi/spi-qcom-qspi.c | 15 ++++++--------- drivers/tty/serial/qcom_geni_serial.c | 13 +++++-------- include/linux/qcom-geni-se.h | 2 -- 11 files changed, 31 insertions(+), 66 deletions(-) base-commit: f4d51dffc6c01a9e94650d95ce0104964f8ae822 -- 2.25.0.rc1.19.g042ed3e048af
2020-09-09spi: spidev: Remove redundant initialization of variable statusJay Fang1-2/+2
In spidev_read() and spidev_write(), the variable status is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Signed-off-by: Jay Fang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-09spi: spi-qcom-qspi: Unconditionally call dev_pm_opp_of_remove_table()Viresh Kumar1-9/+6
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to find the OPP table with error -ENODEV (i.e. OPP table not present for the device). And we can call dev_pm_opp_of_remove_table() unconditionally here. While at it, create a new label and put clkname on errors. Signed-off-by: Viresh Kumar <[email protected]> Link: https://lore.kernel.org/r/b77aa0bbe82a580508e321a34da488b4b27966d0.1598594714.git.viresh.kumar@linaro.org Signed-off-by: Mark Brown <[email protected]>
2020-09-09spi: spi-geni-qcom: Unconditionally call dev_pm_opp_of_remove_table()Viresh Kumar1-8/+5
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to find the OPP table with error -ENODEV (i.e. OPP table not present for the device). And we can call dev_pm_opp_of_remove_table() unconditionally here. While at it, create a new label and put clkname on errors. Signed-off-by: Viresh Kumar <[email protected]> Link: https://lore.kernel.org/r/ea0864d41277e61fa31d304fbd4cf9af6b314269.1598594714.git.viresh.kumar@linaro.org Signed-off-by: Mark Brown <[email protected]>
2020-09-09spi: stm32: fix pm_runtime_get_sync() error checkingDan Carpenter1-1/+1
The pm_runtime_get_sync() can return either 0 or 1 on success but this code treats 1 as a failure. Fixes: db96bf976a4f ("spi: stm32: fixes suspend/resume management") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Alain Volmat <[email protected]> Link: https://lore.kernel.org/r/20200909094304.GA420136@mwanda Signed-off-by: Mark Brown <[email protected]>
2020-09-09spi: Fix memory leak on splited transfersGustav Wiklander1-2/+7
In the prepare_message callback the bus driver has the opportunity to split a transfer into smaller chunks. spi_map_msg is done after prepare_message. Function spi_res_release releases the splited transfers in the message. Therefore spi_res_release should be called after spi_map_msg. The previous try at this was commit c9ba7a16d0f1 which released the splited transfers after spi_finalize_current_message had been called. This introduced a race since the message struct could be out of scope because the spi_sync call got completed. Fixes this leak on spi bus driver spi-bcm2835.c when transfer size is greater than 65532: Kmemleak: sg_alloc_table+0x28/0xc8 spi_map_buf+0xa4/0x300 __spi_pump_messages+0x370/0x748 __spi_sync+0x1d4/0x270 spi_sync+0x34/0x58 spi_test_execute_msg+0x60/0x340 [spi_loopback_test] spi_test_run_iter+0x548/0x578 [spi_loopback_test] spi_test_run_test+0x94/0x140 [spi_loopback_test] spi_test_run_tests+0x150/0x180 [spi_loopback_test] spi_loopback_test_probe+0x50/0xd0 [spi_loopback_test] spi_drv_probe+0x84/0xe0 Signed-off-by: Gustav Wiklander <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08Merge series "spi: Adding support for Microchip Sparx5 SoC" from Lars ↵Mark Brown3-1/+98
Povlsen <[email protected]>: The series add support for the Sparx5 SoC SPI controller in the spi-dw-mmio.c spi driver. v5 changes: - rx-sample-delay-ns documentation changes from Rob Herring: - Drop superfluous type $ref - Add default value = 0 v4 changes: - Changed snps,rx-sample-delay-ns to snps,rx-sample-delay-ns suggested by Rob Herring (rockchip also has this property). - Added support for controller-level rx-sample-delay-ns value as well as per SPI slave value (rockchip has controller-level property). - Dropped internal mux in favor of suggested spi-mux to control bus inteface selection. v3 changes: - Added mux support for controlling SPI bus interface. This is new mux driver, bindings and added to sparx5 base DT. - Removed "microchip,spi-interface2" property in favour of "mux-controls" property in SPI controller (sparx5 only). - Changed dw_spi_sparx5_set_cs() to use the mux control instead of directly acessing "mux" register. Associated code/defines moved to mux driver. - Changed dw_spi_sparx5_set_cs() to match other similar functions in signature and avoid explicit CS toggling. - Spun off duplicated NAND device DT chunks into separate DT file. v2 changes: - Moved all RX sample delay into spi-dw-core.c, using the "snps,rx-sample-delay-ns" device property. - Integrated Sparx5 support directly in spi-dw-mmio.c - Changed SPI2 configuration to per-slave "microchip,spi-interface2" property. - Added bindings to existing snps,dw-apb-ssi.yaml file - Dropped patches for polled mode and SPI memory operations. Lars Povlsen (6): spi: dw: Add support for RX sample delay register spi: dw: Add Microchip Sparx5 support arm64: dts: sparx5: Add SPI controller and associated mmio-mux dt-bindings: snps,dw-apb-ssi: Add sparx5 support, plus rx-sample-delay-ns property arm64: dts: sparx5: Add spi-nor support arm64: dts: sparx5: Add spi-nand devices .../bindings/spi/snps,dw-apb-ssi.yaml | 21 ++++++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 47 ++++++++++++- .../arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 ++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 30 ++++++++ .../boot/dts/microchip/sparx5_pcb134.dts | 1 + .../dts/microchip/sparx5_pcb134_board.dtsi | 16 +++++ .../boot/dts/microchip/sparx5_pcb135.dts | 1 + .../dts/microchip/sparx5_pcb135_board.dtsi | 16 +++++ drivers/spi/spi-dw-core.c | 26 +++++++ drivers/spi/spi-dw-mmio.c | 70 ++++++++++++++++++- drivers/spi/spi-dw.h | 3 + 11 files changed, 260 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
2020-09-08spi: spi-mtk-nor: support standard spi propertiesIkjoon Jang1-13/+16
Use default supports_op() to support spi-[rt]x-bus-width properties. And check dummy op's byte length instead of its bus width for output. Signed-off-by: Ikjoon Jang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: tegra20: Simplify with dev_err_probe()Krzysztof Kozlowski1-7/+3
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: tegra114: Simplify with dev_err_probe()Krzysztof Kozlowski1-8/+3
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: synquacer: Simplify with dev_err_probe()Krzysztof Kozlowski1-3/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: stm32: Simplify with dev_err_probe()Krzysztof Kozlowski1-3/+1
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: qcom-qspi: Simplify with dev_err_probe()Krzysztof Kozlowski1-3/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: spi-mux: Simplify with dev_err_probe()Krzysztof Kozlowski1-3/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: cadence-quadspi: Simplify with dev_err_probe()Krzysztof Kozlowski1-4/+1
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: bcm2835: Simplify with dev_err_probe()Krzysztof Kozlowski1-5/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: atmel: Simplify with dev_err_probe()Krzysztof Kozlowski1-3/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: sprd: Release DMA channel also on probe deferralKrzysztof Kozlowski1-1/+1
If dma_request_chan() for TX channel fails with EPROBE_DEFER, the RX channel would not be released and on next re-probe it would be requested second time. Fixes: 386119bc7be9 ("spi: sprd: spi: sprd: Add DMA mode support") Cc: <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chunyan Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: dw: Add Microchip Sparx5 supportLars Povlsen1-1/+69
This adds SPI support for the Sparx5 SoC, which is using the MMIO Designware SPI controller. The Sparx5 differs from the Ocelot version in these areas: * The CS override is controlled by a new set of registers for this purpose. * The Sparx5 SPI controller has the RX sample delay register, and it must be configured for the (SPI NAND) device on SPI2. * The Sparx5 SPI controller has 2 different SPI bus interfaces on the same controller (don't ask...). The "spi-mux" driver should be used in conjunction with the SPI driver to select the appropriate bus. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: dw: Add support for RX sample delay registerLars Povlsen2-0/+29
This add support for the RX_SAMPLE_DLY register. If enabled in the Designware IP, it allows tuning of the rx data signal by means of an internal rx sample fifo. The register is controlled by the rx-sample-delay-ns DT property, which is defined per SPI slave as well on controller level. The controller level rx-sample-delay-ns will apply to all slaves without the property explicitly defined. The register is located at offset 0xf0, and if the option is not enabled in the IP, changing the register will have no effect. The register will only be written if any slave defines a nonzero value (after scaling by the clock period). Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-08spi: spi-cadence-quadspi: Fix mapping of buffers for DMA readsVignesh Raghavendra1-3/+5
Buffers need to mapped to DMA channel's device pointer instead of SPI controller's device pointer as its system DMA that actually does data transfer. Data inconsistencies have been reported when reading from flash without this fix. Fixes: ffa639e069fb ("mtd: spi-nor: cadence-quadspi: Add DMA support for direct mode reads") Signed-off-by: Vignesh Raghavendra <[email protected]> Tested-by: Jan Kiszka <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-07spi: qup: Allow for compile-testing on !ARMAlex Dewar1-1/+1
There seems no reason to restrict testing to ARM, so remove this constraint to improve test coverage. Build-tested with allyesconfig on x86. Signed-off-by: Alex Dewar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-07spi: stm32: Rate-limit the 'Communication suspended' messageMarek Vasut1-1/+5
The 'spi_stm32 44004000.spi: Communication suspended' message means that when using PIO, the kernel did not read the FIFO fast enough and so the SPI controller paused the transfer. Currently, this is printed on every single such event, so if the kernel is busy and the controller is pausing the transfers often, the kernel will be all the more busy scrolling this message into the log buffer every few milliseconds. That is not helpful. Instead, rate-limit the message and print it every once in a while. It is not possible to use the default dev_warn_ratelimited(), because that is still too verbose, as it prints 10 lines (DEFAULT_RATELIMIT_BURST) every 5 seconds (DEFAULT_RATELIMIT_INTERVAL). The policy here is to print 1 line every 50 seconds (DEFAULT_RATELIMIT_INTERVAL * 10), because 1 line is more than enough and the cycles saved on printing are better left to the CPU to handle the SPI. However, dev_warn_once() is also not useful, as the user should be aware that this condition is possibly recurring or ongoing. Thus the custom rate-limit policy. Finally, turn the message from dev_warn() to dev_dbg(), since the system does not suffer any sort of malfunction if this message appears, it is just slowing down. This further reduces the printing into the log buffer and frees the CPU to do useful work. Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller") Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Amelie Delaunay <[email protected]> Cc: Antonio Borneo <[email protected]> Cc: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-09-02spi: spi-loopback-test: Fix out-of-bounds readVincent Whitchurch1-1/+1
The "tx/rx-transfer - crossing PAGE_SIZE" test always fails when len=131071 and rx_offset >= 5: spi-loopback-test spi0.0: Running test tx/rx-transfer - crossing PAGE_SIZE ... with iteration values: len = 131071, tx_off = 0, rx_off = 3 with iteration values: len = 131071, tx_off = 0, rx_off = 4 with iteration values: len = 131071, tx_off = 0, rx_off = 5 loopback strangeness - rx changed outside of allowed range at: ...a4321000 spi_msg@ffffffd5a4157690 frame_length: 131071 actual_length: 131071 spi_transfer@ffffffd5a41576f8 len: 131071 tx_buf: ffffffd5a4340ffc Note that rx_offset > 3 can only occur if the SPI controller driver sets ->dma_alignment to a higher value than 4, so most SPI controller drivers are not affect. The allocated Rx buffer is of size SPI_TEST_MAX_SIZE_PLUS, which is 132 KiB (assuming 4 KiB pages). This test uses an initial offset into the rx_buf of PAGE_SIZE - 4, and a len of 131071, so the range expected to be written in this transfer ends at (4096 - 4) + 5 + 131071 == 132 KiB, which is also the end of the allocated buffer. But the code which verifies the content of the buffer reads a byte beyond the allocated buffer and spuriously fails because this out-of-bounds read doesn't return the expected value. Fix this by using ITERATE_LEN instead of ITERATE_MAX_LEN to avoid testing sizes which cause out-of-bounds reads. Signed-off-by: Vincent Whitchurch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-08-25spi: spi-fsl-espi: Remove use of %pChris Packham1-1/+1
The register offset is already included in the device name so even prior %p values being hashed printing the base was redundant. Remove the %p from the dev_info() output. Signed-off-by: Chris Packham <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2020-08-25spi: spi-cadence-quadspi: Populate get_name() interfaceVignesh Raghavendra1-0/+9
Implement get_name() interface of spi_controller_mem_ops so as to avoid changing of mtd->name due to driver being moved over to spi-mem framework from SPI NOR. This avoids breaking of MTD cmdline args being passed by bootloaders which maybe using old driver name. Fixes: 31fb632b5d43c ("spi: Move cadence-quadspi driver to drivers/spi/") Reported-by: Jan Kiszka <[email protected]> Suggested-by: Boris Brezillon <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-08-24spi: spi-fsl-dspi: delete EOQ transfer modeVladimir Oltean1-51/+5
After the only user of the limited EOQ mode has now been converted to DMA as of commit b09058bbf5f0 ("spi: spi-fsl-dspi: set ColdFire to DMA mode"), we can finally delete this code. Signed-off-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva3-5/+5
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <[email protected]>
2020-08-20Merge series "spi: rspi: Bit rate improvements" from Geert Uytterhoeven ↵Mark Brown1-29/+52
<[email protected]>: Hi Mark, This patch series contains several improvements for the Renesas SPI/QSPI driver related to bit rate configuration. Changes compared to v1 (https://lore.kernel.org/r/[email protected]): - Drop accepted patch. This has been tested on RSK+RZA1 (RSPI) and R-Car M2-W/Koelsch (QSPI), using a scope and logic analyzer, except for the by-one divider on QSPI. This has not been tested on legacy SuperH, due to lack of hardware. Thanks for your comments! Geert Uytterhoeven (7): spi: rspi: Remove useless .set_config_register() check spi: rspi: Clean up Bit Rate Division Setting handling spi: rspi: Increase bit rate accuracy on RZ/A spi: rspi: Increase bit rate range for RSPI on SH spi: rspi: Increase bit rate range for QSPI spi: rspi: Fill in spi_transfer.effective_speed_hz spi: rspi: Fill in controller speed limits drivers/spi/spi-rspi.c | 81 +++++++++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 29 deletions(-) -- 2.17.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
2020-08-20spi: imx: Remove unneeded probe messageFabio Estevam1-2/+0
There is no point in printing a plain "probed" message on successful probe. Just remove it and make the kernel log a bit less noisy. Signed-off-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-08-20spi: rspi: Fill in controller speed limitsGeert Uytterhoeven1-0/+12
Fill in the controller speed limits, so the SPI core can use them for validating SPI transfers, and adjusting them where needed. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
2020-08-20spi: rspi: Fill in spi_transfer.effective_speed_hzGeert Uytterhoeven1-0/+6
Fill in the effective bit rate used for transfers, so the SPI core can calculate instead of estimate delays. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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