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2023-12-11soc: mediatek: mtk-svs: Check if SVS mode is available in the beginningAngeloGioacchino Del Regno1-0/+16
The svs_init01() and svs_init02() functions are already checking if the INIT01 and INIT02 modes are available - but that's done in for loops and for each SVS bank. Give those a shortcut to get out early if no SVS bank features the desired init mode: this is especially done to avoid some locking in the svs_init01(), but also to avoid multiple for loops to check the same, when no bank supports a specific mode. Link: https://lore.kernel.org/r/20231121125044.78642-17-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Cleanup of svs_probe() functionAngeloGioacchino Del Regno1-21/+11
Cleanup the svs_probe() function: use dev_err_probe() where possible, change some efuse read failure gotos and then remove now impossible IS_ERR_OR_NULL() checks (as they will never return true) for nvmem (efuse read) failures. Also remove some unnecessary blank lines. Link: https://lore.kernel.org/r/20231121125044.78642-16-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Compress of_device_id entriesAngeloGioacchino Del Regno1-18/+6
Compress each entry to one line, as they fit in 84 columns, which is acceptable. While at it, also change the capital 'S' to 's' in 'sentinel'. Link: https://lore.kernel.org/r/20231121125044.78642-15-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_dataAngeloGioacchino Del Regno1-2/+0
Callers of svs_get_efuse_data() are already printing an error in case anything goes wrong, and the error print for nvmem_cell_read() failure is redundant: remove it. Link: https://lore.kernel.org/r/20231121125044.78642-14-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186AngeloGioacchino Del Regno1-37/+7
Include the additions of svs_mt8186_platform_probe() in the common svs_mt8192_platform_probe() function, remove the former, and use the latter as .probe() callback for MT8186. Link: https://lore.kernel.org/r/20231121125044.78642-13-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointerAngeloGioacchino Del Regno1-47/+40
Drop the "pbank" pointer from struct svs_bank: this was used to simply pass a pointer to the SVS bank that the flow was working on. That for instance needs more locking, and it's avoidable by adding one more parameter to functions working on specific banks, either a bank index number, or passing the svs_bank pointer directly from the caller. Even if the locking can now be reduced, for now, it was still left in place for the sake of making sure to not introduce any stability and/or reliability regression. Link: https://lore.kernel.org/r/20231121125044.78642-12-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCsAngeloGioacchino Del Regno1-266/+66
Remove almost all of the per-SoC .efuse_parsing() callbacks and replace them with one common callback svs_common_parse_efuse(): to do that, also change the function signature of the callback to add the newly required pointer to struct svs_platform_data, containing the SVS-global fuse map. This is done for MT8186, MT8188, MT8192, MT8195. As for MT8183, the efuse parse function was simplified by using the new fuse maps. Link: https://lore.kernel.org/r/20231121125044.78642-11-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe()AngeloGioacchino Del Regno1-26/+6
The t-calibration-data (SVS-Thermal calibration data) shall exist for all SoCs or SVS won't work anyway: move it to the common svs_probe() function and remove it from all of the per-SoC efuse_parsing() probe callbacks. Link: https://lore.kernel.org/r/20231121125044.78642-10-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform dataAngeloGioacchino Del Regno1-0/+12
In preparation for commonizing the efuse parsing function, add the SVS-Thermal coefficients for all SoCs for which said function can be commonized (MT8186, MT8188, MT8192, MT8195) and assign those to their platform data structure. That will be used to calculate the MTS parameter with the equation MTS = (ts_coeff * 2) / 1000 This commit brings no functional changes. Link: https://lore.kernel.org/r/20231121125044.78642-9-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Add a map to retrieve fused valuesAngeloGioacchino Del Regno1-0/+87
In preparation for adding a common efuse parsing function which will greatly reduce code duplication, add a SoC-specific mapping that will be used to retrieve the right SVS calibration values from the fuses. The maps are two: one is a Global Map used for reading parameters that are SVS-global, and one is a Bank Map for reading calibrations for each SVS Bank. While at it, also populate the map in the platform data for each SoC. Being this a preparation commit, there are no functional changes. Link: https://lore.kernel.org/r/20231121125044.78642-8-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Change the thermal sensor device nameAngeloGioacchino Del Regno1-3/+3
This driver tries to create a device link to the thermal sensor device: change all instances of "lvts" and "thermal" to "thermal-sensor", as that's what the devicetree node name must be. Note for MT8183: As specified in a previous commit, this SoC never got SVS probing, so this is not a breaking change and it does not require fallback for older device trees. Link: https://lore.kernel.org/r/20231121125044.78642-7-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bankAngeloGioacchino Del Regno1-25/+26
Many 32-bit members of this struct can be size reduced to either 16-bit or even 8-bit, for a total saving of ~61 bytes per bank. Keeping in mind that one SoC declares at least two banks, this brings a minimum of ~122 bytes saving (depending on compiler optimization). Link: https://lore.kernel.org/r/20231121125044.78642-6-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Build bank name string dynamicallyAngeloGioacchino Del Regno1-22/+17
In svs_bank_resource_setup() there is a "big" switch assigning different names depending on sw_id and type and this will surely grow: for example MT8186 has got a two-line type (high/low) SVS bank for CPU_BIG, and this would require more switch nesting. Simplify all of this by changing that to a devm_kasprintf() call that will concatenate the SW_ID string (e.g. SVSB_CPU_LITTLE) with the Type string (e.g. _LOW), resulting in the expected full bank name (e.g. SVSB_CPU_LITTLE_LOW). This being a dynamic allocation can be slower, but this happens only once in the life of this driver and it's not a performance path, so it's totally acceptable. Link: https://lore.kernel.org/r/20231121125044.78642-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Convert sw_id and type to enumerationsAngeloGioacchino Del Regno1-86/+106
The sw_id and type specifiers currently are defined as BIT(x) for unknown reasons: nothing in this code makes any AND/OR check for those, and that would never happen anyway because both sw_id and type are exclusive, as in: - There will never be a bank that is for both CPU and GPU, or for CPU and CCI together; - A bank cannot be contemporarily of one-line and two-line type, as much as it cannot contemporarily have both HIGH and LOW roles Change those definitions to enumerations and also add some kerneldoc to better describe what they are for and what they indicate. While at it, also change the names adding _SWID or _TYPE to increase human readability. Link: https://lore.kernel.org/r/20231121125044.78642-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflictAngeloGioacchino Del Regno1-54/+54
The svs_regs_v2 array of registers was offsetted by 0xc00 because the SVS node was supposed to have the same iostart as the thermal sensors. That's wrong for two reasons: 1. Two different devices cannot have the same iostart in devicetree, as those would technically be the same device otherwise; and 2. SVS and Thermal Sensor (be it LVTS or AUXADC thermal) are not the same IP, and those two do obviously have a different iospace. Even though there already are users of this register array, the only one that declares a devicetree node for SVS is MT8183 - but it never actually worked because the "tzts1" thermal zone missed thermal trips, hence this driver's probe always failed on that SoC. Knowing this - it is safe to say that keeping compatibility with older device trees is pointless, hence simply subtract the 0xc00 offset from the register offset array. Link: https://lore.kernel.org/r/20231121125044.78642-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: Add MT8188 VDOSYS reset bit mapHsiao Chien Sung2-1/+90
Add MT8188 reset bit map for VDOSYS0 and VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: Support reset bit mapping in mmsys driverHsiao Chien Sung2-0/+12
- Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsysHsiao Chien Sung1-0/+16
- Add Padding components - Add Mutex module definitions for Padding Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsysHsiao Chien Sung4-0/+203
- Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: mmsys: Add support for MT8188 VPPSYSyu-chang.lee1-0/+12
Add MT8188 VPPSYS0 and VPPSYS1 driver data. Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: svs: Add support for MT8186 SoCMark Tseng1-0/+282
MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11soc: mediatek: svs: Add support for MT8195 SoCMark Tseng1-0/+136
MT8195 svs gpu uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-07soc: qcom: socinfo: Add PM8937 Power ICDang Huynh1-1/+1
The PM8917 and PM8937 uses the same SUBTYPE ID. The PM8937 is found in boards with MSM8917, MSM8937 and MSM8940 and APQ variants. Signed-off-by: Dang Huynh <danct12@riseup.net> Link: https://lore.kernel.org/r/20231121-pm8937-v2-4-b0171ab62075@riseup.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: llcc: Add configuration data for X1E80100Rajendra Nayak1-0/+39
Add LLCC configuration data for X1E80100 SoC. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231117095315.2087-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: pmic_glink_altmode: fix port sanity checkJohan Hovold1-2/+2
The PMIC GLINK altmode driver currently supports at most two ports. Fix the incomplete port sanity check on notifications to avoid accessing and corrupting memory beyond the port array if we ever get a notification for an unsupported port. Fixes: 080b4e24852b ("soc: qcom: pmic_glink: Introduce altmode support") Cc: stable@vger.kernel.org # 6.3 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231109093100.19971-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: llcc: Add configuration data for SM8650Neil Armstrong1-0/+43
Add Last Level Cache Controller support for the SM8650 platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-llcc-v2-2-f281cec608e2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: socinfo: Add SM8650 SoC ID table entryNeil Armstrong1-0/+1
Add SoC Info support for the SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com> Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-socinfo-v2-2-4751e7391dc9@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: pmic_glink: enable UCSI by defaultDmitry Baryshkov1-10/+9
Now as the issue with the UCSI_GET_PDOS is worked around, enable UCSI support for all PMIC_GLINK platforms except Qualcomm SC8180X. The mentioned SoC has slightly different UCSI implementation, which I would like be tested properly before enabling it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231025115620.905538-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: stats: Express AOSS QMP module dependencyBjorn Andersson1-0/+1
In the case that the Qualcomm Sleep stats driver is builtin and the AOSS QMP driver is built as a module, neither the implementation nor the stub functions are available during linking, resulting in the following errors: qcom_stats.c:(.text+0x33c): undefined reference to `qmp_send' qcom_stats.c:(.text+0x8a0): undefined reference to `qmp_get' Resolve this by expressing the dependency between the two modules. Fixes: e84e61bdb97c ("soc: qcom: stats: Add DDR sleep stats") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/linux-arm-msm/202312061258.nAVYPFq2-lkp@intel.com/ Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205-qcom_stats-aoss_qmp-dependency-v1-1-8dabe1b5c32a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: qcom: stats: fix 64-bit divisionArnd Bergmann1-1/+1
Unguarded 64-bit division is not allowed on 32-bit kernels because this is very slow. The result of trying anyway is a link failure: arm-linux-gnueabi-ld: drivers/soc/qcom/qcom_stats.o: in function `qcom_ddr_stats_show': qcom_stats.c:(.text+0x334): undefined reference to `__aeabi_uldivmod' As this function is only used for debugging and not performance critical, rewrite it to use div_u64() instead. ARCH_TIMER_FREQ is a multiple of MSEC_PER_SEC anyway, so there is no loss in precisison. Fixes: e84e61bdb97c ("soc: qcom: stats: Add DDR sleep stats") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231206123717.524009-1-arnd@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07soc: hisilicon: kunpeng_hccs: Support the platform with PCC type3 and ↵Huisong Li2-25/+125
interrupt ack Support the platform with PCC type3 and interrupt ack. And a version specific structure is introduced to handle the difference between the device in the code. Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-07soc: hisilicon: kunpeng_hccs: Remove an unused blank lineHuisong Li1-1/+0
Remove an unused blank line. Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-07soc: hisilicon: kunpeng_hccs: Add failure log for no _CRS methodHuisong Li1-1/+3
Driver gets the PCC channel id by using the PCC GAS in _CRS. But, currently, if the firmware has no _CRS method on platform, there is not any failure log. So this patch adds the log for this. Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-07soc: hisilicon: kunpeng_hccs: Fix some incorrect format stringsHuisong Li1-6/+6
Fix some incorrect format strings. Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-07drivers: soc: xilinx: Fix error message on SGI registration failureJay Buddhabhatti1-1/+5
Failure to register SGI for firmware event notification is non-fatal error when feature is not supported by other modules such as Xen and TF-A. Add _info level log message for such special case. Also add XST_PM_INVALID_VERSION error code and map it to -EOPNOSUPP Linux kernel error code. If feature is not supported or EEMI API version is mismatch, firmware can return XST_PM_INVALID_VERSION = 4 or XST_PM_NO_FEATURE = 19 error code. Co-developed-by: Tanmay Shah <tanmay.shah@amd.com> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112713.22718-5-jay.buddhabhatti@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-07firmware: xilinx: Update firmware call interface to support additional argsJay Buddhabhatti2-2/+2
System-level platform management layer (do_fw_call()) has support for maximum of 5 arguments as of now (1 EEMI API ID + 4 command arguments). In order to support new EEMI PM_IOCTL IDs (Secure Read/Write), this support must be extended to support one additional argument, which results in a configuration of - 1 EEMI API ID + 5 command arguments. Update zynqmp_pm_invoke_fn() and do_fw_call() with this new definition containing variable arguments. As a result, update all the references to pm invoke function with the updated definition. Co-developed-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112713.22718-2-jay.buddhabhatti@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-06soc: ti: k3-socinfo: Revamp driver to accommodate different rev structsNeha Malcom Francis1-16/+55
k3-socinfo.c driver assumes silicon revisions for every platform are incremental and one-to-one, corresponding to JTAG_ID's variant field: 1.0, 2.0 etc. This assumption is wrong for SoCs such as J721E, where the variant field to revision mapping is 1.0, 1.1. Further, there are SoCs such as AM65x where the sub-variant version requires custom decoding of other registers. Address this by using conditional handling per JTAG ID that requires an exception with J721E as the first example. To facilitate this conversion, use macros to identify the JTAG_ID part number and map them to predefined string array. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Co-developed-by: Thejasvi Konduru <t-konduru@ti.com> Signed-off-by: Thejasvi Konduru <t-konduru@ti.com> Link: https://lore.kernel.org/r/20231016101608.993921-4-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06soc: microchip: mpfs: add auto-update subdev to system controllerConor Dooley1-2/+7
The PolarFire SoC's system controller offers the ability to re-program the FPGA from a user application via two, related, mechanisms. In-Application Programming (IAP) is not ideal for use in Linux, as it will immediately take down the system when requested. Auto Update is preferred, as it will only take affect at device power up*, allowing the OS (and potential applications in AMP) to be shut down gracefully. * Auto Update occurs at device initialisation, which can also be triggered by device reset - possible with the v2023.02 version of the Hart Software Services (HSS) and reference design. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-06soc: microchip: mpfs: print service status in warning messageConor Dooley1-1/+3
Now that resp_status is set for failed services, print the status in the error path's warning. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-06soc: microchip: mpfs: enable access to the system controller's flashConor Dooley2-0/+21
The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming). Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-04soc: qcom: pmic-glink: switch to DRM_AUX_HPD_BRIDGEDmitry Baryshkov2-24/+10
Use the freshly defined DRM_AUX_HPD_BRIDGE instead of open-coding the same functionality for the DRM bridge chain termination. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-6-dmitry.baryshkov@linaro.org
2023-12-03soc: qcom: stats: Add DDR sleep statsKonrad Dybcio1-1/+186
Add DDR sleep stats that include: - the available RAM low power states - per-state residency information - per-frequency residency information (for some freqs only, it seems) - DDR vote information (AB/IB) and some magic thing that we're yet to decode. Based on the msm-5.4 downstream implementation, debugged with some help from Qualcomm's Maulik Shah. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231130-topic-ddr_sleep_stats-v1-2-5981c2e764b6@linaro.org [bjorn: Add missing bitfield.h include] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-11-23soc: apple: mailbox: Add explicit include of platform_device.hRob Herring1-0/+1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other and pull in various other headers. In preparation to fix this, adjust the includes for what is actually needed. platform_device.h is implicitly included by of_platform.h, but that's going to be removed. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2023-11-23soc: apple: mailbox: Rename config symbol to APPLE_MAILBOXHector Martin2-4/+3
With the original owner of APPLE_MAILBOX removed, let's rename the new APPLE_MBOX to the old name. This avoids .config churn for downstream users, and leaves us with an identical config symbol and module name as before. Acked-by: Eric Curtin <ecurtin@redhat.com> Acked-by: Neal Gompa <neal@gompa.dev> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Hector Martin <marcan@marcan.st>
2023-11-23soc: apple: rtkit: Port to the internal mailbox driverHector Martin3-80/+31
Now that we have a mailbox driver in drivers/soc/apple, port the RTKit code to it. This mostly just entails replacing calls through the mailbox subsystem with direct calls into the driver. Acked-by: Eric Curtin <ecurtin@redhat.com> Acked-by: Neal Gompa <neal@gompa.dev> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Hector Martin <marcan@marcan.st>
2023-11-23soc: apple: mailbox: Add ASC/M3 mailbox driverHector Martin4-0/+502
This new driver is based on the existing apple-mailbox driver, but replaces the usage of the mailbox subsystem with directly exported symbols. As part of this refactor, this adds support for using the hardware FIFOs (not supported in mailbox) and implicitly fixes a bunch of bugs caused by bad interactions with the mailbox subsystem. It also adds runtime-PM support. The new config symbol is APPLE_MBOX, while the module name remains identical ("apple-mailbox"). The configs are mutually exclusive in Kconfig, to avoid conflicts. Acked-by: Eric Curtin <ecurtin@redhat.com> Acked-by: Neal Gompa <neal@gompa.dev> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Hector Martin <marcan@marcan.st>
2023-11-23soc: apple: rtkit: Get rid of apple_rtkit_send_message_waitHector Martin1-32/+0
It is fundamentally broken and has no users. Just remove it. Acked-by: Eric Curtin <ecurtin@redhat.com> Acked-by: Neal Gompa <neal@gompa.dev> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Hector Martin <marcan@marcan.st>
2023-11-22soc: sifive: shunt ccache driver to drivers/cacheConor Dooley5-287/+0
Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-15soc: xilinx: fix unhandled SGI warning messageTanmay Shah1-1/+1
Xen broadcasts SGI to each VM when multiple VMs run on Xen hypervisor. In such case spurious SGI is expected if one event is registered by one VM and not registered by another VM. We let users know that Unhandled SGI is not error and expected if kernel is running on Xen hypervisor. Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1698431039-2734260-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-15soc: xilinx: fix quoted string split across linesMichal Simek1-4/+4
Fix checkpatch warning "quoted string split across lines". No functional change. Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1698430295-2731040-1-git-send-email-radhey.shyam.pandey@amd.com
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