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The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Some TI Keystone family of SoCs contain a system controller (like the
Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations
are provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.
This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management
of various devices present on the SoC. Various reset functionalities
are achieved by the means of different TI SCI device operations
provided by the TI SCI framework.
Signed-off-by: Andrew F. Davis <[email protected]>
[[email protected]: documentation changes, revised commit message]
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
[[email protected]: const struct reset_control_ops]
Signed-off-by: Philipp Zabel <[email protected]>
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The Cortina Systems Gemini reset controller is a simple
32bit register with self-deasserting reset lines. It is
accessed using regmap over syscon.
Acked-by: Philipp Zabel <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Rename the current Kconfig name used for the TI SYSCON Reset
driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the
convention used for all the reset drivers present at the
base reset folder.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This patch adds the reset controller functionality for
Peripheral PHYs to the Arria10 System Resource Chip.
Signed-off-by: Thor Thayer <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.
Cc: Lucas Stach <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Andrey Smirnov <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This patch adds reset controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <[email protected]>
Reviewed-by: Shawn Guo <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.
Acked-by: Philipp Zabel <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Also remove the RESET_CONTROLLER dependency, this Kconfig file is
included inside the menuconfig already.
Cc: Chen Feng <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Cc: Moritz Fischer <[email protected]>
Cc: Sören Brinkmann <[email protected]>
Acked-by: Michal Simek <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Cc: Maxime Coquelin <[email protected]>
Cc: Gabriel Fernandez <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: Dinh Nguyen <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Cc: Damien Horsley <[email protected]>
Acked-by: James Hartley <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: Neil Armstrong <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: Joachim Eastwood <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Cc: Antoine Tenart <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: Aban Bedel <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This is the initial commit for UniPhier reset controller driver.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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The STM32 MCUs family IPs can be reset by accessing some registers
from the RCC block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Maxime Coquelin <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add a reset-controller driver for performing reset management of
various devices present on the SoC, with the reset registers shared
between devices in a common register memory space. This driver uses
the syscon/regmap frameworks to actually implement the various reset
functionalities needed by the reset consumer devices.
Signed-off-by: Andrew F. Davis <[email protected]>
[[email protected]: add documentation, syscon name change]
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This patch adds the platform driver for the Amlogic Meson SoC Reset
Controller.
The Meson8b and GXBB SoCs are supported.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add System reset controller driver for Oxford Semiconductor OXNAS SoC
Family.
CC: Ma Haijun <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add reset controller driver for Pistachio SoC
Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: James Hartley <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add reset driver for hi6220-hikey board,this driver supply deassert
of IP on hi6220 SoC.
Signed-off-by: Chen Feng <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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The directory drivers/reset/ is guarded by CONFIG_RESET_CONTROLLER
in driver/Makefile.
CONFIG_RESET_CONTROLLER is boolean, so it always evaluates to 'y'
in drivers/reset/Makefile.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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This adds a reset controller driver to control the Xilinx Zynq
AP-SoC's various resets.
Signed-off-by: Moritz Fischer <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Acked-by: Sören Brinkmann <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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The AR71XX/AR9XXX SoC have a simple reset controller with one bit per
reset line.
Signed-off-by: Alban Bedel <[email protected]>
Acked-by: Ralf Baechle <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add reset driver for the Reset Generation Unit (RGU) found on NXP
LPC18xx and LPC43xx devies. This reset controller features up to 64
reset lines connected to different blocks and peripheral in the SoC.
Most reset lines on the controller are self clearing except for
those dealing with the Cortex-M0 cores on LPC43xx devices.
This driver also registers a restart handler that can be used to
reset the entire device.
Signed-off-by: Joachim Eastwood <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
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Add a reset controller for Marvell Berlin SoCs which is used by the
USB PHYs drivers (for now).
Signed-off-by: Antoine Ténart <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: Steffen Trumtrar <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
---
Notes:
Changes since v2:
- remove superfluous ret in probe function
- add Acked-by
Changes since v1:
- use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
- print pdev->dev.of_node->full_name on error
- use proper IS_ERR/PTR_ERR
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This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.
The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: Stephen Gallimore <[email protected]>
Signed-off-by: Srinivas Kandagatla <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
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The Allwinner A31 and most of the other Allwinner SoCs have an IP
maintaining a few other IPs in the SoC in reset by default. Among these
IPs are the A31's High Speed Timers, hence why we can't use the regular
driver construct in every cases, and need to call the registering
function directly during machine initialisation.
Apart from this, the implementation is fairly straightforward, and could
easily be moved to a generic MMIO-based reset controller driver if the
need ever arise.
Signed-off-by: Maxime Ripard <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
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This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Reviewed-by: Shawn Guo <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Pavel Machek <[email protected]>
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