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I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.
Signed-off-by: Thierry Reding <[email protected]>
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Make sure to unprepare the clock before returning on late probe errors.
Fixes: b388f15fd14c ("pwm: pwm-tiehrpwm: Use clk_enable/disable instead clk_prepare/unprepare.")
Signed-off-by: Johan Hovold <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Remove unbalanced RPM put at driver unbind which resulted in a negative
usage count.
Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Signed-off-by: Johan Hovold <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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66AK2G SoC has ECAP subsystem that is used as pwm-backlight provider for
display. Hence, enable pwm-tiecap driver to be built for Keystone
architecture.
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It adds PWM device driver for ZTE ZX family SoCs. The PWM controller
supports 4 devices with polarity configuration.
The driver has been tested with pwm-regulator support to scale core
voltage via cpufreq.
Signed-off-by: Shawn Guo <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This adds support for the third (optional) pwm cell to specify the
polarity, which is needed by display backlights for example.
Signed-off-by: Stefan Wahren <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The rk3328 SoC supports atomic update, we could lock the configuration
of period and duty at first, after unlock is configured, the period and
duty are effective at the same time.
If the polarity, period and duty need to be configured together,
the way for atomic update is "configure lock and old polarity" ->
"configure period and duty" -> "configure unlock and new polarity".
Signed-off-by: David Wu <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Just use the same PWM ops for each IP, and get rid of the ops in struct
rockchip_pwm_data, but still define the three different instances of the
struct to use common interface for each IP.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It is usually possible to configure the polarity, cycle and duty all at
once, so that the polarity and cycle and duty are applied atomically.
Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as
well as prepare for the next atomic update commit.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and
pwm_apply_v2() instead.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It seems the rockchip_pwm_config() always returns the result 0, so
remove the judge.
Signed-off-by: David Wu <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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New PWM module provides two individual clocks for APB clock and function
clock.
Signed-off-by: David Wu <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu
driver.
Commit edf4100906044225 ("ARM: shmobile: sh7372 dtsi: Remove Legacy
file") removed this SoC from the kernel in v4.1.
Acked-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Undo preparation of a clock source if vt8500_pwm_probe() is not
successful.
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The function
static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep)
takes the chip in and out of sleep mode, depending on the value of
sleep, which is interpreted as a boolean.
To clarify that 'int sleep' is a boolean and not a sleep delay,
change the function interface to:
static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable)
Suggested-by: Andy Shevchenko <[email protected]>
Signed-off-by: Sven Van Asbroeck <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Carlo Caione <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This release cycle's changes include mostly updates and cleanups to
existing drivers along with a few cleanups to the core, documentation
and device tree bindings"
* tag 'pwm/for-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: cros-ec: Fix transposed param settings
pwm: meson: Improve PWM calculation precision
dt-bindings: pwm: meson: Add compatible for gxbb ao PWMs
pwm: meson: Add compatible for the gxbb ao PWMs
pwm: sun4i: Drop legacy callbacks
pwm: sun4i: Switch to atomic PWM
pwm: sun4i: Improve hardware read out
pwm: hibvt: Constify hibvt_pwm_ops
pwm: Silently error out on EPROBE_DEFER
pwm: Standardize document format
pwm: bfin: Remove unneeded error message
dt-bindings: pwm: Update STM32 timers clock names
dt-bindings: pwm: Add R-Car M3-W device tree bindings
pwm: tegra: Set maximum pwm clock source per SoC tapeout
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The __cros_ec_pwm_get_duty() routine was transposing the insize and
outsize fields when calling cros_ec_cmd_xfer_status().
The original code worked without error due to size of the two particular
parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is
not fixing an actual runtime problem, just correcting the calling usage.
Signed-off-by: Nick Vaccaro <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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When using input clocks with high rates, such as clk81 (166MHz), the
fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error.
Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000
fin_ns = 5,9999999
which is, of course, rounded down to 5. This introduces an error of ~20%
on the period requested from the PWM.
This patch uses ps instead of ns (and 64 bit integers) to perform the
calculation. This should give a good enough precision.
Fixes: 211ed630753d ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
squash! pwm: meson: Improve pwm calculation precision
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On the gxbb (and gxl) family, the PWMs of the AO domain require a
specific compatible because the possible input clocks are different
from the EE PWMs input clocks.
Since the number of possible input clocks is also different, the
'num_parents' field is added to all the Meson PWM data.
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Remove the legacy callbacks .enable(), .disable(), .set_polarity() and
.config().
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Switch the driver to atomic PWM. This makes it easier to wait a proper
amount of time when changing the duty cycle before disabling the channel
(main use case is switching the duty cycle to 0 before disabling).
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement .get_state instead of only reading the polarity at probe time.
This allows to get the proper state, period and duty cycle.
Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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File size before:
text data bss dec hex filename
1510 296 0 1806 70e drivers/pwm/pwm-hibvt.o
File size After adding 'const':
text data bss dec hex filename
1606 192 0 1798 706 drivers/pwm/pwm-hibvt.o
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we
shouldn't print an error message. Just be silent in this case.
Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Andreas Färber <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
Signed-off-by: Markus Elfring <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 48 MHz.
In Tegra186, it is 102 MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: Laxman Dewangan <[email protected]>
Acked-by: Jon Hunter <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.
The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.
Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: Paul Cercueil <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
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It is required to know the PWM clock source frequency to calculate the
PWM period.
In driver, the clock source frequency of the PWM does not get change
and, hence, get the clock source frequency in driver init. Get this
values later for period calculation from pwm_config().
This will help in avoiding the clock call for getting clock rate in the
pwm_config() each time.
Signed-off-by: Laxman Dewangan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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GPIO-only driver operation never clears the SLEEP bit, which can cause
the GPIOs to become unusable.
Example:
1. user requests first PWM -> driver clears SLEEP bit
2. user frees last PWM -> driver sets SLEEP bit
3. user requests GPIO
4. user switches GPIO on -> output does not turn on
because SLEEP bit is set
Prevent this behaviour by letting the runtime PM framework control the
SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported
or in use.
Fixes: bccec89f0a35 ("Allow any of the 16 PWMs to be used as a GPIO")
Reported-by: Sven Van Asbroeck <[email protected]>
Signed-off-by: Sven Van Asbroeck <[email protected]>
Suggested-by: Mika Westerberg <[email protected]>
Reviewed-by: Mika Westerberg <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: John Crispin <[email protected]>
Signed-off-by: Fengguang Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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For very short periods, the result of the division might overflow the
unsigned long hz variable (on 32-bit architectures). Avoid that by
making it an unsigned long long. While at it, also remove an unneeded
local variable whose only purpose is to store a temporary computation.
Acked-by: Laxman Dewangan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
the voltage level of the regulator output.
When system enters suspend, some PWM client/slave regulator devices
require the PWM output to be tristated.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan <[email protected]>
Acked-by: Jon Hunter <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The rate of the PWM calculated as follows:
hz = NSEC_PER_SEC / period_ns;
rate = (rate + (hz / 2)) / hz;
This has the precision loss in lower PWM rate.
Change this to have more precision as:
hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns);
rate = DIV_ROUND_CLOSEST(rate * 100, hz)
Example:
1. period_ns = 16672000, PWM clock rate is 200 KHz.
Based on old formula
hz = NSEC_PER_SEC / period_ns
= 1000000000ul/16672000
= 59 (59.98)
rate = (200K + 59/2)/59 = 3390
Based on new method:
hz = 5998
rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
If we measure the PWM signal rate, we will get more accurate
period with rate value of 3334 instead of 3390.
2. period_ns = 16803898, PWM clock rate is 200 KHz.
Based on old formula:
hz = 59, rate = 3390
Based on new formula:
hz = 5951, rate = 3360
The PWM signal rate of 3360 is more near to requested period
than 3333.
Signed-off-by: Laxman Dewangan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Use macro DIV_ROUND_CLOSEST_ULL() for 64-bit division to closest one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This patch adds support for the PWM core found on current ARM base SoCs
made by MediaTek. This IP core supports 5 channels and has 2 operational
modes. There is the old mode, which is a classical PWM and the new mode
which allows the user to define bitmasks that get clocked out on the
pins. As the subsystem currently only supports PWM cores with the "old"
mode, we can safely ignore the "new" mode for now.
Signed-off-by: John Crispin <[email protected]>
[[email protected]: minor cleanups]
Signed-off-by: Thierry Reding <[email protected]>
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sama5d2 can use the same atmel_pwm_data as sama5d3.
Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The currently Atmel PWM controllers supported by this driver could
change period or duty factor without channel disable, for regular
channels (sama5d3 support this by using period or duty factor update
registers, sam9rl support this by writing channel update register and
select the corresponding update: period or duty factor). The chip
doesn't support run time changings of signal polarity. To take advantage
of atomic PWM framework and let controller works without glitches, in
this patch only the duty factor could be changed without disabling PWM
channel. For period and signal polarity the atomic PWM is simulated by
disabling + enabling the right PWM channel.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement the suspend/resume hooks to make sure the PWM device is
restored to a correct state after a suspend.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement the ->apply() hook and drop the ->enable(), ->disable,
->set_polarity and ->config() ones.
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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If the PWM was not enabled at U-Boot loader, PWM could not work for
clock always disabled at PWM driver. The PWM clock is enabled at
beginning of pwm_apply(), but disabled at end of pwm_apply().
If the PWM was enabled at U-Boot loader, PWM clock is always enabled
unless closed by ATF. The pwm-backlight might turn off the power at
early suspend, should disable PWM clock for saving power consume.
It is important to provide opportunity to enable/disable clock at PWM
driver, the PWM consumer should ensure correct order to call PWM enable
and disable, and PWM driver ensure state of PWM clock synchronized with
PWM enabled state.
Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update")
Cc: [email protected]
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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At least on cherrytrail, the update bit will never go low when the
enabled bit is not set.
This causes the backlight on my cube iwork8 air tablet to never turn on
again after being turned off because in the pwm_lpss_apply enable path
pwm_lpss_update will fail causing an error exit and the enable-bit to
never get set. Any following pwm_lpss_apply calls will fail the
pwm_lpss_is_updating check.
Since the docs say that the update bit should be set before the
enable-bit, split pwm_lpss_update into setting the update-bit and
pwm_lpss_wait_for_update, and move the pwm_lpss_wait_for_update call
in the enable path to after setting the enable-bit.
Fixes: 10d56a4 ("pwm: lpss: Avoid reconfiguring while UPDATE bit...")
Cc: Ilkka Koskinen <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Tested-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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As a preparation for special treatment for Broxton we split Tangier
configuration.
Fixes: b89b4b7a3d0a ("pwm: lpss: pci: Enable PWM module on Intel Edison")
Signed-off-by: Andy Shevchenko <[email protected]>
Tested-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This set contains mostly fixes to existing drivers as well as cleanup
of code that's not been in active use for a while"
* tag 'pwm/for-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (27 commits)
acpi: lpss: call pwm_add_table() for BSW PWM device
pwm: Try to load modules during pwm_get()
pwm: Don't hold pwm_lookup_lock longer than necessary
pwm: Make the PWM_POLARITY flag in DTB optional
pwm: Print error messages with pr_err() instead of pr_debug()
pwm: imx: Add polarity inversion support to i.MX's PWMv2
pwm: imx: doc: Update imx-pwm.txt documentation entry
pwm: imx: Remove redundant i.MX PWMv2 code
pwm: imx: Provide atomic PWM support for i.MX PWMv2
pwm: imx: Move PWMv2 wait for fifo slot code to a separate function
pwm: imx: Move PWMv2 software reset code to a separate function
pwm: imx: Rewrite v1 code to facilitate switch to atomic PWM
pwm: imx: Add separate set of PWM ops for v1 and v2
pwm: imx: Remove ipg clock and enable per clock when required
pwm: lpss: Add Intel Gemini Lake PCI ID
pwm: lpss: Do not export board infos for different PWM types
pwm: lpss: Avoid reconfiguring while UPDATE bit is still enabled
pwm: lpss: Switch to new atomic API
pwm: lpss: Allow duty cycle to be 0
pwm: lpss: Avoid potential overflow of base_unit
...
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Add a module name string to the pwm_lookup struct and if specified try
to load the module using request_module() if pwmchip_find_by_name() is
unable to find the PWM chip.
This is a last resort to work around drivers that can't - and can't be
made to - deal with deferred probe.
Signed-off-by: Hans de Goede <[email protected]>
[[email protected]: rename new macro, reword commit message]
[[email protected]: add comment explaining use-case]
Signed-off-by: Thierry Reding <[email protected]>
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There is no need to hold pwm_lookup_lock after we're done with looping
over pwm_lookup_list, so release it earlier.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Change the PWM chip driver registration so that a chip driver that
supports polarity inversion can still be used with DTBs that don't
provide the polarity flag as part of the specifier.
This is done to provide polarity inversion support for the pwm-imx
driver without having to modify all existing DTS files.
Signed-off-by: Lothar Wassmann <[email protected]>
Signed-off-by: Bhuvanchandra DV <[email protected]>
Suggested-by: Sascha Hauer <[email protected]>
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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