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To remove legacy API related functions in the future, this patch
uses "atomic" related function instead. No change in behavior.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This patch adds support for "atomic" API. This behavior differs with
legacy APIs a little.
Legacy APIs:
The PWMCNT register will be updated in rcar_pwm_config() even if
the PWM state is disabled.
Atomic API:
The PWMCNT register will be updated in rcar_pwm_apply() only if
the PWM state is enabled. Otherwize, if a PWM runs with 30% duty
cycles and the pwm_apply_state() is called with state->enabled = 0,
->duty_cycle = 60 and ->period = 100, this is possible to output
a 60% duty cycle.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add support for SAM9X60's PWM controller.
Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Rename objects of type atmel_pwm_data to contain chip name instead of
version number.
Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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SAM9X60's PWM controller uses 32 bits counters thus it could generate
signals with higher period and duty cycles than the old ones. Prepare
the current driver to be able to work with old controllers (that uses
16 bits counters) and with the new SAM9X60's controller, by providing
counters information based on compatible string.
Signed-off-by: Claudiu Beznea <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add struct atmel_pwm_data to embed different per controller information.
It prepares adding support for another similar controller that needs
additional information. At this stage, embed a member of type struct
atmel_pwm_registers in it.
Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add support for the hi3559v100-shub-pwm and hisilicon,hi3559v100-pwm
platforms. They require a special quirk: the PWM has to be enabled twice
to force a duty_cycle refresh.
Signed-off-by: Mathieu Othacehe <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Split pwm_soc array in one struct per SoC and point to the corresponding
one in of-data.
Signed-off-by: Mathieu Othacehe <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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"ret" only holds zero and negative error codes. It needs to be signed
for the error handling to work.
Fixes: 9f4c8f9607c3 ("pwm: imx: Add ipg clock operation")
Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The two PWM implementations called v1 (for i.MX1 and i.MX21) and v2 (for
i.MX27 and later) have nothing in common apart from needing two clocks
named "per" and "ipg" and being integrated in a SoC named i.MX.
So split the file containing the two disjunct drivers into two files and
two complete separate drivers.
Signed-off-by: Uwe Kleine-König <[email protected]>
[[email protected]: fix a modular build issue]
Signed-off-by: Thierry Reding <[email protected]>
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When getting the peripheral clock fails with -EPROBE_DEFER the driver is
usually probed again later and emitting an error message is irritating.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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When ->probe() fails the driver core takes care of unsetting the driver
data.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The ->remove() callback is only called when probe returned successfully.
In this case the driver data cannot be NULL.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This callback was introduced in commit 62099abf67a2 ("pwm: Add debugfs
interface") in 2012 and up to now there is not a single user. So drop
this unused code.
Signed-off-by: Uwe Kleine-König <[email protected]>
[[email protected]: remove kerneldoc for ->dbg_show()]
Signed-off-by: Thierry Reding <[email protected]>
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Given that struct pwm_state is sparse (at least on some platforms),
variables of this type might represent the same state because all fields
are pairwise identical but still memcmp() returns a difference because
some of the unused bits are different.
To prevent surprises compare member by member instead of the whole
occupied memory.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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i.MX PWM module's ipg_clk_s is for PWM register access, on most of i.MX
SoCs, this ipg_clk_s is from system ipg clock or perclk which is always
enabled, but on i.MX7D, the ipg_clk_s is from PWM1_CLK_ROOT which is
controlled by CCGR132, that means the CCGR132 MUST be enabled first
before accessing PWM registers on i.MX7D. This patch adds ipg clock
operation to make sure register access successfully on i.MX7D and it
fixes Linux kernel boot up hang during PWM driver probe.
Fixes: 4a23e6ee9f69 ("ARM: dts: imx7d-sdb: Restore pwm backlight support")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Alexander Shiyan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Commit e39c0df1be5a ("pwm: Introduce the pwm_args concept") has
changed the variable for the period for clps711x-pwm driver, so now
pwm_get/set_period() works with pwm->state.period variable instead
of pwm->args.period.
This patch changes the period variable in other places where it is used.
Signed-off-by: Alexander Shiyan <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Cc: Bart Tanghe <[email protected]>
Signed-off-by: Stefan Wahren <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The Cygnus architecture uses a Kona PWM. This is already present in the
device tree but can't be built actually. Hence, allow the Kona PWM to
be built for the Cygnus architecture.
Signed-off-by: Clément Péron <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement the get_state() function and set the initial state to reflect
real state of the hardware. This allows to keep the PWM running if it was
enabled in bootloader. It is very similar to the GPIO behavior. GPIO pin
set as output in bootloader keep the same setting in Linux unless it is
reconfigured.
If we find the PWM block enabled we need to prepare and enable its source
clock otherwise the clock will be disabled late in the boot as unused.
That will leave the PWM in enabled state but with disabled clock. That has
a side effect that the PWM output is left at its current level at which
the clock was disabled. It is totally non-deterministic and it may be LOW
or HIGH.
Signed-off-by: Michal Vokáč <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Use existing macros to define register fields instead of manually shifting
the bit masks. Also define some more register bits.
Signed-off-by: Michal Vokáč <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Sort included header files alphabetically.
Signed-off-by: Michal Vokáč <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Regarding the .request case: The consumer might be interested in taking
over the configured state from the boot loader. So the initially
configured state should be retained.
For the free case the PWM consumer is responsible for disabling the PWM
before calling pwm_put() and there are three subcases to consider:
a) The PWM is already off. Then there is no gain in disabling the PWM
once more.
b) The PWM is still running and there is a good reason for that. (Not
sure this is a valid case, I cannot imagine such a good reason.)
Then it is counterproductive to disable the PWM.
c) The PWM is still running because the consumer failed to disable the
PWM. Then the consumer needs fixing and there is little incentive to
paper over the problem in the backend driver.
This aligns the lpc18xx-sct driver to the other PWM drivers that also
don't reconfigure the hardware in .request and .free.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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According to the datasheet the update bit must be set if the on-time-div
or the base-unit changes.
Now that we properly order device resume on Cherry Trail so that the GFX0
_PS0 method no longer exits with an error, we end up with a sequence of
events where we are writing the same values twice in a row.
First the _PS0 method restores the duty cycle of 0% the GPU driver set
on suspend and then the GPU driver first updates just the enabled bit in
the pwm_state from 0 to 1, causing us to write the same values again,
before restoring the pre-suspend duty-cycle in a separate pwm_apply call.
When writing the update bit the second time, without changing any of
the values the update bit clears immediately / instantly, instead of
staying 1 for a while as usual. After this the next setting of the update
bit seems to be ignored, causing the restoring of the pre-suspend
duty-cycle to not get applied. This makes the backlight come up with
a 0% dutycycle after suspend/resume.
Any further brightness changes after this do work.
This commit moves the setting of the update bit into pwm_lpss_prepare()
and only sets the bit if we have actually changed any of the values.
This avoids the setting of the update bit the second time we configure
the PWM to 0% dutycycle, this fixes the backlight coming up with 0%
duty-cycle after a suspend/resume.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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On Cherry Trail devices under Windows the PWM controller used for the
backlight is considered part of the GPU even though it is part of the LPSS
block and thus is an entirely different independent hardware unit.
Because of this on Cherry Trail the GPU's (GFX0 ACPI node) _PS3 and _PS0
methods save and restore the PWM controller registers.
If userspace blanks the screen before suspending, such as e.g. GNOME
does, then the PWM controller will be runtime-suspended when the suspend
starts. This causes the GFX0 _PS? methods to save a value of 0xffffffff
for the PWM control register and to restore this value on resume.
0xffffffff is not a valid value for the register and writing this causes
problems such as e.g. a flickering backlight.
This commit adds a prepare method to the dev_pm_ops and makes it return 0
on Cherry Trail devices forcing a runtime-resume before other device's
suspend methods run. This fixes the reading and writing back of 0xffffffff.
Since we now always runtime-resume the device on suspend, it will be
resumed on resume too and we no longer need to check for the GFX0 _PS0
method having resumed it underneath us, so this commit removes the now no
longer necessary complete dev_pm_op.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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K3 devices have the same ECAP IP as OMAP SoCs. Enable driver to be built
for K3 devices. Also, drop reference to AM33xx in help text, as IP is
found on multiple TI SoCs.
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This patch sends a uevent (KOBJ_CHANGE) on the pwmchipN device,
everytime a pwmX channel has been exported/unexported via sysfs. This
allows udev to implement rules on such events, like:
SUBSYSTEM=="pwm*", PROGRAM="/bin/sh -c '\
chown -R root:gpio /sys/class/pwm && chmod -R 770 /sys/class/pwm;\
chown -R root:gpio
/sys/devices/platform/soc/*.pwm/pwm/pwmchip* && chmod -R 770
/sys/devices/platform/soc/*.pwm/pwm/pwmchip*\
'"
This is a replacement patch for commit 7e5d1fd75c3d ("pwm: Set class for
exported channels in sysfs"), see [1].
basic testing:
$ udevadm monitor --environment &
$ echo 0 > /sys/class/pwm/pwmchip0/export
KERNEL[197.321736] change /devices/.../pwm/pwmchip0 (pwm)
ACTION=change
DEVPATH=/devices/.../pwm/pwmchip0
EXPORT=pwm0
SEQNUM=2045
SUBSYSTEM=pwm
[1] https://lkml.org/lkml/2018/9/25/713
Signed-off-by: Fabrice Gasnier <[email protected]>
Tested-by: Gottfried Haider <[email protected]>
Tested-by: Michal Vokáč <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This reverts commit 7e5d1fd75c3dde9fc10c4472b9368089d1b81d00 ("pwm: Set
class for exported channels in sysfs") as it causes regression with
multiple pwm chip[1], when exporting a pwm channel (echo X > export):
- ABI (Documentation/ABI/testing/sysfs-class-pwm) states pwmX should be
created in /sys/class/pwm/pwmchipN/pwmX
- Reverted patch causes new entry to be also created directly in
/sys/class/pwm/pwmX
- 1st time, exporting pwmX will create an entry in /sys/class/pwm/pwmX
- class attributes are added under pwmX folder, such as export, unexport
npwm, symlinks. This is wrong as it belongs to pwmchipN. It may cause
bad behavior and report wrong values.
- when another export happens on another pwmchip, it can't be created
(e.g. -EEXIST). This is causing the issue with multiple pwmchip.
Example on stm32 (stm32429i-eval) platform:
$ ls /sys/class/pwm
pwmchip0 pwmchip4
$ cd /sys/class/pwm/pwmchip0/
$ echo 0 > export
$ ls /sys/class/pwm
pwm0 pwmchip0 pwmchip4
$ cd /sys/class/pwm/pwmchip4/
$ echo 0 > export
sysfs: cannot create duplicate filename '/class/pwm/pwm0'
...Exception stack follows...
This is also seen on other platform [2]
[1] https://lkml.org/lkml/2018/9/25/713
[2] https://lkml.org/lkml/2018/9/25/447
Signed-off-by: Fabrice Gasnier <[email protected]>
Tested-by: Gottfried Haider <[email protected]>
Tested-by: Michal Vokáč <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add a get_state callback so that the initial state correctly reflects
the actual hardware state.
Cc: Andy Shevchenko <[email protected]>
Acked-by: Jani Nikula <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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For each pwm output which gets enabled through pwm_lpss_apply(), we do a
pm_runtime_get_sync().
This commit adds pm_runtime_put() calls to pwm_lpss_remove() to balance
these when the driver gets removed with some of the outputs still enabled.
Fixes: f080be27d7d9 ("pwm: lpss: Add support for runtime PM")
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The _PS0 method for the integrated graphics on some Cherry Trail devices
(observed on a HP Pavilion X2 10-p0XX) turns on the PWM chip (puts it in
D0), causing an inconsistency between the state the pm-core thinks it is
in (left runtime suspended as it was before the suspend/resume) and the
state it actually is in.
Interestingly enough this is done on a device where the pwm controller is
not used for the backlight at all, since it uses an eDP panel. On devices
where the PWM is used this is not a problem since we will resume it
ourselves anyways.
This inconsistency causes us to never suspend the pwm controller again,
which causes the device to not be able to reach S0ix states when suspended.
This commit adds a resume-complete handler, which when we think the device
is still run-time suspended checks the actual power-state and if necessary
updates the rpm-core's internal state.
This fixes the Pavilion X2 10-p0XX not reaching S0ix states when suspended.
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Move struct pwm_lpss_chip definition from pwm-lpss.c to pwm-lpss.h,
so that the pci/platform drivers can access the info member
(struct pwm_lpss_boardinfo *).
This is a preparation patch for adding platform specific quirks, which
the drivers need access to, to pwm_lpss_boardinfo.
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The second PWM controller on Cherry Trail devices uses a separate ACPI
HID: "80862289", add this so that the driver will properly bind to the
second PWM controller.
The second PWM controller is usually not used, the main thing gained by
this is properly putting the PWM controller in D3 on suspend.
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It's common to follow a device tree ID table by the MODULE_DEVICE_TABLE
immediately, without an extra blank line between.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add support for MT7628. The SoC is legacy MIPS and hence has no complex
clock tree. This patch add an extra flag to the SoC specific data
indicating, that no clocks are present.
Signed-off-by: John Crispin <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Current clock name looks like this:
/soc/bus@ffd00000/pwm@1b000#mux0
This is bad because CCF uses the clock to create a directory in clk debugfs.
With such name, the directory creation (silently) fails and the debugfs
entry end up being created at the debugfs root.
With this change, the clock name will now be:
ffd1b000.pwm#mux0
This matches the clock naming scheme used in the ethernet and mmc driver.
It also fixes the problem with debugfs.
Fixes: 36af66a79056 ("pwm: Convert to using %pOF instead of full_name")
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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LPTimer has only one pwm channel (npwm = 1). Remove useless for loop
in remove routine.
Signed-off-by: Fabrice Gasnier <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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If a pwm-omap-dmtimer is probed before the dmtimer it uses, the platform
data won't be set yet.
Fixes: ac30751df953 ("ARM: OMAP: pdata-quirks: Remove unused timer pdata")
Cc: <[email protected]> # 4.17+
Signed-off-by: David Rivshin <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Tested-by: Pavel Machek <[email protected]>
Acked-by: Ladislav Michl <[email protected]>
Tested-by: Andreas Kemnade <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Enabled the support for the new SoC i.MX8QM by adding the compatible
string of "fsl,imx8qm-ftm-pwm" and its per-compatible data with setting
"has_enable_bits" to "true".
Signed-off-by: Shenwei Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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On the i.MX8x SoC family, an additional PWM enable bit is added for each
PWM channel in the register FTM_SC[23:16]. It supports 8 channels. Bit
16 is for channel 0, and bit 23 is for channel 7. As the IP version
information can not be obtained via any of the FTM registers, a property
of "has_enable_bits" is added via per-compatible data structure.
Signed-off-by: Shenwei Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The current driver assumes that the ftm_sys clock works as one of the
clock sources for the IP block as well as the IP interface clock. This
assumption does not apply any more on the latest i.MX8x SoC family. On
i.MX8x SoCs, a dedicated IP interface clock is introduced and it must be
enabled before accessing any FTM registers. Moreover, the clock can not
be used as the source clock for the FTM IP block. This patch introduces
the ipg_clk as the dedicated IP interface clock and by default it is the
same as the ftm_sys clock if not specified.
Signed-off-by: Shenwei Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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pwm-tiehrpwm driver disables PWM output by putting it in low output
state via active AQCSFRC register in ehrpwm_pwm_disable(). But, the
AQCSFRC shadow register is not updated. Therefore, when shadow AQCSFRC
register is re-enabled in ehrpwm_pwm_enable() (say to enable second PWM
output), previous settings are lost as shadow register value is loaded
into active register. This results in things like PWMA getting enabled
automatically, when PWMB is enabled and vice versa. Fix this by
updating AQCSFRC shadow register as well during ehrpwm_pwm_disable().
Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Cc: [email protected]
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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As per AM335x TRM SPRUH73P "15.2.2.11 ePWM Behavior During Emulation",
TBCTL[15:14] only have effect during emulation suspend events (IOW,
to stop PWM when debugging using a debugger). These bits have no effect
on PWM output during normal running of system. Hence, remove code
accessing these bits as they have no role in enabling/disabling PWMs.
Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Cc: [email protected]
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The Berlin PWM driver is currently broken on at least BG2CD. The
symptoms manifest as a very non-linear and erratic mapping from the duty
cycle configured in software to the duty cycle produced by hardware.
The cause of the bug is software's configuration of the prescaler, and
in particular its usage of the six prescaler values between the minimum
value of 1 and the maximum value of 4096. As it turns out, these six
values do not actually slow down the PWM clock; rather, they emulate
slowing down the clock by internally multiplying the value of TCNT.
This would be a fine trick, if not for the fact that the internal,
scaled TCNT value has no extra bits beyond the 16 already exposed to
software in the register. What this means is that, for a prescaler of 4,
the software must ensure that the top two bits of TCNT are not set,
because hardware will chop them off; for a prescaler of 8, the top three
bits must not be set, and so forth. Software does not currently ensure
this, resulting in a TCNT several orders of magnitude lower than
intended any time one of those six prescalers are selected.
Because hardware chops off the high bits in its internal shift, the
middle six prescalers don't actually allow *anything* that the first
doesn't. In fact, they are strictly worse than the first, since the
internal shift of TCNT prevents software from setting the low bits,
decreasing the resolution, without providing any extra high bits.
By skipping the useless prescalers entirely, this patch both fixes the
driver's behavior and increases its performance (since, when the 4096
prescaler is selected, it now does only a single shift rather than the
seven successive divisions it did before).
Tested on BG2CD.
Signed-off-by: Thomas Hebb <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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