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The rk3328 SoC supports atomic update, we could lock the configuration
of period and duty at first, after unlock is configured, the period and
duty are effective at the same time.
If the polarity, period and duty need to be configured together,
the way for atomic update is "configure lock and old polarity" ->
"configure period and duty" -> "configure unlock and new polarity".
Signed-off-by: David Wu <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Just use the same PWM ops for each IP, and get rid of the ops in struct
rockchip_pwm_data, but still define the three different instances of the
struct to use common interface for each IP.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It is usually possible to configure the polarity, cycle and duty all at
once, so that the polarity and cycle and duty are applied atomically.
Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as
well as prepare for the next atomic update commit.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and
pwm_apply_v2() instead.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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It seems the rockchip_pwm_config() always returns the result 0, so
remove the judge.
Signed-off-by: David Wu <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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New PWM module provides two individual clocks for APB clock and function
clock.
Signed-off-by: David Wu <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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If the PWM was not enabled at U-Boot loader, PWM could not work for
clock always disabled at PWM driver. The PWM clock is enabled at
beginning of pwm_apply(), but disabled at end of pwm_apply().
If the PWM was enabled at U-Boot loader, PWM clock is always enabled
unless closed by ATF. The pwm-backlight might turn off the power at
early suspend, should disable PWM clock for saving power consume.
It is important to provide opportunity to enable/disable clock at PWM
driver, the PWM consumer should ensure correct order to call PWM enable
and disable, and PWM driver ensure state of PWM clock synchronized with
PWM enabled state.
Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update")
Cc: [email protected]
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement the ->apply() function to add support for atomic update.
Signed-off-by: Boris Brezillon <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Tested-by: Brian Norris <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The current logic will disable the PWM clk even if the PWM was left
enabled by the bootloader (because it's controlling a critical device
like a regulator for example).
Keep the PWM clk enabled if the PWM is enabled to avoid any glitches.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Tested-by: Brian Norris <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Implement the ->get_state() function to expose initial state.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Tested-by: Brian Norris <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The current implementation always round down the duty and period values,
while it would be better to round them to the closest integer.
These changes are needed in preparation of atomic update support to
prevent a period/duty cycle drift when executing several times the
'pwm_get_state() / modify / pwm_apply_state()' sequence.
Say you have an expected period of 3.333 us and a clk rate of
112.666667 MHz -- the clock frequency doesn't divide evenly, so the
period (stashed in nanoseconds) shrinks when we convert to the register
value and back, as follows:
pwm_apply_state(): register = period * 112666667 / 1000000000;
pwm_get_state(): period = register * 1000000000 / 112666667;
or in other words:
period = period * 112666667 / 1000000000 * 1000000000 / 112666667;
which yields a sequence like:
3333 -> 3328
3328 -> 3319
3319 -> 3310
3310 -> 3301
3301 -> 3292
3292 -> ... (etc) ...
With this patch, we'd see instead:
period = div_round_closest(period * 112666667, 1000000000) *
1000000000 / 112666667;
which yields a stable sequence:
3333 -> 3337
3337 -> 3337
3337 -> ... (etc) ...
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Tested-by: Brian Norris <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Use the pwm_get_xxx() helpers instead of directly accessing the fields
in struct pwm_device. This will allow us to smoothly move to the atomic
update approach.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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The rk3288 has the ability to invert the polarity of the PWM. Let's
enable that ability. Note that this increases pwm_cells to 3 for
rk3288.
Signed-off-by: Doug Anderson <[email protected]>
Reviewed-by: Caesar Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This patch added to support the PWM controller found on
RK3288 SoC.
Signed-off-by: Caesar Wang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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This commit adds a driver for the PWM controller found on Rockchip
RK29, RK30 and RK31 SoCs.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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