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atmel_pwm_config() calls clk_get_rate() which might sleep, so we need to
set pwm_chip can_sleep flag.
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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From the datasheet, the actual duty cycle is:
(period - (1 / clk) * CDTY) / period
This actually correct the polarity of the PWM and solves the issue that
pwm-leds exhibits: when setting a duty cycle of 0 and then disabling a
channel, the level was wrong (1 when the polarity was normal and 0 when
the polarity was inversed).
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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When atmel_pwm_config() calculates and then sets the prescaler, it is
overwriting the channel's CMR register so we are losing the CPOL
configuration.
As atmel_pwm_config() is always called before enabling a channel,
inverting the polarity doesn't work.
Fix that by reading CMR first and only overwriting the prescaler bits.
Signed-off-by: Alexandre Belloni <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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When the PWM controller is registered successfully, the clock can not
unprepare, so fix it.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add a PWM framework driver for the PWM controller found on Atmel SoCs.
Signed-off-by: Bo Shen <[email protected]>
Acked-by: Alexandre Belloni <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
[thierry.reding: coding style and other minor cleanups]
Signed-off-by: Thierry Reding <[email protected]>
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