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2024-06-18platform/x86/intel-uncore-freq: Use uncore_index with read_control_freqTero Kristo4-34/+45
Use the enumerated index for selecting the uncore driver parameter to read, instead of reading everything. This is done in preparation to expand the API to access more parameters later. No functional change intended. Signed-off-by: Tero Kristo <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ij: Removed underscores from variable names] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-18platform/x86/intel-uncore-freq: Get rid of magic min_max argumentTero Kristo4-21/+30
Get rid of the hardcoded / magic min_max argument from internal APIs. Instead, use an enumerated index value for it. No functional change intended. Signed-off-by: Tero Kristo <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-18platform/x86/intel-uncore-freq: Get rid of magic valuesTero Kristo1-8/+14
Get rid of any magic bitmasks from the code. Define proper macros for these, and use the bitfield operations to access them. No functional change intended. Signed-off-by: Tero Kristo <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-18platform/x86/intel-uncore-freq: Re-arrange bit masksTero Kristo1-11/+14
Rename the various bitmasks from the 'UNCORE_GENMASK_*' to 'UNCORE_*_MASK', and re-order them based on the register they reside in. No functional change intended. Signed-off-by: Tero Kristo <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-12platform/x86/intel/ifs: Switch to new Intel CPU model definesTony Luck1-8/+7
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Reviewed-by: Jithu Joseph <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel: chtwc_int33fe: Use 2-argument strscpy()Andy Shevchenko1-3/+3
Use 2-argument strscpy(), which is not only shorter but also provides an additional check that destination buffer is an array. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel_speed_select_if: Switch to new Intel CPU model definesTony Luck1-1/+1
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel-uncore-freq: Switch to new Intel CPU model definesTony Luck1-28/+28
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel_turbo_max_3: Switch to new Intel CPU model definesTony Luck1-2/+2
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86: intel_telemetry: Switch to new Intel CPU model definesTony Luck2-4/+4
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-06-03platform/x86/intel/pmc: Switch to new Intel CPU model definesTony Luck2-31/+31
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <[email protected]> Acked-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86/intel/tpmi/plr: Add support for the plr mailboxTero Kristo1-4/+153
Add support for reading fine grained power limit reasons via the PLR mailbox. Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86/intel/tpmi: Add new auxiliary driver for performance limitsTero Kristo3-0/+212
Add new auxiliary driver that exposes the SoC performance limit reasons via debugfs interface. Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86/intel: TPMI domain id and CPU mappingSrinivas Pandruvada4-0/+260
Each TPMI power domain includes a group of CPUs. Several power management settings in this case applicable to a group of CPUs. There can be several power domains in a CPU package. So, provide interfaces for: - Get power domain id for a Linux CPU - Get mask of Linux CPUs in a power domain Hardware Punit uses different CPU numbering, which is not based on APIC (Advanced Programmable Interrupt Controller) CPU numbering. The Linux CPU numbering is based on APIC CPU numbering. Some PM features like Intel Speed Select, the CPU core mask provided by the hardware is based on the Punit CPU numbering. To use the core mask, this mask needs to be converted to a Linux CPUs mask. So, provide interfaces for: - Convert to a Linux CPU number from a Punit CPU number - Convert to a Punit CPU number from a Linux CPU number On each CPU online, MSR 0x54 is used to read the mapping and stores in a per cpu array. Create a hash for faster searching of a Linux CPU number from a Punit CPU number. Signed-off-by: Srinivas Pandruvada <[email protected]> [tero.kristo: minor updates] Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86/intel/tpmi: Add API to get debugfs rootTero Kristo1-0/+9
Add new API to get the debugfs root directory for TPMI. This allows any TPMI devices to add their own debugfs items under the same directory structure. Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86/intel/tpmi: Add support for performance limit reasonsTero Kristo1-0/+2
Add TPMI ID 0x0C (Perf Limit Reasons) to the list of supported TPMI IDs. Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86: ISST: Use only TPMI interface when presentSrinivas Pandruvada1-0/+3
When the TPMI interface is present, use this interface instead of legacy. On some systems legacy IO device is also present. Using both interfaces together is confusing and may set the hardware in inconsistent state. When TPMI interface is present, don't load legacy drivers. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86: ISST: Avoid some SkyLake server modelsSrinivas Pandruvada3-4/+14
Some SkyLake server variants don't support any SST functionality. No use of providing any SST related interfaces on them. All supported SkyLake servers provide mailbox interface via MSR. So check for the presence of MSR 0xB0 and 0xB1. If not present don't load common module. Move defines for MSR_OS_MAILBOX_INTERFACE and MSR_OS_MAILBOX_DATA to common header file to avoid duplicating them. Signed-off-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-31platform/x86: ISST: Add model specific loading for common moduleSrinivas Pandruvada1-26/+37
SST common module is loaded when model specific or TPMI SST driver registers for services. There are model specific features used in SST common modules which are checked with a CPU model list. So, this module is model specific. There are some use cases where loading the common module independently only on the supported CPU models helps. The first use case is for preventing SST TPMI module loading if the model specific features are not implemented. The second use case for presenting information to user space when SST is used in OOB (Out of Band) mode. 1. With TPMI, SST interface is architectural. This means that no need to add new PCI device IDs for new CPU models. This means that there can be lag in adding CPU models for the model specific features in the common module. For example, before adding CPU model to GRANITERAPIDS_D to hpm_cpu_ids[], SST is still functional for some features and but will get/set wrong data for features like SST-CP. This is because IOCTL ISST_IF_GET_PHY_ID, will not give correct mapping for newer CPU models. So adding explicit model check during load time will prevent such cases. For unsupported CPU models, common driver will fail to load and hence dependent modules will not be loaded. 2. When the SST TPMI features are controlled by some OOB agent (not from OS interface), even if the CPU model is supported, there will be no user space interface available for tools as SST TPMI modules will not be loaded. User space interface is registered when TPMI modules call isst_if_cdev_register(). Even in this case user space orchestrator software needs to get power domain information to schedule workload and get/set turbo ratio limits. This information is exposed by the common module using IOCTLs ISST_IF_GET_PHY_ID and ISST_IF_MSR_COMMAND respectively. Since the user space MSR access can be locked, direct MSR access from the user space is not an option using /dev/cpu/*/msr. Converge all the existing model checks to one common place and use driver data to differentiate. On successful model check call isst_misc_reg(). Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-05-27platform/x86: ISST: fix use-after-free in tpmi_sst_dev_remove()Harshit Mogalapalli1-1/+1
In tpmi_sst_dev_remove(), tpmi_sst is dereferenced after being freed. Fix this by reordering the kfree() post the dereference. Fixes: 9d1d36268f3d ("platform/x86: ISST: Support partitioned systems") Signed-off-by: Harshit Mogalapalli <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Acked-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-05-16Merge tag 'platform-drivers-x86-v6.10-1' of ↵Linus Torvalds12-334/+772
git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 Pull x86 platform driver updates from Hans de Goede: - New drivers/platform/arm64 directory for arm64 embedded-controller drivers - New drivers: - Acer Aspire 1 embedded controllers (for arm64 models) - ACPI quickstart PNP0C32 buttons - Dell All-In-One backlight support (dell-uart-backlight) - Lenovo WMI camera buttons - Lenovo Yoga Tablet 2 Pro 1380F/L fast charging - MeeGoPad ANX7428 Type-C Cross Switch (power sequencing only) - MSI WMI sensors (fan speed sensors only for now) - Asus WMI: - 2024 ROG Mini-LED support - MCU powersave support - Vivobook GPU MUX support - Misc. other improvements - Ideapad laptop: - Export FnLock LED as LED class device - Switch platform profiles using thermal management key - Intel drivers: - IFS: various improvements - PMC: Lunar Lake support - SDSI: various improvements - TPMI/ISST: various improvements - tools: intel-speed-select: various improvements - MS Surface drivers: - Fan profile switching support - Surface Pro thermal sensors support - ThinkPad ACPI: - Reworked hotkey support to use sparse keymaps - Add support for new trackpoint-doubletap, Fn+N and Fn+G hotkeys - WMI core: - New WMI driver development guide - x86 Android tablets: - Lenovo Yoga Tablet 2 Pro 1380F/L support - Xiaomi MiPad 2 status LED and bezel touch buttons backlight support - Miscellaneous cleanups / fixes / improvements * tag 'platform-drivers-x86-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (128 commits) platform/x86: Add new MeeGoPad ANX7428 Type-C Cross Switch driver devm-helpers: Fix a misspelled cancellation in the comments tools arch x86: Add dell-uart-backlight-emulator platform/x86: Add new Dell UART backlight driver platform/x86: x86-android-tablets: Create LED device for Xiaomi Pad 2 bottom bezel touch buttons platform/x86: x86-android-tablets: Xiaomi pad2 RGB LED fwnode updates platform/x86: x86-android-tablets: Pass struct device to init() platform/x86/amd: pmc: Add new ACPI ID AMDI000B platform/x86/amd: pmf: Add new ACPI ID AMDI0105 platform/x86: p2sb: Don't init until unassigned resources have been assigned platform/surface: aggregator: Log critical errors during SAM probing platform/x86: ISST: Support SST-BF and SST-TF per level platform/x86/fujitsu-laptop: Replace sprintf() with sysfs_emit() tools/power/x86/intel-speed-select: v1.19 release tools/power/x86/intel-speed-select: Display CPU as None for -1 tools/power/x86/intel-speed-select: SST BF/TF support per level tools/power/x86/intel-speed-select: Increase number of CPUs displayed tools/power/x86/intel-speed-select: Present all TRL levels for turbo-freq tools/power/x86/intel-speed-select: Fix display for unsupported levels tools/power/x86/intel-speed-select: Support multiple dies ...
2024-05-13Merge branch 'acpi-bus'Rafael J. Wysocki2-2/+0
Merge changes related to _OSC handling and updates eliminating the owner field from struct acpi_driver: - Make the kernel indicate support for several ACPI features that are in fact supported to the platform firmware through _OSC and fix the Generic Initiator Affinity _OSC bit (Armin Wolf). - Make the ACPI core set the owner value for ACPI drivers, drop the owner setting from a number of drivers and eliminate the owner field from struct acpi_driver (Krzysztof Kozlowski). * acpi-bus: (24 commits) ACPI: drop redundant owner from acpi_driver virt: vmgenid: drop owner assignment ptp: vmw: drop owner assignment platform/x86/wireless-hotkey: drop owner assignment platform/x86/toshiba_haps: drop owner assignment platform/x86/toshiba_bluetooth: drop owner assignment platform/x86/toshiba_acpi: drop owner assignment platform/x86/sony-laptop: drop owner assignment platform/x86/lg-laptop: drop owner assignment platform/x86/intel/smartconnect: drop owner assignment platform/x86/intel/rst: drop owner assignment platform/x86/eeepc: drop owner assignment platform/x86/dell: drop owner assignment platform: classmate-laptop: drop owner assignment platform: asus-laptop: drop owner assignment platform/chrome: wilco_ec: drop owner assignment net: fjes: drop owner assignment Input: atlas - drop owner assignment ACPI: store owner from modules with acpi_bus_register_driver() ACPI: bus: Indicate support for IRQ ResourceSource thru _OSC ...
2024-05-01platform/x86: ISST: Support SST-BF and SST-TF per levelSrinivas Pandruvada1-7/+31
SST SST-BF and SST-TF can be enabled/disabled per SST-PP level. So return a mask of all levels, where the feature is supported, instead of just for level 0. Since the return value returns all levels mask, not just level 0, update API version. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Add Grand Ridge to HPM CPU listSrinivas Pandruvada1-0/+1
Add Grand Ridge (ATOM_CRESTMONT) to hpm_cpu_ids, so that MSR 0x54 can be used. Signed-off-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-29platform/x86:intel/pmc: Enable S0ix blocker show in Lunar LakeXi Pardee2-226/+261
Update Lunar Lake lpm maps to include S0ix blocker information. Add Lunar Lake blocker maps to enable S0ix blocker show in pmc core debugfs. Signed-off-by: Xi Pardee <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86:intel/pmc: Add support to show S0ix blocker counterXi Pardee2-0/+44
S0ix blocker counter is available in PWRM space. Add support to read and show S0ix blocker counter value through debugfs. Signed-off-by: Xi Pardee <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86:intel/pmc: Update LNL signal status mapXi Pardee2-1/+22
Update Lunar Lake signal status map. This status map has been updated since the map was merged. This patch updates the signal status map to the lastest version. Signed-off-by: Xi Pardee <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Add missing MODULE_DESCRIPTIONSrinivas Pandruvada2-0/+2
Add missing MODULE_DESCRIPTION() to ISST modules. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Add dev_fmtSrinivas Pandruvada1-0/+2
Add dev_fmt for formatting log messages. No functional impact is expected. Signed-off-by: Srinivas Pandruvada <[email protected]> Suggested-by: Andy Shevchenko <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Use in_range() to check package ID validitySrinivas Pandruvada1-2/+1
Use in_range() macro to simplify range check. No functional impact is expected. Signed-off-by: Srinivas Pandruvada <[email protected]> Suggested-by: Andy Shevchenko <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Support partitioned systemsSrinivas Pandruvada1-32/+267
A partitioned system has two different PCI VSEC devices per package. A non-partitioned device has only one PCI VSEC device per package. The current implementation only supports non partitioned systems. Each partition maps a set of power domains. Other than reading from different MMIO regions, there is no change in the SST functionality. The scope of SST control is still per power domain. Hence user space does not need to be aware of existence of partitions. With partitions, existing per package information defined using struct tpmi_sst_struct is enhanced to store information for both partitions. A mapping function map_partition_power_domain_id() is introduced, which maps to correct partition and index. This mapping function is called in get_instance() and isst_if_clos_assoc(), before indexing into tpmi_sst_struct->power_domain_info[]. The TPMI core platform info provides partition id and compute die ID mask for each partition. Use this information to order power domains, so that compute dies are presented before IO dies to match hardware defined compute die ID for each CPU. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Shorten the assignments for power_domain_infoSrinivas Pandruvada1-17/+16
Instead of long lines for assignment to tpmi_sst->power_domain_info, use a local variable pd_info and assign later. Also move the assignment of number of resources after the assignment of pd_info. No functional change is expected. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86: ISST: Use local variable for auxdev->devSrinivas Pandruvada1-13/+14
Define a local variable for &auxdev->dev and use to shorten length of lines. No functional change is done. Signed-off-by: Srinivas Pandruvada <[email protected]> Suggested-by: Andy Shevchenko <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/tpmi: Add additional TPMI header fieldsSrinivas Pandruvada1-1/+14
TPMI information header added additional fields in version 2. Some of the reserved fields in version 1 are used to define new fields. Parse new fields and export as part of platform data. These fields include: - PCI segment ID - Partition ID of the package: If a package is represented by more than one PCI device, then partition ID along with cdie_mask, describes the scope. For example to update get/set properties for a compute die, one of the PCI MMIO region is selected from the partition ID. - cdie_mask: Mask of all compute dies in this partition. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Zhang Rui <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/tpmi: Check major version change for TPMI InformationSrinivas Pandruvada1-4/+13
Check the major version from TPMI information header and fail to load driver if the version is not supported. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/tpmi: Handle error from tpmi_process_info()Srinivas Pandruvada1-2/+5
When tpmi_process_info() returns error, fail to load the driver. This can happen if call to ioremap() returns error. Signed-off-by: Srinivas Pandruvada <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Cc: [email protected] # v6.3+ Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/pmc: Fix PCH names in commentsColin Ian King2-2/+2
The PCH names in the pmc drivers are incorrect in the comments, fix these. Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel-uncore-freq: Don't present root domain on errorSrinivas Pandruvada1-0/+7
If none of the clusters are added because of some error, fail to load driver without presenting root domain. In this case root domain will present invalid data. Signed-off-by: Srinivas Pandruvada <[email protected]> Fixes: 01c10f88c9b7 ("platform/x86/intel-uncore-freq: tpmi: Provide cluster level control") Cc: <[email protected]> # 6.5+ Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/ifs: Disable irq during one load stageJithu Joseph1-0/+2
One of the stages in IFS image loading process involves loading individual chunks (test patterns) from test image file to secure memory. Driver issues a WRMSR(MSR_AUTHENTICATE_AND_COPY_CHUNK) operation to do this. This operation can take up to 5 msec, and if an interrupt occurs in between, the AUTH_AND_COPY_CHUNK u-code implementation aborts the operation. Interrupt sources such as NMI or SMI are handled by retrying. Regular interrupts may occur frequently enough to prevent this operation from ever completing. Disable irq on local cpu around the aforementioned WRMSR to allow the operation to complete. Signed-off-by: Jithu Joseph <[email protected]> Reviewed-by: Tony Luck <[email protected]> Reviewed-by: Ashok Raj <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-29platform/x86/intel/ifs: Classify error scenarios correctlyJithu Joseph1-12/+15
"Scan controller error" means that scan hardware encountered an error prior to doing an actual test on the target CPU. It does not mean that there is an actual cpu/core failure. "scan signature failure" indicates that the test result on the target core did not match the expected value and should be treated as a cpu failure. Current driver classifies both these scenarios as failures. Modify the driver to classify this situation with a more appropriate "untested" status instead of "fail" status. Signed-off-by: Jithu Joseph <[email protected]> Reviewed-by: Tony Luck <[email protected]> Reviewed-by: Ashok Raj <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Hans de Goede <[email protected]>
2024-04-16platform/x86/intel-uncore-freq: Increase minor number supportSrinivas Pandruvada1-2/+2
No new changes will be added for minor version 2. Change the minor version number to 2 and stop displaying log message for unsupported minor version 2. Signed-off-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-16platform/x86: ISST: Add Granite Rapids-D to HPM CPU listSrinivas Pandruvada1-0/+1
Add Granite Rapids-D to hpm_cpu_ids, so that MSR 0x54 can be used. Signed-off-by: Srinivas Pandruvada <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-15platform/x86/intel/sdsi: Add attribute to read the current meter stateDavid E. Box1-6/+24
The meter_certificate file provides access to metering information that may be attested but is only updated every 8 hours. Add new attribute, meter_current, to allow reading an untested snapshot of the current values. Signed-off-by: David E. Box <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-04-15platform/x86/intel/sdsi: Add in-band BIOS lock supportKuppuswamy Sathyanarayanan1-0/+10
As per SDSi in-band interface specification, sec titled "BIOS lock for in-band provisioning", when IB_LOCK bit is set in control qword, the SDSI agent is only allowed to perform the read flow, but not allowed to provision license blob or license key. So add check for it in sdsi_provision(). Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]> Signed-off-by: David E. Box <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-04-15platform/x86/intel/sdsi: Combine read and write mailbox flowsDavid E. Box1-35/+44
The current mailbox commands are either read-only or write-only and the flow is different for each. New commands will need to send and receive data. In preparation for these commands, create a common polling function to handle sending data and receiving in the same transaction. Signed-off-by: David E. Box <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-04-15platform/x86/intel/sdsi: Set message size during writesDavid E. Box1-0/+1
New mailbox commands will support sending multi packet writes and updated firmware now requires that the message size be written for all commands along with the packet size. Since the driver doesn't perform writes larger than the packet size, set the message size to the same value. Signed-off-by: David E. Box <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
2024-04-08platform/x86: intel-vbtn: Update tablet mode switch at end of probeGwendal Grignou1-2/+3
ACER Vivobook Flip (TP401NAS) virtual intel switch is implemented as follow: Device (VGBI) { Name (_HID, EisaId ("INT33D6") ... Name (VBDS, Zero) Method (_STA, 0, Serialized) // _STA: Status ... Method (VBDL, 0, Serialized) { PB1E |= 0x20 VBDS |= 0x40 } Method (VGBS, 0, Serialized) { Return (VBDS) /* \_SB_.PCI0.SBRG.EC0_.VGBI.VBDS */ } ... } By default VBDS is set to 0. At boot it is set to clamshell (bit 6 set) only after method VBDL is executed. Since VBDL is now evaluated in the probe routine later, after the device is registered, the retrieved value of VBDS was still 0 ("tablet mode") when setting up the virtual switch. Make sure to evaluate VGBS after VBDL, to ensure the convertible boots in clamshell mode, the expected default. Fixes: 26173179fae1 ("platform/x86: intel-vbtn: Eval VBDL after registering our notifier") Signed-off-by: Gwendal Grignou <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-08platform/x86: intel-vbtn: Use acpi_has_method to check for switchGwendal Grignou1-5/+1
The check for a device having virtual buttons is done using acpi_has_method(..."VBDL"). Mimic that for checking virtual switch presence. Signed-off-by: Gwendal Grignou <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-08platform/x86/intel/hid: Add Lunar Lake and Arrow Lake supportSumeet Pawnikar1-0/+2
Add INTC107B for Lunar Lake and INTC10CB for Arrow Lake ACPI devices IDs. Signed-off-by: Sumeet Pawnikar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>
2024-04-08platform/x86/intel/hid: Don't wake on 5-button releasesDavid McFarland1-1/+6
If, for example, the power button is configured to suspend, holding it and releasing it after the machine has suspended, will wake the machine. Also on some machines, power button release events are sent during hibernation, even if the button wasn't used to hibernate the machine. This causes hibernation to be aborted. Fixes: 0c4cae1bc00d ("PM: hibernate: Avoid missing wakeup events during hibernation") Signed-off-by: David McFarland <[email protected]> Tested-by: Enrik Berkhan <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ilpo Järvinen <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]>