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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.11
- Add support for the new RZ/V2H(P) (R9A09G057) Soc,
- Miscellaneous fixes and improvements.
Signed-off-by: Linus Walleij <[email protected]>
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A recent refactoring to use the func member in struct function_desc
missed converting one uses of name in keembay_build_functions(),
resulting in a build failure:
drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_build_functions':
drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no member named 'name'
1630 | if (!fdesc->name) {
| ^~
Perform the same conversion to resolve the build error.
Fixes: 73ee52205e5a ("pinctrl: keembay: Convert to use func member")
Signed-off-by: Nathan Chancellor <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/20240611-pinctrl-keembay-fix-func-conversion-v1-1-3197f2ded3f7@kernel.org
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Linus Walleij <[email protected]>
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The generic pinctrl-scmi.c driver could not be used for i.MX95 because
i.MX95 SCMI firmware not supports functions, groups or generic
'Pin Configuration Type and Enumerations' listed in SCMI Specification.
i.MX95 System Control Management Interface(SCMI) firmware only supports
below pin configuration types which are OEM specific types:
192: PIN MUX
193: PIN CONF
194: DAISY ID
195: DAISY VAL
To Support fsl,pins property together with SCMI OEM protocol, add this
driver.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Cristian Marussi <[email protected]>
Acked-by: Sudeep Holla <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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i.MX95 will have its own pinctrl scmi driver, so need block
pinctrl-scmi driver for i.MX95, otherwise there will be two pinctrl
devices for a single scmi protocol@19.
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Sudeep Holla <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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The PDC was hooked up as a wakeup parent in the DTS in
commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as
wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it
had no effect. Add the mapping for wakeup interrupts on the PDC to their
corresponding pins.
Configuring a pin IRQ as dual-edge would break it unless the
wakeirq_dual_edge_errata flag is set.
Signed-off-by: Richard Acayan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Use REGCACHE_MAPLE instead of REGCACHE_FLAT.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Instead of implementing a custom register paging mechanism in
the driver use the existing regmap ranges feature.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Currently there are 3 locks being used when accessing the chip, one
in the driver and one in each regmap. Reduce that to one driver only
lock that protects all regmap and regcache accesses.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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All drivers are converted to use embedded struct pinfunction.
Remove unused members from struct function_desc.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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struct function_desc is a particular version of the struct pinfunction
with associated opaque data. Start switching pin control core and
drivers to use it explicitly.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Add PINCTRL_FUNCTION_DESC() macro for inline use.
While at it, fix adjective form in the comment of PINCTRL_GROUP_DESC().
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Provide a helper macro to assign the struct function_desc entries.
This helps further refactoring.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Provide a helper macro to assign the struct function_desc entries.
This helps further refactoring.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Since pin control provides a generic data type for the pin function,
use it in the driver.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Since pin control provides a generic data type for the pin function,
use it in the driver.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Some of the rk3308 iomux routes in rk3308_mux_route_data belong to
the rk3308b SoC. Remove them and correct i2c3 routes.
Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support")
Signed-off-by: Dmitry Yashin <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Use pin numbers stored in the pin descriptors instead of index value while
creating the pin groups. Pin Id's are not same as Index values for Xilinx
Versal platform, so use the pin values from descriptor which works for both
ZynqMP and Versal platforms.
Signed-off-by: Swati Agarwal <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2413a1f99278d70313960f13daecda9ef54172d8.1716807432.git.michal.simek@amd.com
Signed-off-by: Linus Walleij <[email protected]>
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The current version of the pinctrl driver has some issues:
1. Duplicated "gpio" pmx function
The common code will add a "gpio" pmx functon to every pin group, so
it's not necessary to define a separate "gpio" pmx function in pin
groups.
2. Duplicated pmx function name
There are some same function name in different pin groups, which will
cause some problems. For example, when we want to use PAD_GPIO0 as
refclk output function, the common clk framework code will search the
entire pin function lists, then return the first one matched, in this
case the matched function list only include the PAD_CO_CLKO pin group
because there are three "refclk" pin function, which is added by
refclk_grp, spi_cs1_grp and gpio_grp.
To solve this problem, a simple way is just add a pingrp refix to
function name like mt7620 pinctrl driver does.
3. Useless "-" or "rsvd" functon
It's really unnecessary to add a reserved pin mux function to the
function lists, because we never use it.
Signed-off-by: Weihao Li <[email protected]>
Link: https://lore.kernel.org/r/20240527022036.31985-1-user@blabla
Signed-off-by: Linus Walleij <[email protected]>
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tps6594_muxval_remap as static to fix sparse warning
pinctrl: tps6594: Fix sparse warning.
warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static?
warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static?
Signed-off-by: Nirmala Devi Mal Nadar <[email protected]>
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com
Signed-off-by: Linus Walleij <[email protected]>
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PMC8380 is a new chip, featuring 10 GPIOs. Describe it.
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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We were not resetting the pointer to the associated gpio_device once
we are done displaying a pin's information.
This meant that once we reached the end of a gpio-range, if there
were pins right after it that did not belong to any known range,
they would be associated with the previous range's gpio device.
This resulted in those pins appearing as <4294966783:old_gdev> instead
of the expected <0:?> (due to gpio_num being -1).
Signed-off-by: Léo DUBOIN <[email protected]>
Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <[email protected]>
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We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges
struct for determining if a pin matched a GPIO number.
This value is present only if the 'pins' array is not NULL,
and is 0 otherwise. This means that GPIO ranges declared using
gpiochip_add_pingroup_range(), thus making use of pins, were always matched
by the pins in the range [0-npins] even if they contained pins in a
completely separate range.
Signed-off-by: Léo DUBOIN <[email protected]>
Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <[email protected]>
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Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.
Signed-off-by: Jacky Huang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Add NXP i.MX91 pinctrl driver
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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The SPMI GPIO driver assumes that the parent device is an SPMI device
and accesses random data when backcasting the parent struct device
pointer for non-SPMI devices.
Fortunately this does not seem to cause any issues currently when the
parent device is an I2C client like the PM8008, but this could change if
the structures are reorganised (e.g. using structure randomisation).
Notably the interrupt implementation is also broken for non-SPMI devices.
Also note that the two GPIO pins on PM8008 are used for interrupts and
reset so their practical use should be limited.
Drop the broken GPIO support for PM8008 for now.
Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008")
Cc: [email protected] # 5.13
Reviewed-by: Bryan O'Donoghue <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
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Add pinctrl driver support for RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock
in rzg2l_pinctrl_pm_setup_pfc() during PFC setup.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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In preparation for passing custom params for RZ/V2H(P) SoC assign the
custom params that are being passed via struct rzg2l_pinctrl_data.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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pinconf_generic_parse_dt_config()
Pass the pincontrol device pointer to pinconf_generic_parse_dt_config()
in preparation for passing custom params.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.
Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.
Value | RZ/G2L | RZ/V2H
---------------------------------
00b: | Bias Disabled | Pull up/down disabled
01b: | Pull-up | Pull up/down disabled
10b: | Pull-down | Pull-down
11b: | Prohibited | Pull-up
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add support to configure slew-rate property of the pin.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Introduce function pointers oen_read() and oen_write(), in the struct
rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before
writing to the PFC_OEN register is necessary, and the PFC_OEN register
has more bits compared to the RZ/G2L family. To handle these
differences between RZ/G2L and RZ/V2H(P) and to reuse the existing code
for RZ/V2H(P), these function pointers are introduced.
Additionally, populate these function pointers with appropriate data for
existing SoCs.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Introduces pmc_writeb() function pointer, in the struct
rzg2l_pinctrl_data to facilitate writing to the PMC register. On the
RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC
registers is required, whereas this is not the case for the existing
RZ/G2L family. This addition enables the reuse of existing code for
RZ/V2H(P). Additionally, populate this function pointer with
appropriate data for existing SoCs.
Note that this functionality is only handled in rzg2l_gpio_request(), as
PMC unlock/lock during PFC setup will be taken care of in the
pwpr_pfc_lock_unlock() function pointer.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
writing to both PFC and PMC registers. Additionally, BIT(7) B0WI is
undocumented for the PWPR register on RZ/V2H(P) SoC. To accommodate these
differences across SoC variants, introduce the pwpr_pfc_lock_unlock()
function pointer.
Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false)
is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is
now called after PMC read/write this is to keep changes minimal for
RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
resulting in invalid register offsets. Ensure that the register offsets
are valid before any read/write operations are performed. If the power
registers are not available, both SD and ETH will be set to '0'.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Enable parsing of variable configuration for all architectures. This
prepares for adding support for the RZ/V2H SoC, which utilizes the ARM64
architecture and features port pins with variable configuration.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Drop the rzg2l_variable_pin_cfg struct and instead use the
RZG2L_VARIABLE_PIN_CFG_PACK() macro for the variable pin configuration.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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The pin configuration bits have been growing for every new SoCs being
added for the pinctrl-rzg2l driver which would mean updating the macros
every time for each new configuration. To avoid this allocate additional
bits for pin configuration by relocating the known fixed bits to the very
end of the configuration.
Also update the size of 'cfg' to 'u64' to allow more configuration bits
in the 'struct rzg2l_variable_pin_cfg'.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Use the scoped variant of for_each_child_of_node() to simplify the code.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/c0a28f466c42d5d59c7fadfa1fd05fd512d43b6f.1717060708.git.geert+renesas@glider.be
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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On PREEMPT_RT kernels the spinlock_t maps to an rtmutex. Using
raw_spin_lock_irqsave()/raw_spin_unlock_irqrestore() on
&pctrl->lock.rlock breaks the PREEMPT_RT builds. To fix this use
spin_lock_irqsave()/spin_unlock_irqrestore() on &pctrl->lock.
Fixes: 02cd2d3be1c3 ("pinctrl: renesas: rzg2l: Configure the interrupt type on resume")
Reported-by: Diederik de Haas <[email protected]>
Closes: https://lore.kernel.org/all/131999629.KQPSlr0Zke@bagend
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Device Support:
- Add support for X-Powers AXP717 PMIC to AXP22X
- Add support for Rockchip RK816 PMIC to RK8XX
- Add support for TI TPS65224 PMIC to TPS6594
New Functionality:
- Add Power Off functionality to Rohm BD71828
- Allow I2C SMBus access in Renesas RSMU
Fix-ups:
- Device Tree binding adaptions/conversions/creation
- Shift Intel support over to MSI interrupts
- Generify adding platform data away from being ACPI specific
- Use device core supplied attribute to register sysfs entries
- Replace hand-rolled functionality with generic APIs
- Utilise centrally provided helpers and macros
- Clean-up error handling
- Remove superfluous/duplicated/unused sections
- Trivial; spelling, whitespace, coding-style adaptions
- More Maple Tree conversions"
* tag 'mfd-next-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (44 commits)
dt-bindings: mfd: Use full path to other schemas
mfd: rsmu: support I2C SMBus access
dt-bindings: mfd: Convert lp873x.txt to json-schema
dt-bindings: mfd: aspeed: Drop 'oneOf' for pinctrl node
dt-bindings: mfd: allwinner,sun6i-a31-prcm: Use hyphens in node names
mfd: ssbi: Remove unused field 'slave' from 'struct ssbi'
mfd: kempld: Remove custom DMI matching code
mfd: cs42l43: Update patching revision check
dt-bindings: mfd: qcom: pm8xxx: Add pm8901 compatible
mfd: timberdale: Remove redundant assignment to variable err
dt-bindings: mfd: qcom,spmi-pmic: Add pbs to SPMI device types
dt-bindings: mfd: syscon: Add ti,am62p-cpsw-mac-efuse compatible
dt-bindings: mfd: qcom,tcsr: Add compatible for SDX75
mfd: axp20x: Convert to use Maple Tree register cache
mfd: bd71828: Remove commented code lines
mfd: intel-m10-bmc: Change staging size to a variable
dt-bindings: mfd: Add ROHM BD71879
mfd: Tidy Kconfig dependency's parentheses
mfd: ocelot-spi: Use spi_sync_transfer()
dt-bindings: mfd: syscon: Add missing simple syscon compatibles
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Use DEFINE_SHOW_STORE_ATTRIBUTE() in debugfs entries
New drivers:
- Qualcomm PMIH0108, PMD8028, PMXR2230 and PM6450 pin control support
Improvements:
- Serious cleanup of the recently merged aw9523 driver
- Fix PIN_CONFIG_BIAS_DISABLE handling in pinctrl-single
- A slew of device tree binding cleanups
- Support a bus clock in the Samsung driver"
* tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: bcm2835: Make pin freeing behavior configurable
dt-bindings: pinctrl: qcom,pmic-gpio: Fix "comptaible" typo for PMIH0108
pinctrl: qcom: pinctrl-sm7150: Fix sdc1 and ufs special pins regs
dt-bindings: pinctrl: mediatek: mt7622: add "antsel" function
dt-bindings: pinctrl: mediatek: mt7622: fix array properties
pinctrl: samsung: drop redundant drvdata assignment
pinctrl: samsung: support a bus clock
dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock
pinctrl: renesas: rzg2l: Limit 2.5V power supply to Ethernet interfaces
pinctrl: renesas: r8a779h0: Add INTC-EX pins, groups, and function
pinctrl: renesas: r8a779h0: Fix IRQ suffixes
pinctrl: renesas: rzg2l: Remove extra space in function parameter
dt-bindings: pinctrl: qcom,pmic-mpp: add support for PM8901
pinctrl: pinconf-generic: print hex value
pinctrl: realtek: fix module autoloading
pinctrl: qcom: sm7150: fix module autoloading
pinctrl: loongson2: fix module autoloading
pinctrl: mediatek: fix module autoloading
pinctrl: freescale: imx8ulp: fix module autoloading
dt-bindings: pinctrl: qcom,pmic-gpio: Allow gpio-hog nodes
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git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski
"This was a quiet release cycle for the GPIO tree and so this
pull-request is relatively small.
We have one new driver, some minor improvements to the GPIO core code
and across several drivers, some DT and documentation updates but in
general nothing stands out or is controversial. All changes have spent
time in next with no reported issues (or ones that were quickly
fixed).
GPIO core:
- remove more unused legacy interfaces (after converting the last
remaining users to better alternatives)
- update kerneldocs
- improve error handling and log messages in GPIO ACPI code
- remove dead code (always true checks) from GPIOLIB
New drivers:
- add a driver for Intel Granite Rapids-D vGPIO
Driver improvements:
- use -ENOTSUPP consistently in gpio-regmap and gpio-pcie-idio-24
- provide an ID table for gpio-cros-ec to avoid a driver name
fallback check
- add support for gpio-ranges for GPIO drivers supporting multiple
GPIO banks
- switch to using dynamic GPIO base in gpio-brcmstb
- fix irq handling in gpio-npcm-sgpio
- switch to memory mapped IO accessors in gpio-sch
DT bindings:
- add support for gpio-ranges to gpio-brcmstb
- add support for a new model and the gpio-line-names property to
gpio-mpfs
Documentation:
- replace leading tabs with spaces in code blocks
- fix typos"
* tag 'gpio-updates-for-v6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (30 commits)
gpio: nuvoton: Fix sgpio irq handle error
gpiolib: Discourage to use formatting strings in line names
gpio: brcmstb: add support for gpio-ranges
gpio: of: support gpio-ranges for multiple gpiochip devices
dt-bindings: gpio: brcmstb: add gpio-ranges
gpio: Add Intel Granite Rapids-D vGPIO driver
gpio: brcmstb: Use dynamic GPIO base numbers
gpiolib: acpi: Set label for IRQ only lines
gpiolib: acpi: Add fwnode name to the GPIO interrupt label
gpiolib: Get rid of never false gpio_is_valid() calls
gpiolib: acpi: Pass con_id instead of property into acpi_dev_gpio_irq_get_by()
gpiolib: acpi: Move acpi_can_fallback_to_crs() out of __acpi_find_gpio()
gpiolib: acpi: Simplify error handling in __acpi_find_gpio()
gpiolib: acpi: Extract __acpi_find_gpio() helper
gpio: sch: Utilise temporary variable for struct device
gpio: sch: Switch to memory mapped IO accessors
gpio: regmap: Use -ENOTSUPP consistently
gpio: pcie-idio-24: Use -ENOTSUPP consistently
Documentation: gpio: Replace leading TABs by spaces in code blocks
gpiolib: acpi: Check for errors first in acpi_find_gpio()
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