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2024-06-17pinctrl: add missing MODULE_DESCRIPTION() macrosJeff Johnson14-0/+14
When ARCH=x86, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/bcm/pinctrl-bcm4908.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_i2c.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_spi.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/meson/pinctrl-meson.o Add the missing invocation of the MODULE_DESCRIPTION() macro to all files which have a MODULE_LICENSE(). This includes many meson drivers which, although they did not produce a warning with the x86 allmodconfig configuration, may cause this warning with ARM or ARM64 configurations. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> # for Amlogic Pinctrl drivers Link: https://lore.kernel.org/r/20240610-md-drivers-pinctrl-v1-1-68462e3d960c@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: zynqmp: Support muxing individual pinsSean Anderson1-29/+54
While muxing groups of pins at once can be convenient for large interfaces, it can also be rigid. This is because the group is set to all pins which support a particular function, even though not all pins may be used. For example, the sdhci0 function may be used with a 8-bit eMMC, 4-bit SD card, or even a 1-bit SD card. In these cases, the extra pins may be repurposed for other uses, but this is not currently allowed. There is not too much point in pin "groups" when there are not actual pin groups at the hardware level. The pins can all be muxed individually, so there's no point in adding artificial groups on top. Just mux the pins like the hardware allows. To this effect, add a new group for each pin which can be muxed. These groups are part of each function the pin can be muxed to. We treat group selectors beyond the number of groups as "pin" groups. To set this up, we initialize groups before functions, and then create a bitmap of used pins for each function. These used pins are appended to the function's list of groups. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240610223550.2449230-3-sean.anderson@linux.dev Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: rockchip: fix pinmux reset in rockchip_pmx_setHuang-Huang Bao1-1/+3
rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error, add missing bank data retrieval in that code to avoid setting mux on unexpected pins. Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Huang-Huang Bao <i@eh5.me> Link: https://lore.kernel.org/r/20240606125755.53778-5-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: rockchip: use dedicated pinctrl type for RK3328Huang-Huang Bao2-1/+5
rk3328_pin_ctrl uses type of RK3288 which has a hack in rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6 at assume, the hack is not applicable to RK3328 as GPIO6 is not even exist in it. So use a dedicated pinctrl type to skip this hack. Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Huang-Huang Bao <i@eh5.me> Link: https://lore.kernel.org/r/20240606125755.53778-4-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pinsHuang-Huang Bao1-0/+51
The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for these pins can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 Add pinmux data to rk3328_mux_recalced_data as mux register offset for these pins does not follow rockchip convention. Signed-off-by: Huang-Huang Bao <i@eh5.me> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") Link: https://lore.kernel.org/r/20240606125755.53778-3-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pinsHuang-Huang Bao1-7/+1
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is recalculated so it remain unchanged. The pinmux bits for those pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5 GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5 GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5 GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5 GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5 GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5 GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5 This fix has been tested on NanoPi R2S for fixing confliting pinmux bits between GPIO2-B7 with GPIO2-B5. Signed-off-by: Huang-Huang Bao <i@eh5.me> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") Link: https://lore.kernel.org/r/20240606125755.53778-2-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: ti: ti-iodelay: fix possible memory leak when pinctrl_enable() failsYang Yingliang1-5/+6
This driver calls pinctrl_register_and_init() which is not devm_ managed, it will leads memory leak if pinctrl_enable() fails. Replace it with devm_pinctrl_register_and_init(). And add missing of_node_put() in the error path. Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-4-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: single: fix possible memory leak when pinctrl_enable() failsYang Yingliang1-3/+4
This driver calls pinctrl_register_and_init() which is not devm_ managed, it will leads memory leak if pinctrl_enable() fails. Replace it with devm_pinctrl_register_and_init(). And call pcs_free_resources() if pinctrl_enable() fails. Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-3-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: core: fix possible memory leak when pinctrl_enable() failsYang Yingliang1-1/+11
In devm_pinctrl_register(), if pinctrl_enable() fails in pinctrl_register(), the "pctldev" has not been added to dev resources, so devm_pinctrl_dev_release() can not be called, it leads memory leak. Introduce pinctrl_uninit_controller(), call it in the error path to free memory. Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-2-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: fix deadlock in create_pinctrl() when handling -EPROBE_DEFERHagar Hemdan1-1/+1
In create_pinctrl(), pinctrl_maps_mutex is acquired before calling add_setting(). If add_setting() returns -EPROBE_DEFER, create_pinctrl() calls pinctrl_free(). However, pinctrl_free() attempts to acquire pinctrl_maps_mutex, which is already held by create_pinctrl(), leading to a potential deadlock. This patch resolves the issue by releasing pinctrl_maps_mutex before calling pinctrl_free(), preventing the deadlock. This bug was discovered and resolved using Coverity Static Analysis Security Testing (SAST) by Synopsys, Inc. Fixes: 42fed7ba44e4 ("pinctrl: move subsystem mutex to pinctrl_dev struct") Suggested-by: Maximilian Heyne <mheyne@amazon.de> Signed-off-by: Hagar Hemdan <hagarhem@amazon.com> Link: https://lore.kernel.org/r/20240604085838.3344-1-hagarhem@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: bcm2835: Use string_choices API instead of ternary operatorStefan Wahren1-2/+3
Use modern string_choices API instead of manually determining the output using ternary operator. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20240603181938.76047-3-wahrenst@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: bcm2835: Fix permissions of persist_gpio_outputsStefan Wahren1-1/+1
The commit 8ff05989b44e ("pinctrl: bcm2835: Make pin freeing behavior configurable") unintentionally made the module parameter persist_gpio_outputs changeable at runtime. So drop the write permission in order to make the freeing behavior predictable for user applications. Fixes: 8ff05989b44e ("pinctrl: bcm2835: Make pin freeing behavior configurable") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Closes: https://lore.kernel.org/linux-gpio/Zjk-C0nLmlynqLAE@surfacebook.localdomain/ Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20240603181938.76047-2-wahrenst@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: tps6594: add missing support for LP8764 PMICThomas Richard1-0/+1
Add missing support for LP8764 PMIC in the probe(). Issue detected with v6.10-rc1 (and reproduced with 6.10-rc2) using a TI J7200 EVM board. tps6594-pinctrl tps6594-pinctrl.8.auto: error -EINVAL: Couldn't register gpio_regmap driver tps6594-pinctrl tps6594-pinctrl.8.auto: probe with driver tps6594-pinctrl failed with error -22 Fixes: 208829715917 (pinctrl: pinctrl-tps6594: Add TPS65224 PMIC pinctrl and GPIO) Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240603082110.2104977-1-thomas.richard@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17Merge tag 'renesas-pinctrl-for-v6.11-tag1' of ↵Linus Walleij5-217/+619
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.11 - Add support for the new RZ/V2H(P) (R9A09G057) Soc, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: keembay: Fix func conversion in keembay_build_functions()Nathan Chancellor1-1/+1
A recent refactoring to use the func member in struct function_desc missed converting one uses of name in keembay_build_functions(), resulting in a build failure: drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_build_functions': drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no member named 'name' 1630 | if (!fdesc->name) { | ^~ Perform the same conversion to resolve the build error. Fixes: 73ee52205e5a ("pinctrl: keembay: Convert to use func member") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240611-pinctrl-keembay-fix-func-conversion-v1-1-3197f2ded3f7@kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406131133.WwdetfBL-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: imx: support SCMI pinctrl protocol for i.MX95Peng Fan3-0/+367
The generic pinctrl-scmi.c driver could not be used for i.MX95 because i.MX95 SCMI firmware not supports functions, groups or generic 'Pin Configuration Type and Enumerations' listed in SCMI Specification. i.MX95 System Control Management Interface(SCMI) firmware only supports below pin configuration types which are OEM specific types: 192: PIN MUX 193: PIN CONF 194: DAISY ID 195: DAISY VAL To Support fsl,pins property together with SCMI OEM protocol, add this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-3-9a1175d735fd@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: scmi: add blocklistPeng Fan1-0/+9
i.MX95 will have its own pinctrl scmi driver, so need block pinctrl-scmi driver for i.MX95, otherwise there will be two pinctrl devices for a single scmi protocol@19. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-2-9a1175d735fd@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: qcom: sdm670: add pdc wakeirq mapRichard Acayan1-0/+19
The PDC was hooked up as a wakeup parent in the DTS in commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it had no effect. Add the mapping for wakeup interrupts on the PDC to their corresponding pins. Configuring a pin IRQ as dual-edge would break it unless the wakeirq_dual_edge_errata flag is set. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20240523230619.256882-2-mailingradian@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: cy8c95x0: Use REGCACHE_MAPLEPatrick Rudolph1-1/+1
Use REGCACHE_MAPLE instead of REGCACHE_FLAT. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240521152602.1097764-3-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: cy8c95x0: Use regmap rangesPatrick Rudolph1-126/+53
Instead of implementing a custom register paging mechanism in the driver use the existing regmap ranges feature. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240521152602.1097764-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: cy8c95x0: Use single I2C lockPatrick Rudolph1-15/+17
Currently there are 3 locks being used when accessing the chip, one in the driver and one in each regmap. Reduce that to one driver only lock that protects all regmap and regcache accesses. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240521152602.1097764-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: pinmux: Remove unused members from struct function_descAndy Shevchenko1-9/+0
All drivers are converted to use embedded struct pinfunction. Remove unused members from struct function_desc. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-12-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: mediatek: moore: Convert to use func memberAndy Shevchenko2-8/+6
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-11-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: keembay: Convert to use func memberAndy Shevchenko1-11/+11
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-10-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: ingenic: Convert to use func memberAndy Shevchenko1-9/+7
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-9-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: imx: Convert to use func memberAndy Shevchenko1-7/+7
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-8-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: pinmux: Embed struct pinfunction into struct function_descAndy Shevchenko2-6/+9
struct function_desc is a particular version of the struct pinfunction with associated opaque data. Start switching pin control core and drivers to use it explicitly. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-7-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: pinmux: Add a convenient define PINCTRL_FUNCTION_DESC()Andy Shevchenko3-8/+14
Add PINCTRL_FUNCTION_DESC() macro for inline use. While at it, fix adjective form in the comment of PINCTRL_GROUP_DESC(). Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-6-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: mediatek: moore: Provide a helper macro PINCTRL_PIN_FUNCTION()Andy Shevchenko6-76/+84
Provide a helper macro to assign the struct function_desc entries. This helps further refactoring. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-5-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: ingenic: Provide a helper macro INGENIC_PIN_FUNCTION()Andy Shevchenko1-345/+352
Provide a helper macro to assign the struct function_desc entries. This helps further refactoring. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-4-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: equilibrium: Make use of struct pinfunctionAndy Shevchenko2-23/+13
Since pin control provides a generic data type for the pin function, use it in the driver. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-3-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: berlin: Make use of struct pinfunctionAndy Shevchenko2-18/+9
Since pin control provides a generic data type for the pin function, use it in the driver. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240530085745.1539925-2-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: rockchip: update rk3308 iomux routesDmitry Yashin1-15/+2
Some of the rk3308 iomux routes in rk3308_mux_route_data belong to the rk3308b SoC. Remove them and correct i2c3 routes. Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support") Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240515121634.23945-2-dmt.yashin@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: pinctrl-zynqmp: Use pin numbers stored in pin descriptorSwati Agarwal1-1/+1
Use pin numbers stored in the pin descriptors instead of index value while creating the pin groups. Pin Id's are not same as Index values for Xilinx Versal platform, so use the pin values from descriptor which works for both ZynqMP and Versal platforms. Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2413a1f99278d70313960f13daecda9ef54172d8.1716807432.git.michal.simek@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: ralink: mt76x8: fix pinmux functionWeihao Li1-61/+27
The current version of the pinctrl driver has some issues: 1. Duplicated "gpio" pmx function The common code will add a "gpio" pmx functon to every pin group, so it's not necessary to define a separate "gpio" pmx function in pin groups. 2. Duplicated pmx function name There are some same function name in different pin groups, which will cause some problems. For example, when we want to use PAD_GPIO0 as refclk output function, the common clk framework code will search the entire pin function lists, then return the first one matched, in this case the matched function list only include the PAD_CO_CLKO pin group because there are three "refclk" pin function, which is added by refclk_grp, spi_cs1_grp and gpio_grp. To solve this problem, a simple way is just add a pingrp refix to function name like mt7620 pinctrl driver does. 3. Useless "-" or "rsvd" functon It's really unnecessary to add a reserved pin mux function to the function lists, because we never use it. Signed-off-by: Weihao Li <cn.liweihao@gmail.com> Link: https://lore.kernel.org/r/20240527022036.31985-1-user@blabla Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: pinctrl-tps6594: make tps65224_muxval_remap and ↵Nirmala Devi Mal Nadar1-2/+2
tps6594_muxval_remap as static to fix sparse warning pinctrl: tps6594: Fix sparse warning. warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static? warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static? Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405111523.9yt759uX-lkp@intel.com/ Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: qcom: spmi: Add PMC8380Konrad Dybcio1-0/+1
PMC8380 is a new chip, featuring 10 GPIOs. Describe it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: core: reset gpio_device in loop in pinctrl_pins_show()Léo DUBOIN1-0/+1
We were not resetting the pointer to the associated gpio_device once we are done displaying a pin's information. This meant that once we reached the end of a gpio-range, if there were pins right after it that did not belong to any known range, they would be associated with the previous range's gpio device. This resulted in those pins appearing as <4294966783:old_gdev> instead of the expected <0:?> (due to gpio_num being -1). Signed-off-by: Léo DUBOIN <lduboin@freebox.fr> Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: core: take into account the pins array in pinctrl_pins_show()Léo DUBOIN1-4/+13
We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges struct for determining if a pin matched a GPIO number. This value is present only if the 'pins' array is not NULL, and is 0 otherwise. This means that GPIO ranges declared using gpiochip_add_pingroup_range(), thus making use of pins, were always matched by the pins in the range [0-npins] even if they contained pins in a completely separate range. Signed-off-by: Léo DUBOIN <lduboin@freebox.fr> Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driverJacky Huang5-0/+3059
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and add support for ma35d1 pinctrl. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Link: https://lore.kernel.org/r/20240521012447.42211-4-ychuang570808@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: st: Use scope based of_node_put() cleanupsPeng Fan1-26/+11
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-8-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: stm32: Use scope based of_node_put() cleanupsPeng Fan1-3/+1
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-3-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: imx: Add pinctrl driver support for i.MX91Peng Fan3-0/+279
Add NXP i.MX91 pinctrl driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240513-imx91-pinctrl-v1-2-c99a23c6843a@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: qcom: spmi-gpio: drop broken pm8008 supportJohan Hovold1-1/+0
The SPMI GPIO driver assumes that the parent device is an SPMI device and accesses random data when backcasting the parent struct device pointer for non-SPMI devices. Fortunately this does not seem to cause any issues currently when the parent device is an I2C client like the PM8008, but this could change if the structures are reorganised (e.g. using structure randomisation). Notably the interrupt implementation is also broken for non-SPMI devices. Also note that the two GPIO pins on PM8008 are used for interrupts and reset so their practical use should be limited. Drop the broken GPIO support for PM8008 for now. Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008") Cc: stable@vger.kernel.org # 5.13 Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240529162958.18081-9-johan+linaro@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-11pinctrl: renesas: rzg2l: Add support for RZ/V2H SoCLad Prabhakar1-3/+371
Add pinctrl driver support for RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-11pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc()Lad Prabhakar1-0/+3
To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock in rzg2l_pinctrl_pm_setup_pfc() during PFC setup. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Link: https://lore.kernel.org/r/20240530173857.164073-15-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-11pinctrl: renesas: rzg2l: Add support for custom parametersLad Prabhakar1-0/+12
In preparation for passing custom params for RZ/V2H(P) SoC assign the custom params that are being passed via struct rzg2l_pinctrl_data. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240530173857.164073-14-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-11pinctrl: renesas: rzg2l: Pass pincontrol device to ↵Lad Prabhakar1-1/+1
pinconf_generic_parse_dt_config() Pass the pincontrol device pointer to pinconf_generic_parse_dt_config() in preparation for passing custom params. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Link: https://lore.kernel.org/r/20240530173857.164073-13-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-11pinctrl: renesas: rzg2l: Add support for pull-up/downLad Prabhakar1-0/+72
Add support to configure bias-disable, bias-pull-up, and bias-pull-down properties of the pin. Two new function pointers, hw_to_bias_param() and bias_param_to_hw(), are introduced in the struct rzg2l_pinctrl_data to configure bias settings, as the values in the PUPD register differ when compared to the RZ/G2L family and the RZ/V2H(P) SoC. Value | RZ/G2L | RZ/V2H --------------------------------- 00b: | Bias Disabled | Pull up/down disabled 01b: | Pull-up | Pull up/down disabled 10b: | Pull-down | Pull-down 11b: | Prohibited | Pull-up Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-11pinctrl: renesas: rzg2l: Add support to configure slew-rateLad Prabhakar1-0/+18
Add support to configure slew-rate property of the pin. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240530173857.164073-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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