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2023-08-15Merge patch series "Introduce Intel Tangier pinctrl driver"Andy Shevchenko7-1277/+778
Raag Jadav <[email protected]> says: Merrifield and Moorefield pinctrl driver implementations are similar in terms of how they access the hardware. We can consolidate their pinctrl functionalities into a common library driver. This patch set introduces: 1. Intel Tangier driver that supports the common pinctrl functionalities for Merrifield and Moorefield platforms. 2. Intel Tangier adaptation for Merrifield pinctrl driver. 3. Intel Tangier adaptation for Moorefield pinctrl driver. Tested on Intel Edison platform. No deviation observed in the contents of below entries before and after this patchset. - /proc/interrupts - /sys/kernel/debug/gpio - /sys/kernel/debug/pinctrl/*/pins Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]>
2023-08-15pinctrl: moorefield: Adapt to Intel Tangier driverRaag Jadav3-622/+37
Make use of Intel Tangier as a library driver for Moorefield. Signed-off-by: Raag Jadav <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]>
2023-08-15pinctrl: merrifield: Adapt to Intel Tangier driverRaag Jadav3-655/+41
Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Raag Jadav <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]>
2023-08-15pinctrl: tangier: Introduce Intel Tangier driverRaag Jadav5-0/+700
Intel Tangier implements the common pinctrl functionalities for Merrifield and Moorefield platforms. Signed-off-by: Raag Jadav <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]>
2023-08-15pinctrl: baytrail: consolidate common mask operationRaag Jadav1-19/+15
Consolidate common mask operation outside of switch cases and limit IO operations to positive cases. Signed-off-by: Raag Jadav <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
2023-08-15Merge tag 'qcom-pinctrl-6.6' of ↵Linus Walleij3-0/+178
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel Qualcomm pinctrl changes for v6.6 1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio SubSystem) TLMM pin controllers. 2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin controllers. Signed-off-by: Linus Walleij <[email protected]>
2023-08-15pinctrl: pinctrl-oxnas: remove obsolete pinctrl driverNeil Armstrong3-1303/+0
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Daniel Golle <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: qcom: Add intr_target_width field to support increased number of ↵Ninad Naik3-3/+9
interrupt targets SA8775 and newer target have added support for an increased number of interrupt targets. To implement this change, the intr_target field, which is used to configure the interrupt target in the interrupt configuration register is increased from 3 bits to 4 bits. In accordance to these updates, a new intr_target_width member is introduced in msm_pingroup structure. This member stores the value of width of intr_target field in the interrupt configuration register. This value is used to dynamically calculate and generate mask for setting the intr_target field. By default, this mask is set to 3 bit wide, to ensure backward compatibility with the older targets. Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms") Tested-by: Andrew Halaney <[email protected]> # sa8775p-ride Signed-off-by: Ninad Naik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: nsp-gpio: Silence probe deferral messagesFlorian Fainelli1-4/+2
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Dhruva Gole <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: iproc-gpio: Silence probe deferral messagesFlorian Fainelli1-4/+2
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Dhruva Gole <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: single: Add compatible for ti,am654-padconfTony Lindgren1-2/+9
Use the "ti,am654-padconf" compatible to enable the use of wake-up enable and event bits on K3 SOCs that support the daisychain feature Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Dhruva Gole <[email protected]> Link: https://lore.kernel.org/r/[email protected] [Alphabetized the compatible list] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: stm32: set default gpio line names using pin namesValentin Caron1-0/+35
Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin descriptor which is matching with a gpio. Most of the time pin number is equal to pin index in array. So the first part of the function is useful to speed up. And during gpio bank register, we set default gpio names with pin names. Signed-off-by: Valentin Caron <[email protected]> Acked-by: Alexandre TORGUE <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: stmfx: Do not check for 0 return after calling platform_get_irq()Ruan Jinjie1-2/+2
Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk"), there is no possible for platform_get_irq() to return 0. Use the return value from platform_get_irq(). Signed-off-by: Ruan Jinjie <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: at91-pio4: drop useless check in atmel_conf_pin_config_dbg_show()Sergey Shtylyov1-4/+3
In atmel_conf_pin_config_dbg_show(), checking atmel_pioctrl->pins[pin_id] against being NULL doesn't make any sense as it gets derefenced first and the driver's probe() method immediately returns -ENOMEM when devm_kzalloc() returns NULL for any atmel_pioctrl->pins[] element anyway, thus failing to register the device... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-10pinctrl: mcp23s08: check return value of devm_kasprintf()Claudiu Beznea1-0/+10
devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 0f04a81784fe ("pinctrl: mcp23s08: Split to three parts: core, I²C, SPI") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-07pinctrl: Replace the IRQ number in the driver with the IRQID macro definitionHuqiang Qin1-17/+18
Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin <[email protected]> Acked-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-07pinctrl: qcom: Remove the unused _groups variable build warningSricharan Ramabadhran1-10/+0
When building with clang toolchain and arm64-randconfig-r015-20230712 kernel test robot reports the below warning. drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable] static const char * const _groups[] = { ^ 1 warning generated. static const char * const _groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", }; Fixing it by removing the variable. Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by: Sricharan Ramabadhran <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-07pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio3-0/+185
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-07pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high impedanceSai Krishna Potthuri1-0/+9
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. Using these pinctrl properties observed hang issues with older PMUFW(Xilinx ZynqMP Platform Management Firmware), hence reverted the patch. Commit 9989bc33c4894e075167 ("Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance""). Support for configuring these properties added in PMUFW Configuration Set version 2.0. When there is a request for these configurations from pinctrl driver for ZynqMP platform, xilinx firmware driver checks for this version before configuring these properties to avoid the hang issue and proceeds further only when firmware version is >=2 otherwise it returns error. Signed-off-by: Sai Krishna Potthuri <[email protected]> Reviewed-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-08-03Merge tag 'renesas-pinctrl-for-v6.6-tag1' of ↵Linus Walleij2-70/+50
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.6 - Use the new devm_clk_get_enabled() helper. Signed-off-by: Linus Walleij <[email protected]>
2023-07-28pinctrl: pinmux: handle radix_tree_insert() errors in ↵Sergey Shtylyov1-2/+4
pinmux_generic_add_function() pinctrl_generic_add_function() doesn't check result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-28pinctrl: core: handle radix_tree_insert() errors in pinctrl_register_one_pin()Sergey Shtylyov1-3/+11
pinctrl_register_one_pin() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-28pinctrl: core: handle radix_tree_insert() errors in pinctrl_generic_add_group()Sergey Shtylyov1-2/+4
pinctrl_generic_add_group() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-26pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio3-0/+185
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-07-25pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helperChristophe JAILLET1-27/+5
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by: Christophe JAILLET <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-07-25pinctrl: renesas: rzv2m: Use devm_clk_get_enabled() helperGeert Uytterhoeven1-27/+5
Simplify clock handling by using the devm_clk_get_enabled() helper, instead of open-coding the same operations. Move the clock pointer from the driver-private data to a local variable, as it is not needed outside the .probe() callback. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/cca0b1795fd0335401bdf2be393ab84445e04095.1688396836.git.geert+renesas@glider.be
2023-07-24pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMMKrzysztof Kozlowski3-0/+178
Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-07-23pinctrl: amd: Don't show `Invalid config param` errorsMario Limonciello1-2/+2
On some systems amd_pinconf_set() is called with parameters 0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE) which are not supported by pinctrl-amd. Don't show an err message when called with an invalid parameter, downgrade this to debug instead. Cc: [email protected] # 6.1 Fixes: 635a750d958e1 ("pinctrl: amd: Use amd_pinconf_set() for all config options") Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-23pinctrl: Add driver support for Amlogic C3 SoCsHuqiang Qin3-0/+1115
Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-20pinctrl: Explicitly include correct DT includesRob Herring107-145/+80
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Acked-by: Emil Renner Berthing <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-20pinctrl: qcom: lpass-lpi: Make the clocks optional, alwaysKonrad Dybcio1-5/+1
Some platforms provide a single clock source to all LPASS peripherals, others provide two, and there are probably others that provide it through magic invisible-to-Linux wires. Rely on bindings to mandate the adequate number of clocks necessary. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-20pinctrl: tegra: Add support to display pin functionPrathamesh Shete2-2/+19
The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete <[email protected]> Acked-by: Thierry Reding <[email protected]> Reviewed-by: Jon Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-20pinctrl: sunxi: Add some defensiveness for regulators arrayMark Brown1-0/+3
The sunxi pinctrl has a fixed size array it uses to store regulators used in the driver. There is currently nothing that ensures that the number of elements in the array is large enough to map the regulators defined by the individual SoCs. While this is currently the case having an explicit check in there will make life easier for anyone debugging memory issues that manifest in the driver so let's add one. Signed-off-by: Mark Brown <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-20pinctrl: cy8c95x0: Add reset supportPatrick Rudolph1-0/+15
This patch adds support for an optional "reset" GPIO pin in the cy8c95x0 pinctrl driver. On probe, the reset pin is pulled low to bring chip out of reset. The reset pin has an internal pull-down and can be left floating if not required. The datasheet doesn't mention any timing related to the reset pin. Based on empirical tests, it was found that the chip requires a delay of 250 milliseconds before accepting I2C transfers after driving the reset pin low. Therefore, a delay of 250ms is added before proceeding with I2C transfers. Signed-off-by: Patrick Rudolph <[email protected]> Signed-off-by: Naresh Solanki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: ti: Convert to devm_platform_get_and_ioremap_resource()Yangtao Li1-9/+2
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: pic32: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: mvebu: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-2/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: berlin: as370: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-2/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: qcom-pmic-gpio: Add support for pmx75Rohit Agarwal1-0/+1
pmx75 pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-16pinctrl: qcom-pmic-gpio: Add support for pm7550baRohit Agarwal1-0/+1
pm7550ba pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-13Merge tag 'renesas-pinctrl-fixes-for-v6.5-tag1' of ↵Linus Walleij2-16/+40
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into fixes pinctrl: renesas: Fixes for v6.5 - Fix handling of non-unique pin control configuration subnode names on the RZ/V2M and RZ/G2L SoC families. Signed-off-by: Linus Walleij <[email protected]>
2023-07-13pinctrl: amd: Unify debounce handling into amd_pinconf_set()Mario Limonciello1-16/+5
Debounce handling is done in two different entry points in the driver. Unify this to make sure that it's always handled the same. Tested-by: Jan Visser <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-13pinctrl: amd: Drop pull up select configurationMario Limonciello2-13/+4
pinctrl-amd currently tries to program bit 19 of all GPIOs to select either a 4kΩ or 8hΩ pull up, but this isn't what bit 19 does. Bit 19 is marked as reserved, even in the latest platforms documentation. Drop this programming functionality. Tested-by: Jan Visser <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-13pinctrl: amd: Use amd_pinconf_set() for all config optionsMario Limonciello1-13/+15
On ASUS TUF A16 it is reported that the ITE5570 ACPI device connected to GPIO 7 is causing an interrupt storm. This issue doesn't happen on Windows. Comparing the GPIO register configuration between Windows and Linux bit 20 has been configured as a pull up on Windows, but not on Linux. Checking GPIO declaration from the firmware it is clear it *should* have been a pull up on Linux as well. ``` GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) { // Pin list 0x0007 } ``` On Linux amd_gpio_set_config() is currently only used for programming the debounce. Actually the GPIO core calls it with all the arguments that are supported by a GPIO, pinctrl-amd just responds `-ENOTSUPP`. To solve this issue expand amd_gpio_set_config() to support the other arguments amd_pinconf_set() supports, namely `PIN_CONFIG_BIAS_PULL_DOWN`, `PIN_CONFIG_BIAS_PULL_UP`, and `PIN_CONFIG_DRIVE_STRENGTH`. Reported-by: Nik P <[email protected]> Reported-by: Nathan Schulte <[email protected]> Reported-by: Friedrich Vock <[email protected]> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217336 Reported-by: [email protected] Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217493 Link: https://lore.kernel.org/linux-input/[email protected]/ Tested-by: Jan Visser <[email protected]> Fixes: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-13pinctrl: amd: Only use special debounce behavior for GPIO 0Mario Limonciello1-3/+5
It's uncommon to use debounce on any other pin, but technically we should only set debounce to 0 when working off GPIO0. Cc: [email protected] Tested-by: Jan Visser <[email protected]> Fixes: 968ab9261627 ("pinctrl: amd: Detect internal GPIO0 debounce handling") Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-10pinctrl: renesas: rzg2l: Handle non-unique subnode namesBiju Das1-8/+20
Currently, sd1 and sd0 have unique subnode names 'sd1_mux' and 'sd0_mux'. If we change these to non-unique subnode names such as 'mux' this can lead to the below conflict as the RZ/G2L pin control driver considers only the names of the subnodes. pinctrl-rzg2l 11030000.pinctrl: pin P47_0 already requested by 11c00000.mmc; cannot claim for 11c10000.mmc pinctrl-rzg2l 11030000.pinctrl: pin-376 (11c10000.mmc) status -22 pinctrl-rzg2l 11030000.pinctrl: could not request pin 376 (P47_0) from group mux on device pinctrl-rzg2l renesas_sdhi_internal_dmac 11c10000.mmc: Error applying setting, reverse things back Fix this by constructing unique names from the node names of both the pin control configuration node and its child node, where appropriate. Based on the work done by Geert for the RZ/V2M pinctrl driver. Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-07-10pinctrl: renesas: rzv2m: Handle non-unique subnode namesGeert Uytterhoeven1-8/+20
The eMMC and SDHI pin control configuration nodes in DT have subnodes with the same names ("data" and "ctrl"). As the RZ/V2M pin control driver considers only the names of the subnodes, this leads to conflicts: pinctrl-rzv2m b6250000.pinctrl: pin P8_2 already requested by 85000000.mmc; cannot claim for 85020000.mmc pinctrl-rzv2m b6250000.pinctrl: pin-130 (85020000.mmc) status -22 renesas_sdhi_internal_dmac 85020000.mmc: Error applying setting, reverse things back Fix this by constructing unique names from the node names of both the pin control configuration node and its child node, where appropriate. Reported by: Fabrizio Castro <[email protected]> Fixes: 92a9b825257614af ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Fabrizio Castro <[email protected]> Link: https://lore.kernel.org/r/607bd6ab4905b0b1b119a06ef953fa1184505777.1688396717.git.geert+renesas@glider.be
2023-06-30Merge tag 'pinctrl-v6.5-1' of ↵Linus Torvalds94-7231/+10986
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time New drivers: - Tegra234 support - Qualcomm IPQ5018 support - Intel Meteor Lake-S support - Qualcomm SDX75 subdriver - Qualcomm SPMI-based PM8953 support Improvements: - Fix up support for GPIO3 on the AXP209 - Push-pull drive configuration support for the AT91 PIO4 - Fix misc non-urgent bugs in the AMD driver - Misc non-urgent improved error handling - Misc janitorial and minor improvements" * tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: cherryview: Drop goto label pinctrl: baytrail: invert if condition pinctrl: baytrail: add warning for BYT_VAL_REG retrieval failure pinctrl: baytrail: reduce scope of spinlock in ->dbg_show() hook pinctrl: tegra: avoid duplicate field initializers dt-bindings: pinctrl: qcom,sdx65-tlmm: add pcie_clkreq function pinctrl: mlxbf3: remove broken Kconfig 'select' pinctrl: spear: Remove unused of_gpio.h inclusion pinctrl: lantiq: Remove unused of_gpio.h inclusion pinctrl: at91-pio4: check return value of devm_kasprintf() pinctrl: microchip-sgpio: check return value of devm_kasprintf() pinctrl: freescale: Fix a memory out of bounds when num_configs is 1 pinctrl: intel: refine ->irq_set_type() hook pinctrl: intel: refine ->set_mux() hook pinctrl: baytrail: Use str_hi_lo() helper lib/string_choices: Add str_high_low() helper lib/string_helpers: Split out string_choices.h lib/string_helpers: Add missing header files to MAINTAINERS database pinctrl: npcm7xx: Add missing check for ioremap pinctrl:sunplus: Add check for kmalloc ...
2023-06-29Merge tag 'soc-newsoc-6.5' of ↵Linus Torvalds4-0/+2591
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new ARM SoC support from Arnd Bergmann: "There are two new SoC families this time, and both appear fairly similar: The Nuvoton MA35D1 and the STMicroelectronics STM32MP2 are both dual-core Cortex-A35 based chips for the low-power industrial embedded market, and they mark the first 64-bit product in a widely used family of 32-bit Arm MCUs and SoCs. The way into the kernel is completely different here: The team at ST has a long history of working upstream with their STM32MP1 and other SoCs, and they produced a complete port to arm64 together with the initial announcement. Nuvoton also has multiple SoC product lines with current or previous upstream support, but those are maintained by third parties and are unrelated. The patch series from Nuvoton's Jacky Huang had to go through many revisisions to get to this point and is still missing a few drivers including the serial port for the moment. The branch contains the devicetree files as well as all the code changes, in order to have something that can be tested standalone" * tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) clk: nuvoton: Use clk_parent_data instead of string for parent clock clk: nuvoton: Update all constant hex values to lowercase clk: nuvoton: Add clk-ma35d1.h for driver extern functions remoteproc: stm32: use correct format strings on 64-bit MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE arm64: defconfig: enable ARCH_STM32 and STM32 serial driver arm64: dts: st: add stm32mp257f-ev1 board support dt-bindings: stm32: document stm32mp257f-ev1 board arm64: dts: st: introduce stm32mp25 pinctrl files arm64: dts: st: introduce stm32mp25 SoCs family arm64: introduce STM32 family on Armv8 architecture dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon pinctrl: stm32: add stm32mp257 pinctrl support dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Documentation/process: add soc maintainer handbook reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35 reset: Add Nuvoton ma35d1 reset driver support clk: nuvoton: Add clock driver for ma35d1 clock controller arm64: dts: nuvoton: Add initial ma35d1 device tree dt-bindings: serial: Document ma35d1 uart controller ...
2023-06-28Merge tag 'regulator-v6.5' of ↵Linus Torvalds2-22/+169
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator Pull regulator updates from Mark Brown: "This release is almost all drivers, there's some small improvements in the core but otherwise everything is updates to drivers, mostly the addition of new ones. There's also a bunch of changes pulled in from the MFD subsystem as dependencies, Rockchip and TI core MFD code that the regulator drivers depend on. I've also yet again managed to put a SPI commit in the regulator tree, I don't know what it is about those two trees (this for spi-geni-qcom). Summary: - Support for Renesas RAA215300, Rockchip RK808, Texas Instruments TPS6594 and TPS6287x, and X-Powers AXP15060 and AXP313a" * tag 'regulator-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: (43 commits) regulator: Add Renesas PMIC RAA215300 driver regulator: dt-bindings: Add Renesas RAA215300 PMIC bindings regulator: ltc3676: Use maple tree register cache regulator: ltc3589: Use maple tree register cache regulator: helper: Document ramp_delay parameter of regulator_set_ramp_delay_regmap() regulator: mt6358: Use linear voltage helpers for single range regulators regulator: mt6358: Const-ify mt6358_regulator_info data structures regulator: mt6358: Drop *_SSHUB regulators regulator: mt6358: Merge VCN33_* regulators regulator: dt-bindings: mt6358: Drop *_sshub regulators regulator: dt-bindings: mt6358: Merge ldo_vcn33_* regulators regulator: dt-bindings: pwm-regulator: Add missing type for "pwm-dutycycle-unit" regulator: Switch two more i2c drivers back to use .probe() spi: spi-geni-qcom: Do not do DMA map/unmap inside driver, use framework instead soc: qcom: geni-se: Add interfaces geni_se_tx_init_dma() and geni_se_rx_init_dma() regulator: tps6594-regulator: Add driver for TI TPS6594 regulators regulator: axp20x: Add AXP15060 support regulator: axp20x: Add support for AXP313a variant dt-bindings: pfuze100.yaml: Add an entry for interrupts regulator: stm32-pwr: Fix regulator disabling ...
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