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2023-12-04pinctrl: amd: Mask non-wake source pins with interrupt enabled at suspendMario Limonciello2-0/+14
If a pin isn't marked as a wake source processing any interrupts is just going to destroy battery life. The APU may wake up from a hardware sleep state to process the interrupt but not return control to the OS. Mask interrupt for all non-wake source pins at suspend. They'll be re-enabled at resume. Reported-and-tested-by: Marcus Aram <marcus+oss@oxar.nl> Reported-and-tested-by: Mark Herbert <mark.herbert42@gmail.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2812 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20231203032431.30277-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: pinctrl-single: add ti,j7200-padconf compatibleThomas Richard1-0/+5
On j7200, during suspend to ram pinctrl contexts are lost. To save and restore contexts during suspend/resume, the flag PCS_CONTEXT_LOSS_OFF shall be set. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20231128-j7200-pinctrl-s2r-v1-2-704e7dc24460@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: qcom: fail to retrieve configuration from invalid pin groupsRichard Acayan1-0/+4
The pinconf-groups debugfs file dumps each valid configuration item of all pin groups. Some platforms and devices may have pin groups which cannot be accessed, according to commit 691bf5d5a7bf ("pinctrl: qcom: Don't allow protected pins to be requested"). Fail for each configuration item of an invalid pin group by checking the GPIO chip's valid mask. The validity of the pin group cannot be checked in the generic pinconf dump (function "pinconf_generic_dump_one"), as it does not directly interact with the gpiochip or the pinmux callbacks (which would give it access to the request callback). Instead, an entry contains the ID and name of the pingroup with no properties when all items fail. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231128020202.728156-3-mailingradian@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: mediatek: Switch to use no-IRQ PM helpersAndy Shevchenko14-18/+16
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231122144744.2222207-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: Convert unsigned to unsigned intAndy Shevchenko10-95/+95
Simple type conversion with no functional change implied. While at it, adjust indentation where it makes sense. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-24-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: starfive: jh7100: ignore disabled device tree nodesNam Cao1-2/+2
The driver always registers pin configurations in device tree. This can cause some inconvenience to users, as pin configurations in the base device tree cannot be disabled in the device tree overlay, even when the relevant devices are not used. Ignore disabled pin configuration nodes in device tree. Fixes: ec648f6b7686 ("pinctrl: starfive: Add pinctrl driver for StarFive SoCs") Cc: <stable@vger.kernel.org> Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/fe4c15dcc3074412326b8dc296b0cbccf79c49bf.1701422582.git.namcao@linutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-04pinctrl: starfive: jh7110: ignore disabled device tree nodesNam Cao1-2/+2
The driver always registers pin configurations in device tree. This can cause some inconvenience to users, as pin configurations in the base device tree cannot be disabled in the device tree overlay, even when the relevant devices are not used. Ignore disabled pin configuration nodes in device tree. Fixes: 447976ab62c5 ("pinctrl: starfive: Add StarFive JH7110 sys controller driver") Cc: <stable@vger.kernel.org> Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/fd8bf044799ae50a6291ae150ef87b4f1923cacb.1701422582.git.namcao@linutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01pinctrl: imx: Use temporary variable to hold pinsAndy Shevchenko1-8/+9
The pins are allocated from the heap, but in order to pass them as constant object, we need to use non-constant pointer. Achieve this by using a temporary variable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01pinctrl: equilibrium: Use temporary variable to hold pinsAndy Shevchenko1-7/+6
The pins are allocated from the heap, but in order to pass them as constant object, we need to use non-constant pointer. Achieve this by using a temporary variable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01pinctrl: equilibrium: Unshadow error code of of_property_count_u32_elems()Andy Shevchenko1-3/+4
of_property_count_u32_elems() might return an error code in some cases. It's naturally better to assign what it's returned to the err variable and supply the real code to the upper layer(s). Besides that, it's a common practice to avoid assignments for the data in cases when we know that the error condition happened. Refactor the code accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01pinctrl: qcom: lpass-lpi: Remove unused member in struct lpi_pingroupAndy Shevchenko9-163/+0
The group is not used anywhere, remove it. And if needed, it should be struct pingroup anyway. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01pinctrl: qcom: lpass-lpi: Replace kernel.h with what is being usedAndy Shevchenko1-1/+1
Replace kernel.h with what exactly is being used, i.e. array_size.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231129161459.1002323-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-01Merge tag 'renesas-pinctrl-for-v6.8-tag1' of ↵Linus Walleij1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.8 - Add support for interrupt affinity to the RZ/G2L GPIO driver, - Drop unneeded quotes in the RZ/A2 Pin controller DT bindings. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-30pinctrl: samsung: add irq_set_affinity() for non wake up external gpio interruptYoungmin Nam1-0/+14
To support affinity setting for non wake up external gpio interrupt, add irq_set_affinity callback using irq number from pinctrl driver data. Before this patch, changing the irq affinity of gpio interrupt is not possible: # cat /proc/irq/418/smp_affinity 3ff # echo 00f > /proc/irq/418/smp_affinity # cat /proc/irq/418/smp_affinity 3ff # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 ... 418: 3631 0 0 0 ... With this patch applied, it's possible to change irq affinity of gpio interrupt: # cat /proc/irq/418/smp_affinity 3ff # echo 00f > /proc/irq/418/smp_affinity # cat /proc/irq/418/smp_affinity 00f # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 ... 418: 3893 201 181 188 ... Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231126094618.2545116-1-youngmin.nam@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-11-27pinctrl: renesas: rzg2l: Enhance driver to support interrupt affinity settingLad Prabhakar1-0/+1
Implement irq_set_affinity callback so that we can set affinity for GPIO IRQs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231011195923.67404-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-11-25pinctrl: don't include GPIOLIB private headerBartosz Golaszewski1-4/+1
gpio_to_desc() is declared in linux/gpio.h so there's no need to include gpiolib.h directly. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231115165001.2932350-4-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-25pinctrl: stop using gpiod_to_chip()Bartosz Golaszewski1-6/+7
Don't dereference struct gpio_chip directly, use dedicated gpio_device getters instead. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231115165001.2932350-3-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-24pinctrl: baytrail: Simplify code with cleanup helpersAndy Shevchenko1-108/+68
Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2023-11-24pinctrl: baytrail: Move default strength assignment to a switch-caseAndy Shevchenko1-8/+1
When ->pin_config_set() is called from the GPIO library (assumed GpioIo() ACPI resource), the argument can be 1, when, for example, PullDefault is provided. In such case we supply sane default in the driver. Move that default assingment to a switch-case, so it will be consolidated in one place. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2023-11-24pinctrl: baytrail: Factor out byt_gpio_force_input_mode()Andy Shevchenko1-21/+21
There is a piece of code that it being used at least twice. Factor it out. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2023-11-24pinctrl: baytrail: Fix types of config value in byt_pin_config_set()Andy Shevchenko1-1/+2
When unpacked, the config value is split to two of different types. Fix the types accordingly. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-24pinctrl: lynxpoint: Simplify code with cleanup helpersAndy Shevchenko1-51/+21
Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-24pinctrl: tangier: simplify locking using cleanup helpersRaag Jadav1-9/+7
Use lock guards from cleanup.h to simplify locking. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-24pinctrl: as3722: Use devm_gpiochip_add_data() to simplify remove pathAndrew Davis1-15/+2
Use devm version of gpiochip add function to handle removal for us. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231116223045.274211-1-afd@ti.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-24pinctrl: qcom: Add X1E80100 pinctrl driverRajendra Nayak3-0/+1887
Add initial pinctrl driver to support pin configuration with pinctrl framework for X1E80100 SoC. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-24pinctrl: npcm7xx: prevent glitch when setting the GPIO to output highTomer Maimon1-1/+1
Enable GPIO output after setting the output value to prevent a glitch when pinctrl driver sets gpio pin to output high and the pin is in the default state (high->low->high). Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: William A. Kennington III <william@wkennington.com> Link: https://lore.kernel.org/r/20231115211209.1683449-1-william@wkennington.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-24pinctrl: stm32: return errors from stm32_gpio_direction_output()Sergey Shtylyov1-2/+1
In the STMicroelectronics STM32 driver, stm32_gpio_direction_output() ignores the result of pinctrl_gpio_direction_output() for no good reason. Let's propagate errors from pinctrl_gpio_direction_output() upstream... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/5ce023a8-db0c-13a9-be42-09e3348ca44d@omp.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-24pinctrl: realtek: Fix logical error when finding descriptorTzuyi Chang1-2/+2
The pin descriptor should be returned if the name has been found in the descriptor table. Remove the negation in the if statement for accurate retrieval. Fixes: e99ce78030db ("pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCs") Signed-off-by: Tzuyi Chang <tychang@realtek.com> Link: https://lore.kernel.org/r/20231121091107.5564-1-tychang@realtek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-22pinctrl: intel: use the correct _PM_OPS() export macroRaag Jadav1-1/+1
Since we don't have runtime PM handles here, we should be using EXPORT_NS_GPL_DEV_SLEEP_PM_OPS() macro, so that the compiler can discard it in case CONFIG_PM_SLEEP=n. Fixes: b10a74b5c0c1 ("pinctrl: intel: Provide Intel pin control wide PM ops structure") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-16pinctrl: lochnagar: Don't build on MIPSCharles Keepax1-1/+2
MIPS appears to define a RST symbol at a high level, which clashes with some register naming in the driver. Since there is currently no case for running this driver on MIPS devices simply cut off the build of this driver on MIPS. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311071303.JJMAOjy4-lkp@intel.com/ Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20231115162853.1891940-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-15pinctrl: avoid reload of p state in list iterationMaria Yu1-3/+3
When in the list_for_each_entry iteration, reload of p->state->settings with a local setting from old_state will turn the list iteration into an infinite loop. The typical symptom when the issue happens, will be a printk message like: "not freeing pin xx (xxx) as part of deactivating group xxx - it is already used for some other setting". This is a compiler-dependent problem, one instance occurred using Clang version 10.0 on the arm64 architecture with linux version 4.19. Fixes: 6e5e959dde0d ("pinctrl: API changes to support multiple states per device") Signed-off-by: Maria Yu <quic_aiquny@quicinc.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20231115102824.23727-1-quic_aiquny@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: cy8c95x0: Fix doc warningLinus Walleij1-0/+1
One member of struct cy8c95x0_pinctrl is missing kerneldoc, which leads to warnings. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311031342.r4To3GaD-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231114-cy8c95x0-doc-v1-1-31674103ad18@linaro.org
2023-11-14pinctrl: tps6594: Add driver for TPS6594 pinctrl and GPIOsEsteban Blanc3-0/+390
TI TPS6594 PMIC has 11 GPIOs which can be used for different functions. This patch adds a pinctrl and GPIO drivers in order to use those functions. Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231108104124.2818275-1-eblanc@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: s32cc: Avoid possible string truncationChester Lin1-2/+2
With "W=1" and "-Wformat-truncation" build options, the kernel test robot found a possible string truncation warning in pinctrl-s32cc.c, which uses an 8-byte char array to hold a memory region name "map%u". Since the maximum number of digits that a u32 value can present is 10, and the "map" string occupies 3 bytes with a termination '\0', which means the rest 4 bytes cannot fully present the integer "X" that exceeds 4 digits. Here we check if the number >= 10000, which is the lowest value that contains more than 4 digits. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311030159.iyUGjNGF-lkp@intel.com/ Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20231107141044.24058-1-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: stm32: fix array read out of boundAntonio Borneo1-3/+5
The existing code does not verify if the "tentative" index exceeds the size of the array, causing out of bound read. Issue identified with kasan. Check the index before using it. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Fixes: 32c170ff15b0 ("pinctrl: stm32: set default gpio line names using pin names") Link: https://lore.kernel.org/r/20231107110520.4449-1-antonio.borneo@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: intel: Add a generic Intel pin control platform driverAndy Shevchenko3-0/+236
New generations of Intel platforms will provide better description of the pin control devices in the ACPI tables. Hence, we may provide a generic pin control platform driver to cover all of them. Currently the following Intel SoCs / platforms require this to be functional: - Lunar Lake Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-14pinctrl: intel: Revert "Unexport intel_pinctrl_probe()"Andy Shevchenko2-2/+6
In order to prepare for a new coming driver export the original intel_pinctrl_probe() again. This reverts commit 0dd519e3784b13befa1cdfeff847a0885b06650f. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-14pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config registerKrzysztof Kozlowski2-6/+21
Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231013145935.220945-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: qcom: lpass-lpi: split slew rate set to separate functionKrzysztof Kozlowski1-20/+33
Setting slew rate for each pin will grow with upcoming Qualcomm SoCs, so split the code responsible for this into separate function for easier readability and maintenance. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231013145935.220945-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: intel: allow independent COMPILE_TESTRaag Jadav1-1/+1
Now that we have completed the transition to standard ACPI helpers for the entire Intel pinctrl tree, we can detach COMPILE_TEST from ACPI dependency. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: stm32: Add check for devm_kcallocChen Ni1-0/+5
Add check for the return value of devm_kcalloc() and return the error if it fails in order to avoid NULL pointer dereference. Fixes: 32c170ff15b0 ("pinctrl: stm32: set default gpio line names using pin names") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Acked-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20231031080807.3600656-1-nichen@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driverNeil Armstrong3-0/+1771
Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-3-0e179c368933@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: qcom: handle intr_target_reg wakeup_present/enable bitsNeil Armstrong2-0/+47
New platforms uses a new set of bits to control the wakeirq delivery to the PDC block. The intr_wakeup_present_bit indicates if the GPIO supports wakeirq and intr_wakeup_enable_bit enables wakeirq delivery to the PDC block. While the name seems to imply this only enables wakeup events, it is required to allow interrupts events to the PDC block. Enable this bit in the irq resource request/free if: - gpio is in wakeirq map - has the intr_wakeup_present_bit - the intr_wakeup_enable_bit is set Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-2-0e179c368933@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASSKrzysztof Kozlowski3-0/+266
Add driver for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm SM8650 SoC. Notable differences against SM8550 LPASS pin controller: 1. Additional address space for slew rate thus driver uses LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different register. 2. Two new pin mux functions: qca_swr_clk and qca_swr_data Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: tegra: Display pin function in pinconf-groupsThierry Reding1-0/+8
The function that a pin is muxed to can be read from the top-level pinctrl-maps debugfs file. However, this only reflects the values that were specified in device tree, so they will only show deviations from the hardware default setting. Display the current pinmux setting in the per-controller pinconf-groups debugfs file along with the rest of the per-pin configuration settings. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://lore.kernel.org/r/20230929122101.466266-1-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-13pinctrl: intel: Refactor intel_pinctrl_get_soc_data()Andy Shevchenko1-4/+3
Refactor intel_pinctrl_get_soc_data() to drop initial assignment of the data variable. It's only used in ACPI case and instead we may always assign it there as the ACPI ID table has the terminator entry that has driver data set to NULL. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Move default strength assignment to a switch-caseAndy Shevchenko1-4/+2
iWhen ->pin_config_set() is called from the GPIO library (assumed GpioIo() ACPI resource), the argument can be 1, when, for example, PullDefault is provided. In such case we supply sane default in the driver. Move that default assingment to a switch-case, so it will be consolidated in one place. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: tangier: Move default strength assignment to a switch-caseAndy Shevchenko1-8/+2
iWhen ->pin_config_set() is called from the GPIO library (assumed GpioIo() ACPI resource), the argument can be 1, when, for example, PullDefault is provided. In such case we supply sane default in the driver. Move that default assingment to a switch-case, so it will be consolidated in one place. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: tangier: Enable 910 Ohm biasAndy Shevchenko1-0/+6
Family 7 (I2C) supports special bias value, i.e. 910 Ohm. Enable it for configuring pin. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Make PM ops functions staticAndy Shevchenko2-13/+2
No more users outside of the main module. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231030120734.2831419-18-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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