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2023-07-24phy: qcom-qmp-combo: simplify clock handlingDmitry Baryshkov1-44/+23
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: Remove duplicated include in xusb.cYang Li1-1/+0
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930 Signed-off-by: Yang Li <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: hisilicon: Fix an out of bounds check in hisi_inno_phy_probe()Harshit Mogalapalli1-1/+1
The size of array 'priv->ports[]' is INNO_PHY_PORT_NUM. In the for loop, 'i' is used as the index for array 'priv->ports[]' with a check (i > INNO_PHY_PORT_NUM) which indicates that INNO_PHY_PORT_NUM is allowed value for 'i' in the same loop. This > comparison needs to be changed to >=, otherwise it potentially leads to an out of bounds write on the next iteration through the loop Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Harshit Mogalapalli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: starfive: Add mipi dphy rx supportChanghuang Liang3-2/+244
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang <[email protected]> Reviewed-by: Minda Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: starfive: fix error code in probeDan Carpenter1-1/+1
This is using the wrong pointer, "phy->regs" vs "phy->phy". Fixes: fd097f48eea9 ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver") Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-18phy: qcom-qmp-pcie: add support for sa8775pMrinmay Sarkar3-0/+344
Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-17phy: Explicitly include correct DT includesRob Herring81-65/+65
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <[email protected]> Acked-by: Marc Kleine-Budde <[email protected]> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <[email protected]> Acked-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-14phy: ti: gmii-sel: Allow parent to not be syscon nodeAndrew Davis1-3/+6
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: zynqmp: Allow variation in refclk rateSean Anderson1-1/+4
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-ufs: populate offsets configurationDmitry Baryshkov1-0/+10
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen3-0/+215
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen5-0/+170
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki1-0/+98
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Marcin Wierzbicki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee1-25/+173
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu1-0/+13
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman1-2/+4
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman1-4/+1
no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rateZheng Yang1-3/+5
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Zheng Yang <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328Jonas Karlman1-2/+2
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: extract common function to setup clocksDmitry Baryshkov1-37/+26
Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: drop qmp_v6_dp_aux_init()Dmitry Baryshkov1-32/+12
The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: drop similar functionsDmitry Baryshkov1-121/+2
The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for some more registersDmitry Baryshkov2-12/+24
Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for even more registersDmitry Baryshkov3-33/+76
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for more registersDmitry Baryshkov1-36/+64
Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: correct bias0_en programmingDmitry Baryshkov1-2/+2
It seems the commit a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: xilinx: phy-zynqmp: dynamic clock support for power-savePiyush Mehta1-46/+15
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by: Piyush Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: xilinx: add runtime PM supportPiyush Mehta1-7/+28
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by: Piyush Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Compress of_device_id match entriesAngeloGioacchino Del Regno1-7/+4
All of the entries do fit in a maximum of 82 columns, which is acceptable. While at it, also remove the useless comma on the last entry and add the usual sentinel comment. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Use devm variant for of_clk_add_hw_provider()AngeloGioacchino Del Regno1-7/+1
Switch to devm_of_clk_add_hw_provider() in the probe function: this also allows to entirely remove the .remove_new() callback, as its only task was to unregister the clock provider. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Convert to register clk_hwAngeloGioacchino Del Regno2-8/+6
Instead of registering a struct clk, directly register clk_hw: this allows us to cleanup a pointer to struct clk from struct mtk_mipi_tx. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-usb: split off the legacy USB+dp_com supportDmitry Baryshkov4-556/+1418
When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-combo: add support for the USB+DP PHY on SM8150 platformDmitry Baryshkov1-0/+4
SM8150 and SC8180X are close relatives. Reuse sc8180x data to support USB+DP combo PHY on SM8150 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: improve error messageSebastian Reichel1-2/+1
Printing the OF node is not useful, since we get the same information from the device context. Instead print the reg address, that could not be found. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: simplify getting match dataSebastian Reichel1-8/+4
Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: simplify phy clock handlingSebastian Reichel1-13/+6
Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource leak in driver remove path and adds proper error handling. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add rk3588 phy tuning supportSebastian Reichel1-0/+63
On RK3588 some registers need to be tweaked to support waking up from suspend when a USB device is plugged into a port from a suspended PHY. Without this change USB devices only work when they are plugged at boot time. Apart from that it optimizes settings to avoid devices toggling between fullspeed and highspeed mode. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add reset supportSebastian Reichel1-0/+38
Add reset handling support, which is needed for proper operation with RK3588. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add rk3588 supportSebastian Reichel1-15/+211
Add basic support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by: William Wu <[email protected]> Signed-off-by: William Wu <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence-torrent: Use key:value pair table for all settingsRoger Quadros1-1176/+485
Instead of a 3D matrix use a key:value pair table for link_cmn_vals, xcvr_diag_vals, pcs_cmn_vals, phy_pma_cmn_vals, cmn_vals, tx_ln_vals and rx_ln_vals. This makes it scaleable for multiple reference clocks. Wherever both CDNS and TI use the same settings, reuse the same data. Introduce CLK_ANY and ANY_SSC enums which are used if the setting is independent of clock rate or SSC type. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Swapnil Jakhade <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence-torrent: Add single link USXGMII configuration for 156.25MHz refclkSwapnil Jakhade1-5/+228
Add register sequences for single link USXGMII configuration supporting 156.25MHz reference clock frequency. Signed-off-by: Swapnil Jakhade <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: renesas: r8a779f0-ether-serdes: Convert to devm_platform_ioremap_resource()Yangtao Li1-8/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: rockchip: phy-rockchip-typec: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-2/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: marvell: phy-mvebu-cp110-comphy: Use ↵Yangtao Li1-2/+1
devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-snps-femto-v2: use qcom_snps_hsphy_suspend/resume error codeAdrien Thierry1-4/+2
The return value from qcom_snps_hsphy_suspend/resume is not used. Make sure qcom_snps_hsphy_runtime_suspend/resume return this value as well. Signed-off-by: Adrien Thierry <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-snps-femto-v2: properly enable ref clockAdrien Thierry1-15/+48
The driver is not enabling the ref clock, which thus gets disabled by the clk_disable_unused() initcall. This leads to the dwc3 controller failing to initialize if probed after clk_disable_unused() is called, for instance when the driver is built as a module. To fix this, switch to the clk_bulk API to handle both cfg_ahb and ref clocks at the proper places. Note that the cfg_ahb clock is currently not used by any device tree instantiation of the PHY. Work needs to be done separately to fix this. Link: https://lore.kernel.org/linux-arm-msm/ZEqvy+khHeTkC2hf@fedora/ Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Adrien Thierry <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-snps-femto-v2: keep cfg_ahb_clk enabled during runtime suspendAdrien Thierry1-9/+0
In the dwc3 core, both system and runtime suspend end up calling dwc3_suspend_common(). From there, what happens for the PHYs depends on the USB mode and whether the controller is entering system or runtime suspend. HOST mode: (1) system suspend on a non-wakeup-capable controller The [1] if branch is taken. dwc3_core_exit() is called, which ends up calling phy_power_off() and phy_exit(). Those two functions decrease the PM runtime count at some point, so they will trigger the PHY runtime sleep (assuming the count is right). (2) runtime suspend / system suspend on a wakeup-capable controller The [1] branch is not taken. dwc3_suspend_common() calls phy_pm_runtime_put_sync(). Assuming the ref count is right, the PHY runtime suspend op is called. DEVICE mode: dwc3_core_exit() is called on both runtime and system sleep unless the controller is already runtime suspended. OTG mode: (1) system suspend : dwc3_core_exit() is called (2) runtime suspend : do nothing In host mode, the code seems to make a distinction between 1) runtime sleep / system sleep for wakeup-capable controller, and 2) system sleep for non-wakeup-capable controller, where phy_power_off() and phy_exit() are only called for the latter. This suggests the PHY is not supposed to be in a fully powered-off state for runtime sleep and system sleep for wakeup-capable controller. Moreover, downstream, cfg_ahb_clk only gets disabled for system suspend. The clocks are disabled by phy->set_suspend() [2] which is only called in the system sleep path through dwc3_core_exit() [3]. With that in mind, don't disable the clocks during the femto PHY runtime suspend callback. The clocks will only be disabled during system suspend for non-wakeup-capable controllers, through dwc3_core_exit(). [1] https://elixir.bootlin.com/linux/v6.4/source/drivers/usb/dwc3/core.c#L1988 [2] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/LV.AU.1.2.1.r2-05300-gen3meta.0/drivers/usb/phy/phy-msm-snps-hs.c#L524 [3] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/LV.AU.1.2.1.r2-05300-gen3meta.0/drivers/usb/dwc3/core.c#L1915 Signed-off-by: Adrien Thierry <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: hdmi: mt8195: fix prediv bad upper limit testGuillaume Ranquet1-1/+1
The pll prediv calculus searchs for the smallest prediv that gets the ns_hdmipll_ck in the range of 5 GHz to 12 GHz. A typo in the upper bound test was testing for 5Ghz to 1Ghz Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-mtk-dp: Fix an error code in probe()Dan Carpenter1-1/+1
Negative -EINVAL was intended instead of positive EINVAL. Fixes: 6a23afad443a ("phy: phy-mtk-dp: Add driver for DP phy") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-05Merge tag 'phy-for-6.5_v2' of ↵Linus Torvalds24-446/+2584
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Debugfs support for phy core and mediatek driver - Hisilicon inno-usb2-phy driver supporting Hi3798MV100 - Qualcomm SGMII SerDes PHY driver, SM6115 & QCM2290 QMP-USB support, SA8775P USB PHY & USB3 UNI support, QUSB2 support for IPQ9574, IPQ9574 USB3 PHY UpdatesL - Sparx5 serdes phy power optimzation - cadence salvo usb properties and updates and torrent DP with PCIe & USB support - Yaml conversion for Broadcom kona USB bindings and MXS USB binding" * tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (67 commits) dt-bindings: phy: brcm,brcmstb-usb-phy: Fix error in "compatible" conditional schema dt-bindings: phy: mixel,mipi-dsi-phy: Remove assigned-clock* properties dt-bindings: phy: intel,combo-phy: restrict node name suffixes dt-bindings: phy: qcom,usb-hs-phy: Add compatible phy: tegra: xusb: check return value of devm_kzalloc() phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550 phy: qcom: add the SGMII SerDes PHY driver dt-bindings: phy: describe the Qualcomm SGMII PHY phy: qualcomm: fix indentation in Makefile phy: usb: suppress OC condition for 7439b2 phy: usb: Turn off phy when port is in suspend phy: tegra: xusb: Clear the driver reference in usb-phy dev dt-bindings: phy: mxs-usb-phy: add imx8ulp and imx8qm compatible dt-bindings: phy: mxs-usb-phy: convert to DT schema format dt-bindings: phy: qcom,qmp-usb: fix bindings error dt-bindings: phy: qcom,qmp-ufs: fix the sc8180x regs dt-bindings: phy: qcom,qmp-pcie: fix the sc8180x regs phy: mediatek: tphy: add debugfs files phy: core: add debugfs files phy: fsl-imx8mp-usb: add support for phy tuning ...
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