aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy
AgeCommit message (Collapse)AuthorFilesLines
2023-12-21phy: qcom-qmp-combo: Add x1e80100 USB/DP combo physAbel Vesa1-0/+170
The X1E80100 has three copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: mediatek: tphy: add support force phy mode switchChunfeng Yun1-0/+25
this is used to be compatible with old SoCs, such as mt8195, which shares t-phy between usb3 and pcie controller, usually, it's default mode is pcie rc mode, and could use force mode to switch into usb3 mode, because pericfg layer doesn't provide mode switch, also no efuse or jumper can be used; Currently, only support switch from default pcie mode to usb3; Note: don't use this way on new SoCs, use pericfg layer's mode switch instead (by perperty "mediatek,syscon-type"). Signed-off-by: Chunfeng Yun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: phy-can-transceiver: insert space after includeWang Jinchao1-5/+5
Maintain Consistent Formatting: Insert Space after #include Signed-off-by: Wang Jinchao <[email protected]> Reviewed-by: Marc Kleine-Budde <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY SettingsCan Guo2-9/+20
The registers, which are being touched in current SM8550 UFS PHY settings, and the values being programmed are mainly the ones working for HS-G4 mode, meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. However, even consider HS-G4 mode only, some of them are incorrect and some are missing. Rectify the HS-G4 PHY settings by strictly aligning with the SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Can Guo <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: renesas: phy-rcar-gen2: use select for GENERIC_PHYRandy Dunlap1-1/+1
Change the last "depends on GENERIC_PHY" to use select, like the other 170+ Kconfig users do. This can help prevent circular dependency issues. Signed-off-by: Randy Dunlap <[email protected]> Cc: Vinod Koul <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add v7 register offsetsAbel Vesa2-0/+79
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE. Add the new qserdes TX RX offsets in a dedicated header file. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-7-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsetsAbel Vesa2-0/+52
There is a variant of V6 offsets that are different, the QMP PHY N4, and it is found on the X1E80100 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-6-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-com: Add v7 register offsetsAbel Vesa2-0/+89
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-5-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: pcs-usb: Add v7 register offsetsAbel Vesa1-0/+17
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-4-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: pcs: Add v7 register offsetsAbel Vesa2-0/+34
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB, and PCIe. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsetsAbel Vesa1-0/+4
Add some missing v6.20 registers offsets that are needed by the new Snapdragon X Elite (X1E80100) platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-2-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-com: Add some more v6 register offsetsAbel Vesa2-0/+6
Add some missing V6 registers offsets that are needed by the new Snapdragon X Elite (X1E80100) platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-17Merge tag 'phy-fixes-6.7' of ↵Linus Torvalds3-3/+6
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy fixes from Vinod Koul: - register offset fix for TI driver - mediatek driver minimal supported frequency fix - negative error code in probe fix for sunplus driver * tag 'phy-fixes-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: sunplus: return negative error code in sp_usb_phy_probe phy: mediatek: mipi: mt8183: fix minimal supported frequency phy: ti: gmii-sel: Fix register offset when parent is not a syscon node
2023-12-04phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGEDmitry Baryshkov2-43/+3
Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-27phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY supportRohit Agarwal1-0/+173
Add support for USB3 QMP PHY found in SDX75 platform. Signed-off-by: Rohit Agarwal <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-27phy: sunplus: return negative error code in sp_usb_phy_probeSu Hui1-1/+1
devm_phy_create() return negative error code, 'ret' should be 'PTR_ERR(phy)' rather than '-PTR_ERR(phy)'. Fixes: 99d9ccd97385 ("phy: usb: Add USB2.0 phy driver for Sunplus SP7021") Signed-off-by: Su Hui <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-27phy: phy-rockchip-inno-usb2: Add RK3128 supportAlex Bee1-0/+57
Add registers to support the 2-port usb2 phy found in RK312x SoC familiy. Signed-off-by: Alex Bee <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-27phy: rockchip-inno-usb2: Split ID interrupt phy registersAlex Bee1-29/+70
Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID detection interrupt registers. However the current implementation assumes that falling and rising edge interrupt are always enabled in registers spanning over subsequent bits. That is not the case for RK3128's version of the phy and this implementation can't be used as-is, since there are bits with different purpose in between. This splits up the register definitions for id_det_en, id_det_en and id_det_clr registers in rising and falling edge variants. It's required as preparation to support RK3128's Innosilicon usb2 phy as well in this driver and matches pretty much to what the vendor does, so I'm not expecting issues for other SoCs with that change. Signed-off-by: Alex Bee <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-27phy: mediatek: mipi: mt8183: fix minimal supported frequencyMichael Walle1-1/+1
The lowest supported clock frequency of the PHY is 125MHz (see also mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the wrong minimal value, which will make the .enable() op return -EINVAL on low frequencies. Fix the minimal clamping value. Fixes: efda51a58b4a ("drm/mediatek: add mipi_tx driver for mt8183") Signed-off-by: Michael Walle <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: core: Remove usage of the deprecated ida_simple_xx() APIChristophe JAILLET1-2/+2
ida_alloc() and ida_free() should be preferred to the deprecated ida_simple_get() and ida_simple_remove(). This is less verbose. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/d2323636c6cd2ec22f73a0ae6c2d34ac99b4abd5.1698854255.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-combo: add QMP USB3/DP PHY tables for SM8650Neil Armstrong1-0/+4
Add QMP USB3/DP Combo PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650Neil Armstrong1-0/+65
Add QMP PCIe PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650Neil Armstrong3-0/+94
Add QMP UFS PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: ti: gmii-sel: Fix register offset when parent is not a syscon nodeAndrew Davis1-1/+4
When the node for this phy selector is a child node of a syscon node then the property 'reg' is used as an offset into the parent regmap. When the node is standalone and gets its own regmap this offset is pre-applied. So we need to track which method was used to get the regmap and not apply the offset in the standalone case. Fixes: 1fdfa7cccd35 ("phy: ti: gmii-sel: Allow parent to not be syscon node") Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-06Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY"Johan Hovold5-1349/+0
This reverts commit 134e6d25f6bd06071e5aac0a7eefcea6f7713955. The recently added Realtek PHY drivers depend on the new port status notification mechanism which was built on the deprecated USB PHY implementation and devicetree binding. Specifically, using these PHYs would require describing the very same PHY using both the generic "phy" property and the deprecated "usb-phy" property which is clearly wrong. We should not be building new functionality on top of the legacy USB PHY implementation even if it is currently stuck in some kind of transitional limbo. Revert the new Realtek PHY drivers for now so that the port status notification interface can be reverted and replaced. Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY") Cc: [email protected] # 6.6 Cc: Stanley Chang <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-11-06Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY"Johan Hovold3-774/+0
This reverts commit adda6e82a7de7d6d478f6c8ef127f0ac51c510a1. The recently added Realtek PHY drivers depend on the new port status notification mechanism which was built on the deprecated USB PHY implementation and devicetree binding. Specifically, using these PHYs would require describing the very same PHY using both the generic "phy" property and the deprecated "usb-phy" property which is clearly wrong. We should not be building new functionality on top of the legacy USB PHY implementation even if it is currently stuck in some kind of transitional limbo. Revert the new Realtek PHY drivers for now so that the port status notification interface can be reverted and replaced. Fixes: adda6e82a7de ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY") Cc: [email protected] # 6.6 Cc: Stanley Chang <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-11-03Merge tag 'phy-for-6.7' of ↵Linus Torvalds27-295/+564
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New Support: - Qualcomm sa8775p qmp-pcie, IPQ5018, and SC7280 qmp-ufs support - Mediatek MT8188 support Updates: - Device tree device_get_match_data() usage and dropping of_match_device() calls - Qualcomm qmp usb and combo phy updates for v6 register layout - Qualcomm eusb2-repeater updates for tuning overrides, regmap fields - STih407 usb binding and ralink usb-phy yaml conversion - renesas r8a779f0 serdes init sequencing updates" * tag 'phy-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (32 commits) phy: Remove duplicated include in phy-ralink-usb.c phy: Kconfig: Select GENERIC_PHY for GENERIC_PHY_MIPI_DPHY phy: qcom-qmp-pcie: add endpoint support for sa8775p dt-bindings: phy: ralink-usb-phy: convert to dtschema dt-bindings: phy: Convert PXA1928 USB/HSIC PHY to DT schema phy: Drop unnecessary of_match_device() calls phy: rockchip-inno-usb2: Drop unnecessary DT includes phy: Use device_get_match_data() phy: realtek: Replace of_device.h with explicit includes phy: renesas: r8a779f0-ether-serdes: Add .exit() ops phy: renesas: r8a779f0-ether-serdes: Reset in .init() phy: qcom-qmp-combo: use v6 registers in v6 regs layout phy: qcom-qmp-usb: move PCS v6 register to the proper header phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers phy: sun4i-usb: update array size phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overrides phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields dt-bindings: phy: qcom,snps-eusb2-repeater: Add magic tuning overrides dt-bindings: phy: Add compatible for Mediatek MT8188 ...
2023-10-23phy: Remove duplicated include in phy-ralink-usb.cYang Li1-1/+0
./drivers/phy/ralink/phy-ralink-usb.c: linux/platform_device.h is included more than once. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6851 Signed-off-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-23phy: Kconfig: Select GENERIC_PHY for GENERIC_PHY_MIPI_DPHYSakari Ailus1-1/+1
GENERIC_PHY can be selected by GENERIC_PHY_MIPI_DPHY directly as GENERIC_PHY has no dependencies. This way drivers that depend on GENERIC_PHY_MIPI_DPHY can avoid having to select both --- which they apparently often omit, too, which further leads to build failures. Signed-off-by: Sakari Ailus <[email protected]> Reviewed-by: Randy Dunlap <[email protected]> Tested-by: Randy Dunlap <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-23phy: qcom-qmp-pcie: add endpoint support for sa8775pMrinmay Sarkar2-0/+39
Add support for dual lane end point mode PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-22Merge tag 'phy-fixes-6.6' of ↵Linus Torvalds9-48/+57
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy fixes from Vinod Koul: - mapphone-mdm6600 runtime pm & pinctrl handling fixes - Qualcomm qmp usb pcs register fixes, qmp pcie register size warning fix, m31 fixes for wrong pointer in PTR_ERR and dropping wrong vreg check, qmp combo fix for 8550 power config register - realtek usb fix for debugfs_create_dir() and kconfig dependency * tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: realtek: Realtek PHYs should depend on ARCH_REALTEK phy: qualcomm: Fix typos in comments phy: qcom-qmp-combo: initialize PCS_USB registers phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1 phy: qcom: m31: Remove unwanted qphy->vreg is NULL check phy: realtek: usb: Drop unnecessary error check for debugfs_create_dir() phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to static phy: qcom: phy-qcom-m31: fix wrong pointer pass to PTR_ERR() dt-bindings: phy: qcom,ipq8074-qmp-pcie: fix warning regarding reg size phy: qcom-qmp-usb: split PCS_USB init table for sc8280xp and sa8775p phy: qcom-qmp-usb: initialize PCS_USB registers phy: mapphone-mdm6600: Fix pinctrl_pm handling for sleep pins phy: mapphone-mdm6600: Fix runtime PM for remove phy: mapphone-mdm6600: Fix runtime disable on probe
2023-10-13phy: Drop unnecessary of_match_device() callsRob Herring2-17/+1
If probe is reached, we've already matched the device and in the case of DT matching, the struct device_node pointer will be set. Therefore, there is no need to call of_match_device() in probe. Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: rockchip-inno-usb2: Drop unnecessary DT includesRob Herring1-2/+0
Neither of_address.h or of_platform.h are used in the driver, so drop them. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: Use device_get_match_data()Rob Herring8-55/+26
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: realtek: Replace of_device.h with explicit includesRob Herring2-2/+2
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other and pull in various other headers. In preparation to fix this, adjust the includes for what is actually needed. of_device.h isn't needed, but platform_device.h was implicitly included by it. Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: renesas: r8a779f0-ether-serdes: Add .exit() opsYoshihiro Shimoda1-0/+10
Add r8a779f0_eth_serdes_exit() to clear the initialized flag for re-initializing this PHY if needed. Signed-off-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: renesas: r8a779f0-ether-serdes: Reset in .init()Yoshihiro Shimoda1-2/+4
Reset this PHY in .init() instead of probe() for re-initializing this PHY after probed correctly. Signed-off-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-combo: use v6 registers in v6 regs layoutDmitry Baryshkov3-7/+12
Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-usb: move PCS v6 register to the proper headerDmitry Baryshkov2-18/+14
The commit 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register offsets") incorrectly added plain PCS registers to the PCS_USB header. Move them to a proper location. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registersDmitry Baryshkov2-39/+39
For all other generations, we have been using just the QPHY prefix for the PCS registers. Remove the _USB part of the QPHY_USB prefix. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: sun4i-usb: update array sizeChristophe JAILLET1-1/+1
With gcc 12.3.0, when this file is built, we get errors such as: drivers/phy/allwinner/phy-sun4i-usb.c: In function ‘sun4i_usb_phy_probe’: drivers/phy/allwinner/phy-sun4i-usb.c:790:52: error: ‘_vbus’ directive output may be truncated writing 5 bytes into a region of size between 2 and 12 [-Werror=format-truncation=] 790 | snprintf(name, sizeof(name), "usb%d_vbus", i); | ^~~~~ drivers/phy/allwinner/phy-sun4i-usb.c:790:17: note: ‘snprintf’ output between 10 and 20 bytes into a destination of size 16 790 | snprintf(name, sizeof(name), "usb%d_vbus", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Because of the possible value of 'i', this can't be an issue in real world application, but in order to have "make W=1" work correctly, give more space for 'name'. Signed-off-by: Christophe JAILLET <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/0bc81612171baaa6d5dff58c8e009debc03e1ba8.1693735840.git.christophe.jaillet@wanadoo.fr [vkoul: updated patch title] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13Merge branch 'fixes' into nextVinod Koul9-47/+56
Merge fixes into next as qmp phy patches on list depend on it
2023-10-06phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registersVladimir Oltean1-0/+9
The protocol converter configuration registers PCC8, PCCC, PCCD (implemented by the driver), as well as others, control protocol converters from multiple lanes (each represented as a different struct phy). So, if there are simultaneous calls to phy_set_mode_ext() to lanes sharing the same PCC register (either for the "old" or for the "new" protocol), corruption of the values programmed to hardware is possible, because lynx_28g_rmw() has no locking. Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take the global spinlock from the phy_ops :: set_mode() implementation. There are no other callers which modify PCC registers. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-10-06phy: lynx-28g: lock PHY while performing CDR lock workaroundVladimir Oltean1-3/+6
lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset the lane receiver if the CDR has not locked onto bit transitions in the RX stream. But the PHY consumer may do stuff with the PHY simultaneously, and that isn't okay. Block concurrent generic PHY calls by holding the PHY mutex from this workqueue. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-10-06phy: lynx-28g: cancel the CDR check work item on the remove pathIoana Ciornei1-0/+9
The blamed commit added the CDR check work item but didn't cancel it on the remove path. Fix this by adding a remove function which takes care of it. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-09-29phy: realtek: Realtek PHYs should depend on ARCH_REALTEKGeert Uytterhoeven1-0/+5
The Realtek SoC USB2 and USB3 PHY Transceivers are only present on Realtek Digital Home Center (DHC) RTD series SoCs. Hence add a dependency on ARCH_REALTEK, to prevent asking the user about these drivers when configuring a kernel without Realtek SoC support. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/2892527cac9af6fa8f5e7b8daeffd7d4351fde68.1692113167.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overridesKonrad Dybcio1-1/+16
There are devices in the wild, like the Sony Xperia 1 V that *require* different tuning than the base design for USB to work. Add support for overriding the necessary tuning values. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regsKonrad Dybcio1-14/+44
The vendor kernel zeroes out all tuning data outside the init sequence as part of initialization. Follow suit to avoid UB. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fieldsKonrad Dybcio1-30/+61
Switch to regmap_fields, so that the values written into registers are sanitized by their explicit sizes and the different registers are structured in an iterable object to make external changes to the init sequence simpler. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-m31: Add compatible, phy init sequence for IPQ5018Nitheesh Sekar1-0/+51
Add phy init sequence and compatible string for IPQ5018 chipset. Signed-off-by: Nitheesh Sekar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.