aboutsummaryrefslogtreecommitdiff
path: root/drivers/pci/controller
AgeCommit message (Collapse)AuthorFilesLines
2024-06-28PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)Kishon Vijay Abraham I1-1/+43
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Achal Verma <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Jan Kiszka <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2024-06-25PCI: ls-gen4: Make struct mobiveil_rp_ops constantChristophe JAILLET2-2/+2
The struct mobiveil_rp_ops is not modified in this driver. Thus, make this struct constant, which also moves data to a read-only section decreasing object size and also improving overall security. On a x86_64, with allmodconfig, as an example: Before: ====== text data bss dec hex filename 4446 336 32 4814 12ce drivers/pci/controller/mobiveil/pcie-layerscape-gen4.o After: ===== text data bss dec hex filename 4454 328 32 4814 12ce drivers/pci/controller/mobiveil/pcie-layerscape-gen4.o [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/189fd881cc8fd80220e74e91820e12cf3a5be114.1719260294.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2024-06-06PCI: tegra: Remove unused struct 'tegra_pcie_soc'Dr. David Alan Gilbert1-4/+0
'tegra_pcie_soc' has been unused since 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support"). Remove it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dr. David Alan Gilbert <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-06-03PCI: Use preserve_config in place of pci_flagsVidya Sagar1-4/+0
Use preserve_config in place of checking for PCI_PROBE_ONLY flag to enable support for "linux,pci-probe-only" on a per host bridge basis. This also obviates the use of adding PCI_REASSIGN_ALL_BUS flag if !PCI_PROBE_ONLY, as pci_assign_unassigned_root_bus_resources() takes care of reassigning the resources that are not already claimed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: tegra194: Set EP alignment restriction for inbound ATUJon Hunter1-0/+1
Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the Tegra194 PCIe driver. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Suggested-by: Manikanta Maddireddy <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-05-28PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup()Marek Vasut1-1/+5
Avoid large backtrace, it is sufficient to warn the user that there has been a link problem. Either the link has failed and the system is in need of maintenance, or the link continues to work and user has been informed. The message from the warning can be looked up in the sources. This makes an actual link issue less verbose. First of all, this controller has a limitation in that the controller driver has to assist the hardware with transition to L1 link state by writing L1IATN to PMCTRL register, the L1 and L0 link state switching is not fully automatic on this controller. In case of an ASMedia ASM1062 PCIe SATA controller which does not support ASPM, on entry to suspend or during platform pm_test, the SATA controller enters D3hot state and the link enters L1 state. If the SATA controller wakes up before rcar_pcie_wakeup() was called and returns to D0, the link returns to L0 before the controller driver even started its transition to L1 link state. At this point, the SATA controller did send an PM_ENTER_L1 DLLP to the PCIe controller and the PCIe controller received it, and the PCIe controller did set PMSR PMEL1RX bit. Once rcar_pcie_wakeup() is called, if the link is already back in L0 state and PMEL1RX bit is set, the controller driver has no way to determine if it should perform the link transition to L1 state, or treat the link as if it is in L0 state. Currently the driver attempts to perform the transition to L1 link state unconditionally, which in this specific case fails with a PMSR L1FAEG poll timeout, however the link still works as it is already back in L0 state. Reduce this warning verbosity. In case the link is really broken, the rcar_pcie_config_access() would fail, otherwise it will succeed and any system with this controller and ASM1062 can suspend without generating a backtrace. Fixes: 84b576146294 ("PCI: rcar: Finish transition to L1 state in rcar_pcie_config_access()") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: starfive: Add JH7110 PCIe controllerMinda Chen4-1/+571
Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 with PLDA host PCIe core. Link: https://lore.kernel.org/linux-pci/[email protected] Co-developed-by: Kevin Xie <[email protected]> Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Mason Huo <[email protected]>
2024-05-28PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems()Minda Chen3-4/+4
plda_pcie_setup_iomems() needs the bridge->windows list from struct pci_host_bridge and is currently used only by pcie-microchip-host.c. This driver uses pci_host_common_probe(), which sets a pci_host_bridge as the drvdata, so plda_pcie_setup_iomems() used platform_get_drvdata() to find the pci_host_bridge. But we also want to use plda_pcie_setup_iomems() in the new pcie-starfive.c driver, which does not use pci_host_common_probe() and will have struct starfive_jh7110_pcie as its drvdata, so pass the pci_host_bridge directly to plda_pcie_setup_iomems() so it doesn't need platform_get_drvdata() to find it. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: commit log, reorder to where this is needed] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: plda: Add host init/deinit and map bus functionsMinda Chen2-14/+139
Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function so vendors can use it to init PLDA PCIe host core. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Mason Huo <[email protected]>
2024-05-28PCI: plda: Add event bitmap field to struct plda_pcie_rpMinda Chen3-2/+6
PLDA DMA interrupts are not all implemented, and the non-implemented interrupts should be masked. Add a bitmap field to mask the non-implemented interrupts. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: microchip: Move IRQ functions to pcie-plda-host.cMinda Chen3-467/+476
Move IRQ related functions to common file pcie-plda-host.c The re-use code including MSI, INTx, event interrupts and IRQ init functions. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add event irqchip field to host port and add PLDA irqchipMinda Chen2-16/+84
As the PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) shows, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIe event IRQs include PLDA interrupts and PolarFire additional interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip PolarFire PCIe additional interrupts require to write PolarFire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add get_events() callback and PLDA get_event()Minda Chen2-1/+66
As PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. PolarFire implements its own PCIe interrupts, additional to the regular PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA regular interrupts, necessitating a custom get_events() implementation. Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... plda_get_events() adds interrupt register to PLDA event num mapping codes. All the PLDA interrupts can be seen in new added graph. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add INTx and MSI event num to struct plda_eventMinda Chen2-2/+6
The INTx and MSI interrupt event num is different across platforms, so add two event num fields in struct plda_event. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add request_event_irq() callback functionMinda Chen2-4/+32
As the PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) shows, the PLDA IP contains an interrupt controller. Microchip PolarFire add some interrupts based on PLDA interrupt controller. The Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... Both event_cause[] and mc_event_handler() contain additional interrupt symbol names; these can not be re-used. Add a new plda_event_handler() function, which implements PLDA interrupt defalt handler, and add a request_event_irq() callback function for Microchip PolarFire additional interrupts. [kwilczynski, bhelgaas: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add num_events field to struct plda_pcie_rpMinda Chen2-3/+6
The number of events is different across platforms. In order to share interrupt processing code, add a variable that defines the number of events so that it can be set per-platform instead of hardcoding it. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Rename interrupt related functionsMinda Chen1-52/+57
Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data instances. MSI, INTx interrupt code and IRQ init code can all be re-used. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Move PLDA functions to pcie-plda-host.cMinda Chen5-60/+84
Move plda_pcie_setup_window() and plda_pcie_setup_iomems() to pcie-plda-host.c so they can be shared by all PLDA-based drivers. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Rename PLDA functions to be genericMinda Chen1-12/+12
Rename mc_pcie_setup_window() to plda_pcie_setup_window() and mc_pcie_setup_windows() to plda_pcie_setup_iomems() so they can be shared by all PLDA-based drivers. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Move PLDA structures to plda-pcie.hMinda Chen2-20/+21
Move the PLDA generic data structures to a header file so they can be re-used by all PLDA-based drivers. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Rename PLDA structures to be genericMinda Chen1-43/+53
Rename struct mc_msi to plda_msi and move most of struct mc_pcie to a new struct plda_pcie_rp so they can be shared by all PLDA-based drivers. The axi_base_addr field remains in struct mc_pcie since it's Microchip-specific data. The event interrupt code is still using struct mc_pcie because the event interrupt code can not be re-used. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Add bridge_addr field to struct mc_pcieMinda Chen1-14/+9
Bridge address base is common PLDA field, add this to struct mc_pcie first. INTx and MSI interrupt code will be changed to common code, so get the bridge base address from port->bridge_addr instead of axi_base_addr. The axi_base_addr is Microchip-specific data. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Move PLDA IP register macros to pcie-plda.hMinda Chen2-92/+124
Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and PLDA IRQ event number. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: microchip: Move pcie-microchip-host.c to PLDA directoryMinda Chen5-10/+19
Since Microchip PolarFire PCIe host is PLDA XpressRich IP, move to PLDA directory. Prepare for refactoring the codes. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-05-28PCI: keystone: Fix NULL pointer dereference in case of DT error in ↵Aleksandr Mishin1-5/+15
ks_pcie_setup_rc_app_regs() If IORESOURCE_MEM is not provided in Device Tree due to any error, resource_list_first_type() will return NULL and pci_parse_request_of_pci_ranges() will just emit a warning. This will cause a NULL pointer dereference. Fix this bug by adding NULL return check. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources") Link: https://lore.kernel.org/linux-pci/[email protected] Suggested-by: Bjorn Helgaas <[email protected]> Suggested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Aleksandr Mishin <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: keystone: Don't enable BAR 0 for AM654xSiddharth Vadapalli1-34/+18
After 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus"), ks_pcie_v3_65_add_bus() enabled BAR 0 for both v3.65a and v4.90a devices. On the AM654x SoC, which uses v4.90a, enabling BAR 0 causes Completion Timeouts when setting up MSI-X. These timeouts delay boot of the AM654x by about 45 seconds. Move the BAR 0 initialization to ks_pcie_msi_host_init(), which is only used for v3.65a devices, and remove ks_pcie_v3_65_add_bus(). [bhelgaas: commit log] Fixes: 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus") Link: https://lore.kernel.org/linux-pci/[email protected] Suggested-by: Bjorn Helgaas <[email protected]> Suggested-by: Niklas Cassel <[email protected]> Suggested-by: Serge Semin <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-05-28PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()Siddharth Vadapalli1-42/+42
Relocate ks_pcie_set_dbi_mode() and ks_pcie_clear_dbi_mode() to avoid forward declaration in a subsequent patch. No functional change intended. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: imx6: Convert to use agnostic GPIO APIAndy Shevchenko1-26/+10
The of_gpio.h legacy API is going to be removed. In preparation for that, convert the driver to the agnostic API. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: dwc: Remove unused of_gpio.h inclusionAndy Shevchenko4-5/+0
The of_gpio.h API is deprecated and subject to removal. The driver doesn't use it, so simply remove the unused header. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: aardvark: Remove unused of_gpio.h inclusionAndy Shevchenko1-1/+0
The of_gpio.h API is deprecated and subject to removal. The driver doesn't use it, so simply remove the unused header. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: dra7xx: Add missing chained IRQ header inclusionAndy Shevchenko1-0/+1
Driver is using chained_irq_*() APIs, add the respective inclusion. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: exynos: Adapt to use bulk clock APIsShradha Todi1-50/+4
There is no need to hardcode the clock info in the driver as driver can rely on the devicetree to supply the clocks required for the functioning of the peripheral. Thus, remove the static clock info and obtain the platform supplied clocks. All the clocks supplied are obtained and enabled using the devm_clk_bulk_get_all_enable() API. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Shradha Todi <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Alim Akhtar <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: dra7xx: Fix dra7xx_pcie_cpu_addr_fixup() parameter nameNiklas Cassel1-2/+2
The function pointer declaration for the cpu_addr_fixup() callback uses "cpu_addr" as parameter name. Likewise, the argument that is supplied to the function pointer when the function is actually called is "cpu_addr". Rename the dra7xx_pcie_cpu_addr_fixup() function parameter name to match reality. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: artpec6: Fix artpec6_pcie_cpu_addr_fixup() parameter nameNiklas Cassel1-4/+4
The function pointer declaration for the cpu_addr_fixup() callback uses "cpu_addr" as parameter name. Likewise, the argument that is supplied to the function pointer when the function is actually called is "cpu_addr". Rename the artpec6_pcie_cpu_addr_fixup() parameter name to match reality. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jesper Nilsson <[email protected]>
2024-05-28PCI: al: Check IORESOURCE_BUS existence during probeAleksandr Mishin1-3/+13
If IORESOURCE_BUS is not provided in Device Tree it will be fabricated in of_pci_parse_bus_range(), so NULL pointer dereference should not happen here. But that's hard to verify, so check for NULL anyway. Found by Linux Verification Center (linuxtesting.org) with SVACE. Link: https://lore.kernel.org/linux-pci/[email protected] Suggested-by: Bjorn Helgaas <[email protected]> Signed-off-by: Aleksandr Mishin <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-28PCI: endpoint: Rename BME to Bus Master EnableManivannan Sadhasivam1-2/+2
BME which stands for 'Bus Master Enable' is not defined in the PCIe base spec even though it is commonly referred in many places (vendor docs). To align with the spec, rename it to its expansion 'Bus Master Enable'. Suggested-by: Damien Le Moal <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Niklas Cassel <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: squash removal of irrelevant 'Link is enabled'] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-05-28PCI: qcom-ep: Add HDMA support for SA8775P SoCMrinmay Sarkar1-1/+22
SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. [mani: reworded commit message, added kdoc, and minor cleanups] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2024-05-28PCI: dwc: Pass the eDMA mapping format flag directly from glue driversManivannan Sadhasivam3-11/+12
Instead of maintaining a separate capability for glue drivers that cannot support auto detection of the eDMA mapping format, pass the mapping format directly from them. This will simplify the code and also allow adding HDMA support that also doesn't support auto detection of mapping format. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]>
2024-05-28PCI: dwc: Skip finding eDMA channels count for HDMA platformsManivannan Sadhasivam1-3/+11
In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way the drivers can auto detect the number of read/write channels as like its predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA have to pass the channels count during probe. To accommodate that, skip the existing auto detection of channels count procedure for HDMA based platforms. If the channels count passed by the glue drivers were wrong in any form, then the existing sanity check will catch it. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
2024-05-28PCI: dwc: Refactor dw_pcie_edma_find_chip() APIManivannan Sadhasivam1-7/+30
In order to add support for Hyper DMA (HDMA), refactor the existing dw_pcie_edma_find_chip() API by moving the common code to separate functions. No functional change. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
2024-05-28PCI: qcom-ep: Add support for SA8775P SOCMrinmay Sarkar1-0/+1
Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller driver. Adding new compatible string as it has different set of clocks compared to other SoCs. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-28PCI: qcom: Use devm_clk_bulk_get_all() APIManivannan Sadhasivam1-119/+58
There is no need for the device drivers to validate the clocks defined in Devicetree. The validation should be performed by the DT schema and the drivers should just get all the clocks from DT. Right now the driver hardcodes the clock info and validates them against DT which is redundant. So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT and get rid of all static clocks info from the driver. This simplifies the driver. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2024-05-16Merge branch 'pci/controller/tegra194'Bjorn Helgaas1-0/+3
- Return success from endpoint probe before incorrectly dropping the reference to the BPMP (Vidya Sagar) * pci/controller/tegra194: PCI: tegra194: Fix probe path for Endpoint mode
2024-05-16Merge branch 'pci/controller/rockchip'Bjorn Helgaas1-5/+3
- Configure endpoint BAR to be 64-bit if the PCI_BASE_ADDRESS_MEM_TYPE_64 flag is set instead of depending on the new BAR value itself (Niklas Cassel) - Set Subsystem Vendor ID correctly (Rick Wertenbroek) * pci/controller/rockchip: PCI: rockchip-ep: Remove wrong mask on subsys_vendor_id PCI: rockchip-ep: Set a 64-bit BAR if requested
2024-05-16Merge branch 'pci/controller/mt7621'Bjorn Helgaas1-1/+1
- Enlarge PHY name buffer to avoid snprintf() overflow (Sergio Paracuellos) * pci/controller/mt7621: PCI: mt7621: Fix string truncation in mt7621_pcie_parse_port()
2024-05-16Merge branch 'pci/controller/dwc'Bjorn Helgaas16-95/+298
- Move DBI accesses from dw_pcie_ep_init() to dw_pcie_ep_init_complete() so drivers for endpoints that require Refclk for DBI access, e.g., qcom and tegra194, can control when this happens (Manivannan Sadhasivam) - Add endpoint API kernel-doc (Manivannan Sadhasivam) - Remove .deinit() callback and instead call rcar_gen4_pcie_ep_deinit() explicitly from rcar-gen4, which was the only user (Manivannan Sadhasivam) - Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to correspond with dw_pcie_ep_init() (Manivannan Sadhasivam) - Add dw_pcie_ep_cleanup() for drivers that need to clean up eDMA resources when PERST# is asserted, e.g., qcom, tegra194 (Manivannan Sadhasivam) - Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to better reflect the functionality (Manivannan Sadhasivam) - Call dw_pcie_ep_init_registers() directly from drivers instead of from dw_pcie_ep_init() so drivers, e.g., qcom and tegra194, can do it when Refclk is available (Manivannan Sadhasivam) - Remove the "core_init_notifier" flag, which previously identified drivers that required Refclk before DBI access, because it's now unnecessary (Manivannan Sadhasivam) * pci/controller/dwc: PCI: endpoint: Remove "core_init_notifier" flag PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST# PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops PCI: dwc: ep: Add Kernel-doc comments for APIs PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
2024-05-15PCI: rockchip-ep: Remove wrong mask on subsys_vendor_idRick Wertenbroek1-4/+2
Remove wrong mask on subsys_vendor_id. Both the Vendor ID and Subsystem Vendor ID are u16 variables and are written to a u32 register of the controller. The Subsystem Vendor ID was always 0 because the u16 value was masked incorrectly with GENMASK(31,16) resulting in all lower 16 bits being set to 0 prior to the shift. Remove both masks as they are unnecessary and set the register correctly i.e., the lower 16-bits are the Vendor ID and the upper 16-bits are the Subsystem Vendor ID. This is documented in the RK3399 TRM section 17.6.7.1.17 [kwilczynski: removed unnecesary newline] Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Rick Wertenbroek <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Cc: [email protected]
2024-04-11PCI: mt7621: Fix string truncation in mt7621_pcie_parse_port()Sergio Paracuellos1-1/+1
The following warning appears when driver is compiled with W=1. CC drivers/pci/controller/pcie-mt7621.o drivers/pci/controller/pcie-mt7621.c: In function ‘mt7621_pcie_probe’: drivers/pci/controller/pcie-mt7621.c:228:49: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] 228 | snprintf(name, sizeof(name), "pcie-phy%d", slot); | ^ drivers/pci/controller/pcie-mt7621.c:228:9: note: ‘snprintf’ output between 10 and 11 bytes into a destination of size 10 228 | snprintf(name, sizeof(name), "pcie-phy%d", slot); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Clean this up increasing destination buffer one byte. [kwilczynski: commit log] Closes: https://lore.kernel.org/linux-pci/20240110212302.GA2123146@bhelgaas/T/#t Link: https://lore.kernel.org/linux-pci/[email protected] Reported-by: Bjorn Helgaas <[email protected]> Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2024-04-10PCI: tegra194: Fix probe path for Endpoint modeVidya Sagar1-0/+3
Tegra194 PCIe probe path is taking failure path in success case for Endpoint mode. Return success from the switch case instead of going into the failure path. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Jon Hunter <[email protected]>
2024-04-10PCI: endpoint: Remove "core_init_notifier" flagManivannan Sadhasivam15-2/+25
"core_init_notifier" flag is set by the glue drivers requiring refclk from the host to complete the DWC core initialization. Also, those drivers will send a notification to the EPF drivers once the initialization is fully completed using the pci_epc_init_notify() API. Only then, the EPF drivers will start functioning. For the rest of the drivers generating refclk locally, EPF drivers will start functioning post binding with them. EPF drivers rely on the 'core_init_notifier' flag to differentiate between the drivers. Unfortunately, this creates two different flows for the EPF drivers. So to avoid that, let's get rid of the "core_init_notifier" flag and follow a single initialization flow for the EPF drivers. This is done by calling the dw_pcie_ep_init_notify() from all glue drivers after the completion of dw_pcie_ep_init_registers() API. This will allow all the glue drivers to send the notification to the EPF drivers once the initialization is fully completed. Only difference here is that, the drivers requiring refclk from host will send the notification once refclk is received, while others will send it during probe time itself. But this also requires the EPC core driver to deliver the notification after EPF driver bind. Because, the glue driver can send the notification before the EPF drivers bind() and in those cases the EPF drivers will miss the event. To accommodate this, EPC core is now caching the state of the EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the notification to EPF drivers based on that after each EPF driver bind. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Niklas Cassel <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.