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2020-10-05PCI: meson: Build as module by defaultKevin Hilman2-2/+9
Enable pci-meson to build as a module whenever ARCH_MESON is enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kevin Hilman <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Cc: Yue Wang <[email protected]>
2020-10-05Merge 5.9-rc8 into usb-nextGreg Kroah-Hartman1-7/+4
We need the USB fixes in here as well for testing. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-02Merge tag 'pci-v5.9-fixes-2' of ↵Linus Torvalds1-7/+4
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - Fix rockchip regression in rockchip_pcie_valid_device() (Lorenzo Pieralisi) - Add Pali Rohár as aardvark PCI maintainer (Pali Rohár) * tag 'pci-v5.9-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: MAINTAINERS: Add Pali Rohár as aardvark PCI maintainer PCI: rockchip: Fix bus checks in rockchip_pcie_valid_device()
2020-10-02PCI: aardvark: Fix initialization with old Marvell's Arm Trusted FirmwarePali Rohár1-1/+3
Old ATF automatically power on pcie phy and does not provide SMC call for phy power on functionality which leads to aardvark initialization failure: [ 0.330134] mvebu-a3700-comphy d0018300.phy: unsupported SMC call, try updating your firmware [ 0.338846] phy phy-d0018300.phy.1: phy poweron failed --> -95 [ 0.344753] advk-pcie d0070000.pcie: Failed to initialize PHY (-95) [ 0.351160] advk-pcie: probe of d0070000.pcie failed with error -95 This patch fixes above failure by ignoring 'not supported' error in aardvark driver. In this case it is expected that phy is already power on. Tested-by: Tomasz Maciej Nowak <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: 366697018c9a ("PCI: aardvark: Add PHY support") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: <[email protected]> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno
2020-10-02PCI: xgene: Remove unused assignment to variable msi_valKrzysztof Wilczyński1-2/+2
The value assigned to msi_val after the inner loop finishes its run is never used for anything, and it is also immediately overridden in the line that follows with the return value from the xgene_msi_int_read() function. Since the value of msi_val following the inner loop completion is never used in any meaningful way the assignment can be removed. Addresses-Coverity-ID: 1437183 ("Unused value") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Bjorn Helgaas <[email protected]>
2020-10-02PCI: loongson: Simplify loongson_pci_probe() return expressionQinglang Miao1-6/+1
Simplify the return expression. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Qinglang Miao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-10-02PCI: cadence: Simplify cdns_pcie_host_init_address_translation() return ↵Qinglang Miao1-6/+2
expression Simplify the return expression. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Qinglang Miao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-10-02PCI: mobiveil: Simplify mobiveil_pcie_init_irq_domain() return expressionLiu Shixin1-6/+1
Simplify the return expression by removing useless code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Liu Shixin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-10-02PCI: iproc: Use module_bcma_driver to simplify the codeLiu Shixin1-12/+1
module_bcma_driver() makes the code simpler by eliminating boilerplate code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Liu Shixin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Ray Jui <[email protected]>
2020-10-02PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match listJim Quinlan1-0/+4
Now that the support is in place with previous commits, we add several chips that use the BrcmSTB driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]> Acked-by: Rob Herring <[email protected]>
2020-10-02PCI: brcmstb: Set bus max burst size by chip typeJim Quinlan1-4/+15
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The 2711 family requires 128B whereas other devices can employ 512. The assignment is complicated by the fact that the values for this two-bit field have different meanings; Value Type_Generic Type_7278 00 Reserved 128B 01 128B 256B 10 256B 512B 11 512B Reserved Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-10-02PCI: brcmstb: Accommodate MSI for older chipsJim Quinlan1-21/+49
Older BrcmSTB chips do not have a separate register for MSI interrupts; the MSIs are in a register that also contains unrelated interrupts. In addition, the interrupts lie in bits [31..24] for these legacy chips. This commit provides common code for both legacy and non-legacy MSI interrupt registers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-10-02PCI: brcmstb: Set additional internal memory DMA viewport sizesJim Quinlan1-18/+49
The Raspberry Pi (RPI) is currently the only chip using this driver (pcie-brcmstb.c). There, only one memory controller is used, without an extension region, and the SCB0 viewport size is set to the size of the first and only dma-range region. Other BrcmSTB SOCs have more complicated memory configurations that require setting additional viewport sizes. BrcmSTB PCIe controllers are intimately connected to the memory controller(s) on the SOC. The SOC may have one to three memory controllers; they are indicated by the term SCBi. Each controller has a base region and an optional extension region. In physical memory, the base and extension regions of a controller are not adjacent, but in PCIe-space they are. There is a "viewport" for each memory controller that allows DMA from endpoint devices. Each viewport's size must be set to a power of two, and that size must be equal to or larger than the amount of memory each controller supports which is the sum of base region and its optional extension. Further, the 1-3 viewports are also adjacent in PCIe-space. Unfortunately the viewport sizes cannot be ascertained from the "dma-ranges" property so they have their own property, "brcm,scb-sizes". This is because dma-range information does not indicate what memory controller it is associated. For example, consider the following case where the size of one dma-range is 2GB and the second dma-range is 1GB: /* Case 1: SCB0 size set to 4GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) /* Case 2: SCB0 size set to 2GB, SCB1 size set to 1GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) By just looking at the dma-ranges information, one cannot tell which situation applies. That is why an additional property is needed. Its length indicates the number of memory controllers being used and each value indicates the viewport size. Note that the RPI DT does not have a "brcm,scb-sizes" property value, as it is assumed that it only requires one memory controller and no extension. So the optional use of "brcm,scb-sizes" will be backwards compatible. One last layer of complexity exists: all of the viewports sizes must be added and rounded up to a power of two to determine what the "BAR" size is. Further, an offset must be given that indicates the base PCIe address of this "BAR". The use of the term BAR is typically associated with endpoint devices, and the term is used here because the PCIe HW may be used as an RC or an EP. In the former case, all of the system memory appears in a single "BAR" region in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely used in the EP role and its system of mapping memory is an artifact that requires multiple dma-ranges regions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-10-02PCI: brcmstb: Add control of rescal resetJim Quinlan1-2/+77
Some STB chips have a special purpose reset controller named RESCAL (reset calibration). The PCIe HW can now control RESCAL to start and stop its operation. On probe(), the RESCAL is deasserted and the driver goes through the sequence of setting registers and reading status in order to start the internal PHY that is required for the PCIe. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-10-02PCI: hv: Fix hibernation in case interrupts are not re-createdDexuan Cui1-3/+47
pci_restore_msi_state() directly writes the MSI/MSI-X related registers via MMIO. On a physical machine, this works perfectly; for a Linux VM running on a hypervisor, which typically enables IOMMU interrupt remapping, the hypervisor usually should trap and emulate the MMIO accesses in order to re-create the necessary interrupt remapping table entries in the IOMMU, otherwise the interrupts can not work in the VM after hibernation. Hyper-V is different from other hypervisors in that it does not trap and emulate the MMIO accesses, and instead it uses a para-virtualized method, which requires the VM to call hv_compose_msi_msg() to notify the hypervisor of the info that would be passed to the hypervisor in the case of the trap-and-emulate method. This is not an issue to a lot of PCI device drivers, which destroy and re-create the interrupts across hibernation, so hv_compose_msi_msg() is called automatically. However, some PCI device drivers (e.g. the in-tree GPU driver nouveau and the out-of-tree Nvidia proprietary GPU driver) do not destroy and re-create MSI/MSI-X interrupts across hibernation, so hv_pci_resume() has to call hv_compose_msi_msg(), otherwise the PCI device drivers can no longer receive interrupts after the VM resumes from hibernation. Hyper-V is also different in that chip->irq_unmask() may fail in a Linux VM running on Hyper-V (on a physical machine, chip->irq_unmask() can not fail because unmasking an MSI/MSI-X register just means an MMIO write): during hibernation, when a CPU is offlined, the kernel tries to move the interrupt to the remaining CPUs that haven't been offlined yet. In this case, hv_irq_unmask() -> hv_do_hypercall() always fails because the vmbus channel has been closed: here the early "return" in hv_irq_unmask() means the pci_msi_unmask_irq() is not called, i.e. the desc->masked remains "true", so later after hibernation, the MSI interrupt always remains masked, which is incorrect. Refer to cpu_disable_common() -> fixup_irqs() -> irq_migrate_all_off_this_cpu() -> migrate_one_irq(): static bool migrate_one_irq(struct irq_desc *desc) { ... if (maskchip && chip->irq_mask) chip->irq_mask(d); ... err = irq_do_set_affinity(d, affinity, false); ... if (maskchip && chip->irq_unmask) chip->irq_unmask(d); Fix the issue by calling pci_msi_unmask_irq() unconditionally in hv_irq_unmask(). Also suppress the error message for hibernation because the hypercall failure during hibernation does not matter (at this time all the devices have been frozen). Note: the correct affinity info is still updated into the irqdata data structure in migrate_one_irq() -> irq_do_set_affinity() -> hv_set_affinity(), so later when the VM resumes, hv_pci_restore_msi_state() is able to correctly restore the interrupt with the correct affinity. Link: https://lore.kernel.org/r/[email protected] Fixes: ac82fc832708 ("PCI: hv: Add hibernation support") Signed-off-by: Dexuan Cui <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Jake Oshins <[email protected]>
2020-09-28PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't readyBean Huo1-1/+5
PCI host bridge driver can be probed before the gpiochip it requires, so, of_get_named_gpio() can return -EPROBE_DEFER. Current code lets the kirin_pcie_probe() directly return -ENODEV, which results in the PCI host controller driver probe failure; with this error code the PCI host controller driver will not be probed again when the gpiochip driver is loaded. Fix the above issue by letting kirin_pcie_probe() return -EPROBE_DEFER in such a case. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bean Huo <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-09-28PCI: dwc: Fix 'cast truncates bits from constant value'Gustavo Pimentel1-1/+1
Fixes warning given by executing "make C=2 drivers/pci/" Sparse output: CHECK drivers/pci/controller/dwc/pcie-designware.c drivers/pci/controller/dwc/pcie-designware.c:432:52: warning: cast truncates bits from constant value (ffffffff7fffffff becomes 7fffffff) Link: https://lore.kernel.org/r/7ea7f7d342f97c758949a17b870012f52ce5b3f5.1600767645.git.gustavo.pimentel@synopsys.com Reported-by: Bjorn Helgaas <[email protected]> Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]>
2020-09-28PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macroLiu Shixin1-25/+3
Use DEFINE_SEQ_ATTRIBUTE macro to simplify the code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Liu Shixin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]>
2020-09-28PCI: hv: Document missing hv_pci_protocol_negotiation() parameterKrzysztof Wilczyński1-1/+4
Add missing documentation for the parameter "version" and "num_version" of the hv_pci_protocol_negotiation() function and resolve build time kernel-doc warnings: drivers/pci/controller/pci-hyperv.c:2535: warning: Function parameter or member 'version' not described in 'hv_pci_protocol_negotiation' drivers/pci/controller/pci-hyperv.c:2535: warning: Function parameter or member 'num_version' not described in 'hv_pci_protocol_negotiation' No change to functionality intended. Signed-off-by: Krzysztof Wilczyński <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Michael Kelley <[email protected]> Signed-off-by: Wei Liu <[email protected]>
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Modify MSI and MSIX CAP way of findingXiaowei Bao2-21/+118
Each PF of EP device should have its own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and move the msi_cap and msix_cap to this struct from dw_pcie_ep, and manage the PFs via a list. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-09-21PCI: designware-ep: Move the function of getting MSI capability forwardXiaowei Bao1-4/+4
Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Add the doorbell mode of MSI-X in EP modeXiaowei Bao2-0/+31
Add the doorbell mode of MSI-X in DWC EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Add multiple PFs support for DWCXiaowei Bao3-59/+143
Add multiple PFs support for DWC, due to different PF have different config space, we use func_conf_select callback function to access the different PF's config space, the different chip company need to implement this callback function when use the DWC IP core and intend to support multiple PFs feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2020-09-17PCI: brcmstb: Add bcm7278 PERST# supportJim Quinlan1-28/+69
The PERST# bit was moved to a different register in 7278-type STB chips. In addition, the polarity of the bit was also changed; for other chips writing a 1 specified assert; for 7278-type chips, writing a 0 specifies assert. Of course, PERST# is a PCIe asserted-low signal. While we are here, also change the bridge_sw_init_set() functions so like the perst_set() functions they are chip specific and we no longer rely on data wrt chip specific field mask and shift values. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-09-17PCI: brcmstb: Add suspend and resume pm_opsJim Quinlan1-0/+47
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend and resume. Now the PCIe driver may do so as well. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-09-17PCI: brcmstb: Add bcm7278 register infoJim Quinlan1-12/+93
Add in compatibility strings and code for three Broadcom STB chips. Some of the register locations, shifts, and masks are different for certain chips, requiring the use of different constants based on of_id. We would like to add the following at this time to the match list but we need to wait until the end of this patchset so that everything works. { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]> Acked-by: Rob Herring <[email protected]>
2020-09-17PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTBJim Quinlan1-1/+2
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to ARCH_BRCMSTB. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2020-09-16PCI/MSI: Make arch_.*_msi_irq[s] fallbacks selectableThomas Gleixner1-0/+3
The arch_.*_msi_irq[s] fallbacks are compiled in whether an architecture requires them or not. Architectures which are fully utilizing hierarchical irq domains should never call into that code. It's not only architectures which depend on that by implementing one or more of the weak functions, there is also a bunch of drivers which relies on the weak functions which invoke msi_controller::setup_irq[s] and msi_controller::teardown_irq. Make the architectures and drivers which rely on them select them in Kconfig and if not selected replace them by stub functions which emit a warning and fail the PCI/MSI interrupt allocation. Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16PCI_vmd_Mark_VMD_irqdomain_with_DOMAIN_BUS_VMD_MSIThomas Gleixner1-0/+6
Devices on the VMD bus use their own MSI irq domain, but it is not distinguishable from regular PCI/MSI irq domains. This is required to exclude VMD devices from getting the irq domain pointer set by interrupt remapping. Override the default bus token. Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Joerg Roedel <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16x86/msi: Use generic MSI domain opsThomas Gleixner1-8/+0
pci_msi_get_hwirq() and pci_msi_set_desc are not longer special. Enable the generic MSI domain ops in the core and PCI MSI code unconditionally and get rid of the x86 specific implementations in the X86 MSI code and in the hyperv PCI driver. Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16x86/msi: Consolidate MSI allocationThomas Gleixner1-1/+1
Convert the interrupt remap drivers to retrieve the pci device from the msi descriptor and use info::hwirq. This is the first step to prepare x86 for using the generic MSI domain ops. Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Wei Liu <[email protected]> Acked-by: Joerg Roedel <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16PCI: vmd: Dont abuse vector irqomain as parentThomas Gleixner1-1/+2
VMD has it's own PCI/MSI interrupt domain which is not in any way depending on the x86 vector domain. PCI devices behind VMD share the VMD MSIX vector entries via a VMD specific message translation to the actual VMD MSIX vector. The VMD device interrupt handler for the VMD MSIX vectors invokes all interrupt handlers of the devices which share a vector. Making the x86 vector domain the actual parent of the VMD irq domain is pointless and actually counterproductive. When a device interrupt is requested then it will activate the interrupt which traverses down the hierarchy and consumes an interrupt vector in the vector domain which is never used. The domain is self contained and has no parent dependencies, so just hand in NULL for the parent and be done with it. Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16PCI: hip: Add handling of HiSilicon HIP PCIe controller errorsYicong Yang3-0/+335
The HiSilicon HIP PCIe controller is capable of handling errors on root port and performing port reset separately at each root port. Add error handling driver for HIP PCIe controller to log and report recoverable errors. Perform root port reset and restore link status after the recovery. Following are some of the PCIe controller's recoverable errors 1. completion transmission timeout error. 2. CRS retry counter over the threshold error. 3. ECC 2 bit errors 4. AXI bresponse/rresponse errors etc. The driver placed in the drivers/pci/controller/ because the HIP PCIe controller does not use DWC IP. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Yicong Yang <[email protected]> Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc: Use DBI accessorsRob Herring2-10/+8
Convert the remaining cases of register accesses using dbi_base rather than dw_pcie_(read|write)[bwl]_dbi accessors. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-10PCI: dwc: Move N_FTS setup to common setupRob Herring5-85/+35
The Designware controller has common registers to set number of fast training sequence ordered sets. The Artpec6, Intel, and Tegra driver initialize these register fields. Let's move the initialization to the common setup code and drivers just have to provide the value. There's a slight change in that the common clock mode N_FTS field is now initialized. Previously only the Intel driver set this. It's not clear from the code if common clock mode is used in the Artpec6 or Tegra driver. It depends on the DWC configuration. Given the field is not initialized while the others are, it seems unlikely common clock mode is used. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-10PCI: dwc/intel-gw: Drop unused max_widthRob Herring1-4/+0
'max_width' is read, but never used, so let's remove it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()Rob Herring1-14/+1
The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so let's retrieve it there and avoid storing the offset. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' propertyRob Herring1-6/+0
A driver doesn't need to check for DT 'device_type' property, so let's remove the check. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup codeRob Herring2-4/+1
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The default value is set and it seems pretty certain that enabling link initialization is always required. Maybe it could just be dropped from the Intel driver, but lets move setting it into the common code to be sure. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc: Centralize link gen settingRob Herring11-151/+40
keystone would force gen2 if no DT property. Now it relies on the PCI_EXP_LNKCAP value. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-08PCI: rockchip: Fix bus checks in rockchip_pcie_valid_device()Lorenzo Pieralisi1-7/+4
The root bus checks rework in d84c572de1a3 ("PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus") caused a regression whereby in rockchip_pcie_valid_device() if the bus parameter is the root bus and the dev value == 0, the function should return 1 (ie true) without checking if the bus->parent pointer is a root bus because that triggers a NULL pointer dereference. Fix this by streamlining the root bus detection. Fixes: d84c572de1a3 ("PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus") Link: https://lore.kernel.org/r/[email protected] Reported-by: Samuel Dionne-Riel <[email protected]> Tested-by: Samuel Dionne-Riel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Shawn Lin <[email protected]>
2020-09-08PCI: iproc: Set affinity mask on MSI interruptsMark Tomlinson1-4/+9
The core interrupt code expects the irq_set_affinity call to update the effective affinity for the interrupt. This was not being done, so update iproc_msi_irq_set_affinity() to do so. Link: https://lore.kernel.org/r/[email protected] Fixes: 3bc2b2348835 ("PCI: iproc: Add iProc PCIe MSI support") Signed-off-by: Mark Tomlinson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Ray Jui <[email protected]>
2020-09-08PCI: mvebu: Remove useless msi_controller pointer allocationLorenzo Pieralisi1-3/+0
The mvebu host controller driver allocates an msi_controller structure pointer without allocating the structure and initializing its methods, which makes the pointer useless. This means that the PCI IRQ MSI layer ignores it and that after all it should not really be needed. Remove it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Rob Herring <[email protected]> Cc: Thomas Petazzoni <[email protected]>
2020-09-08PCI: dwc: Make ATU accessors privateRob Herring2-18/+6
The ATU registers are only accessed in pcie-designware.c and can be private to it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Remove read_dbi2 codeRob Herring3-36/+0
The DBI2 appears to be write-only and there's no read accesses in the code anyways, so let's remove all the read_dbi2 related code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-09-08PCI: dwc/tegra: Use common Designware port logic register definitionsRob Herring2-34/+28
The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
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