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2022-07-27PCI: brcmstb: Remove unnecessary forward declarationsJim Quinlan1-77/+72
Remove forward function declarations in this driver. Also move some constant structure definitions lower in the file. There are no changes to the code that has been moved. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Florian Fainelli <[email protected]>
2022-07-22PCI: tegra194: Add Tegra234 PCIe supportVidya Sagar1-59/+225
Add support for Synopsys DesignWare core IP based PCIe host controllers present in the Tegra234 SoC. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Extend Endpoint mode supportVidya Sagar1-0/+9
Since only Controller-5 can be used in the Endpoint mode in P2972-0000 platform, support is available only for Controller-5. Extend that support by enabling the Endpoint mode capable controller during initialization which otherwise is not required if it is only Controller-5. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Fix link up retry sequenceVidya Sagar1-1/+1
Add the missing DLF capability offset while clearing DL_FEATURE_EXCHANGE_EN bit during link up retry. Link: https://lore.kernel.org/r/[email protected] Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Clean up the exit path for Endpoint modeVidya Sagar1-14/+31
Clean up the exit path during .remove() and .shutdown() calls when in Endpoint mode. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Enable support for 256 Byte payloadVidya Sagar1-0/+13
Set 256 byte payload as the default in the Device Control Register to allow the PCIe subsystem to enable 256 byte Max Payload Size when a capable link partner is connected. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Clear bandwidth management statusVidya Sagar1-0/+6
In the event of a bandwidth management interrupt, clear the bandwidth management status in the configuration space also along with clearing corresponding status in the application logic register to avoid slew of interrupts. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Fix Root Port interrupt handlingVidya Sagar1-24/+22
As part of Root Port interrupt handling, level-0 register is read first and based on the bits set in that, corresponding level-1 registers are read for further interrupt processing. Since both these values are currently read into the same 'val' variable, checking level-0 bits the second time around is happening on the 'val' variable value of level-1 register contents instead of freshly reading the level-0 value again. Fix by using different variables to store level-0 and level-1 registers contents. Link: https://lore.kernel.org/r/[email protected] Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: tegra194: Find RAS DES PCIe capability offsetVidya Sagar2-37/+35
Find RAS DES PCIe capability offset instead of hardcoding the offset for each controller. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"Vidya Sagar1-111/+111
This reverts commit b572569183993b68dec0e990b33641e6f77744ba. Revert b57256918399 ("PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie") to keep the names of data structures generic and not contain any one particular chip name. This is a preparatory change for the upcoming changes that add support for Tegra234. This has no functional impact. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-22PCI: xilinx-cpm: Add support for Versal CPM5 Root PortBharat Kumar Gogada1-2/+58
The Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has a few changes from the existing CPM block: - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Add support for the new CPM5 features. [bhelgaas: compare variant->version with CPM5 explicitly] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bharat Kumar Gogada <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-21PCI: loongson: Work around LS7A incorrect Interrupt Pin registersJianmin Lv1-1/+27
Several devices integrated into LS7A report 1 (which means they use INTA) in their Interrupt Pin registers, but they actually use a different interrupt. Add a quirk to override the incorrect Interrupt Pin values. This is only needed by ACPI-based systems. For DT-based systems, pci_assign_irq() ignores the Interrupt Pin register except to learn that the device uses INTx and the host bridge .map_irq() function (loongson_map_irq()) learns the IRQ mapping via DT and of_irq_parse_pci(). [bhelgaas: drop PCIE_PORT_x, OHCI, GPU since they are function 0 and don't need the quirk, squash in updates from https://lore.kernel.org/r/CAAhV-H40_o+9KS1t67O98GusM38pDaiB4bssxd3KQZpAByfnLg@mail.gmail.com] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jianmin Lv <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-19PCI: fu740: Remove unnecessary include filesBjorn Helgaas1-2/+0
fu740 uses no syscon or regman interfaces, so it doesn't need to include mfs/syscon.h. It uses no regulator interfaces, so it doesn't need to include regulator/consumer.h either. Remove both unnecessary includes. Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-15PCI: qcom: Add IPQ60xx supportSelvam Sathappan Periakaruppan2-0/+131
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform. The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0). Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on(). [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il Tested-by: Robert Marko <[email protected]> Signed-off-by: Selvam Sathappan Periakaruppan <[email protected]> Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-07-15PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*Baruch Siach1-2/+15
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning. Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-07-15PCI: dwc: Move GEN3_RELATED DBI definitions to common headerBaruch Siach2-6/+6
These are common dwc macros that will be used for other platforms. Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-15PCI: qcom: Drop manual pipe_clk_src handlingDmitry Baryshkov1-38/+1
Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable() in the PHY driver. Drop redundant code switching of the pipe clock between the PHY clock source and the safe bi_tcxo. Link: https://lore.kernel.org/r/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-07-14PCI: loongson: Don't access non-existent devicesHuacai Chen1-6/+23
On LS2K/LS7A, config reads to some non-existent devices don't return 0xffffffff (they are hidden devices for debug, and accessing the config space may cause machine hang). This is a hardware flaw but we can only avoid it by software now. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-14PCI: loongson: Add ACPI init supportHuacai Chen2-20/+76
Loongson PCH (LS7A chipset) will be used by both MIPS-based and LoongArch- based Loongson processors. MIPS-based Loongson uses FDT, while LoongArch- based Loongson uses ACPI. Add ACPI init support for the driver in pci-loongson.c because it is currently FDT-only. LoongArch is a new RISC ISA, mainline support will come soon, and documentations are here (in translation): https://github.com/loongson/LoongArch-Documentation Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-14PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7AHuacai Chen1-19/+46
LS2K/LS7A support 8/16/32-bits PCI config access operations via CFG1, so we can disable CFG0 for them and safely use pci_generic_config_read()/ pci_generic_config_write() instead of pci_generic_config_read32()/pci_ generic_config_write32(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Bjorn Helgaas <[email protected]>
2022-07-14PCI: qcom: Remove unnecessary pipe_clk handlingDmitry Baryshkov1-34/+3
PCIe PHY drivers (both QMP and PCIe2) already do clk_prepare_enable() / clk_prepare_disable() pipe_clk. Remove extra calls to enable/disable this clock from the PCIe driver, so that the PHY driver can manage the clock on its own. [bhelgaas: rebase on Robert Marko's DBI cleanup: https://lore.kernel.org/r/[email protected]] Link: https://lore.kernel.org/r/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-07-13PCI: qcom: Power on PHY before DBI register accessesRobert Marko1-73/+95
IPQ8074 requires the PHY to be powered on before accessing DBI registers. It's not clear whether other variants have the same dependency, but there seems to be no reason for them to be different, so move all the DBI accesses from .init() to .post_init() so they are all after phy_power_on(). [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-13PCI: qcom: Power on PHY before IPQ8074 DBI register accessesRobert Marko1-20/+28
Currently the Gen2 port in IPQ8074 will cause the system to hang as it accesses DBI registers in qcom_pcie_init_2_3_3(), and those are only accesible after phy_power_on(). Move the DBI read/writes to a new qcom_pcie_post_init_2_3_3(), which is executed after phy_power_on(). Link: https://lore.kernel.org/r/[email protected] Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code") Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Cc: [email protected] # v5.11+
2022-07-13PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocksChristian Marangi1-6/+4
We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to enable clocks and resets. This causes the driver to never set to a ready state with the error 'Phy link never came up'. This is caused by the PHY clock getting enabled before setting the required bits in the PARF regs. A workaround for this was set but with this new discovery we can drop the workaround and use a proper solution to the problem by just enabling the clock only AFTER the PARF_PHY_CTRL bit is set. This correctly sets up the PCIe link and makes it usable even when a bootloader leaves the PCIe link in an undefined state. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-08PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu()Samuel Holland1-1/+1
The cpumask that is passed to this function ultimately comes from irq_data_get_effective_affinity_mask(), which was recently changed to return a const cpumask pointer. The first level of functions handling the affinity mask were updated, but not this helper function. Fixes: 4d0b8298818b ("genirq: Return a const cpumask from irq_data_get_affinity_mask") Reported-by: kernel test robot <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Michael Kelley <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-07genirq: Return a const cpumask from irq_data_get_affinity_maskSamuel Holland1-5/+5
Now that the irq_data_update_affinity helper exists, enforce its use by returning a a const cpumask from irq_data_get_affinity_mask. Since the previous commit already updated places that needed to call irq_data_update_affinity, this commit updates the remaining code that either did not modify the cpumask or immediately passed the modified mask to irq_set_affinity. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Michael Kelley <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-07-06PCI: Drop of_match_ptr() to avoid unused variablesBjorn Helgaas4-4/+4
We have stubs for most OF interfaces even when CONFIG_OF is not set, so we allow building of most controller drivers in that case for compile testing. When CONFIG_OF is not set, "of_match_ptr(<match_table>)" compiles to NULL, which leaves <match_table> unused, resulting in errors like this: $ make W=1 drivers/pci/controller/pci-xgene.c:636:34: error: ‘xgene_pcie_match_table’ defined but not used [-Werror=unused-const-variable=] Drop of_match_ptr() to avoid the unused variable warning. Signed-off-by: Bjorn Helgaas <[email protected]>
2022-07-05PCI: dwc-plat: Drop dw_plat_pcie_of_match[] forward declarationSerge Semin1-2/+0
The dw_plat_pcie_of_match[] forward declaration was required when dw_plat_pcie_probe() called of_match_device(). 5c204204cf24 ("PCI: designware-plat: Prefer of_device_get_match_data()") replaced that with of_device_get_match_data(), which no longer needs the declaration. Drop the unnecessary forward declaration. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc-plat: Drop unused regmap pointerSerge Semin1-2/+0
1d906b22076e ("PCI: dwc: Add support for EP mode") added the struct dw_plat_pcie regmap pointer, but it has never been used. Remove it. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc-plat: Simplify dw_plat_pcie_probe() return valuesSerge Semin1-4/+5
Save the return value in "ret" for all three cases (DW_PCIE_RC_TYPE, DW_PCIE_EP_TYPE, default) handled by dw_plat_pcie_probe() and return from a single place. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Rename struct pcie_port to dw_pcie_rpSerge Semin23-103/+103
All of the DW PCIe core driver entities except the pcie_port struct have names with the "dw_" prefix to distinguish local and common PCIe name spaces, and endpoint-related entities have an "_ep" suffix. Rename struct pcie_port to dw_pcie_rp to make it more consistent with other names. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Jesper Nilsson <[email protected]>
2022-07-05PCI: dwc: Move io_cfg_atu_shared to struct pcie_portSerge Semin2-4/+4
The io_cfg_atu_shared flag is set if there is an outbound iATU window used for both config space accesses and IO port transfers. Since the flag semantic is purely Root Port specific, it's not used in either the DW PCIe common code or in the DW PCIe Endpoint driver. Move it to the struct pcie_port and rename to cfg0_io_shared. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Add start_link/stop_link inlinesSerge Semin5-34/+20
Factor out this pattern: if (!pci->ops || !pci->ops->start_link) return -EINVAL; return pci->ops->start_link(pci); into a new dw_pcie_start_link() wrapper and do the same for the stop_link() method. Note that dw_pcie_ep_start() previously returned -EINVAL if there was no platform start_link() method, which didn't make much sense since that is not an error. It will now return 0 in that case. As a side-effect, drop the empty start_link() and dummy dw_pcie_ops instances from the generic DW PCIe and Layerscape EP platform drivers. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Reuse local pointer to the resource dataSerge Semin1-8/+8
dw_pcie_host_init() has two instances of the resource structure pointers used in unrelated places. It's pointless to have two different local storages for them since the corresponding code is small and having resource-specific names doesn't make it more readable. Convert these parts of the function to use a common pointer to the resource structure instance. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Organize local variable usageSerge Semin2-10/+8
There are several places in the common DW PCIe code with incoherent local variable usage: a variable is defined and initialized with a structure field, but the structure pointer is dereferenced to access that field anyway; the local variable is defined and initialized but either used just once or not used afterwards in the main part of the subsequent method. It mainly concerns the pcie_port.dev field. Fix that in the relevant places. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Convert dw_pcie_link_up() to use dw_pcie_readl_dbi()Serge Semin1-1/+1
While the rest of the generic DWC PCIe code uses the dedicated IO-mem accessors, the dw_pcie_link_up() method for some unobvious reason directly calls readl() to get PortLogic.DEBUG1 register content. Since the way the DBI bus is accessed can be platform-specific, use dw_pcie_readl_dbi() instead so dw_pcie_link_up() is slightly more generic. Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Simplify unrolled iATU detectionSerge Semin1-6/+5
The unrolled version of the internal ATU has been available since the DWC PCIe v4.80a IP core, but it may not be enabled. Per [1], if unrolled ATU is enabled, the PCIE_ATU_VIEWPORT does not exist and reads as 0xffffffff; while if unrolled ATU is disabled, PCIE_ATU_VIEWPORT will contain some zeros. Simplify dw_pcie_iatu_unroll_enabled() by checking the value of PCIE_ATU_VIEWPORT. [1] DesignWare Cores, PCI Express Controller, Register Desciptions, v.4.90a, December 2016, p.855 [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Add newlines to log messagesSerge Semin2-2/+2
Add newlines to log messages that are missing them. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Add braces to multi-line if-else statementsSerge Semin2-3/+4
Add braces around single-line if-else statements when the opposite case requires them. Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" existsSerge Semin1-7/+7
If the "snps,enable-cdm-check" property exists, we should enable the CDM check. But previously dw_pcie_setup() could exit before doing so if the "num-lanes" property was absent or invalid. Move the CDM enable earlier so we do it regardless of whether "num-lanes" is present. [bhelgaas: commit log] Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Vidya Sagar <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Deallocate EPC memory on dw_pcie_ep_init() errorsSerge Semin1-2/+16
If dw_pcie_ep_init() fails to perform any action after the EPC memory is initialized and the MSI memory region is allocated, the latter parts won't be undone thus causing a memory leak. Add a cleanup-on-error path to fix these leaks. [bhelgaas: commit log] Fixes: 2fd0c9d966cc ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init") Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2022-07-05PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit addressSerge Semin1-6/+10
We program the 64-bit ATU limit address (in PCIE_ATU_LIMIT/ PCIE_ATU_UPPER_LIMIT or PCIE_ATU_UNR_LOWER_LIMIT/PCIE_ATU_UNR_UPPER_LIMIT), but in addition, the PCIE_ATU_INCREASE_REGION_SIZE bit must be set if the upper 32 bits of the limit address differ from the upper 32 bits of the base address (see [1,2]). 5b4cf0f65324 ("PCI: dwc: Add upper limit address for outbound iATU") set PCIE_ATU_INCREASE_REGION_SIZE, but only when the *size* was greater than 4GB. It did not set it when a smaller region crossed a 4GB boundary, e.g., [mem 0x0_f0000000-0x1_0fffffff]. Set PCIE_ATU_INCREASE_REGION_SIZE whenever PCIE_ATU_UPPER_LIMIT is greater than PCIE_ATU_UPPER_BASE. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-36, p.175 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-37, p.176 [bhelgaas: commit log] Fixes: 5b4cf0f65324 ("PCI: dwc: Add upper limit address for outbound iATU") Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Disable outbound windows only for controllers using iATUSerge Semin1-6/+8
Some DWC-based controllers (e.g., pcie-al.c and pci-keystone.c, identified by the fact that they override the default dw_child_pcie_ops) use their own address translation approach instead of the DWC internal ATU (iATU). For those controllers, skip disabling the iATU outbound windows. [bhelgaas: commit log, update multiple window comment] Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset") Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Add unroll iATU space support to dw_pcie_disable_atu()Serge Semin1-3/+13
dw_pcie_disable_atu() was introduced by f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") and supported only the viewport version of the iATU CSRs. DW PCIe IP cores v4.80a and newer also support unrolled iATU/eDMA space. Callers of dw_pcie_disable_atu(), including pci_epc_ops.clear_bar(), pci_epc_ops.unmap_addr(), and dw_pcie_setup_rc(), don't work correctly when it is enabled. Add dw_pcie_disable_atu() support for controllers with unrolled iATU CSRs enabled. [bhelgaas: commit log] Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: dwc: Stop link on host_init errors and de-initializationSerge Semin1-2/+14
It's logically correct to undo everything that was done when an error is discovered or in the corresponding cleanup counterpart. Otherwise the host controller will be left in an undetermined state. Since the link is set up in the host_init method, deactivate it there in the cleanup-on-error block and stop the link in the antagonistic routine - dw_pcie_host_deinit(). Link deactivation is platform-specific and should be implemented in dw_pcie_ops.stop_link(). Fixes: 886a9c134755 ("PCI: dwc: Move link handling into common code") Link: https://lore.kernel.org/r/[email protected] Tested-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-07-05PCI: iproc: Use bitmap API to allocate bitmapsChristophe JAILLET1-2/+2
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. Link: https://lore.kernel.org/r/d839a951358ceb447226dc776590a2a38f3e3f9d.1656940469.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Ray Jui <[email protected]>
2022-06-28PCI: vmd: Add DID 8086:7D0B and 8086:AD0B for Intel MTL SKUsFrancisco Munoz1-0/+8
Add support for VMD devices in MTL-H/P/U/S/M with bus restriction mode and vector 0 disabled for MSI-X remapping. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Francisco Munoz <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Nirmal Patel <[email protected]>
2022-06-23PCI: rcar-gen2: Add RZ/N1 SOC family compatible stringHerve Codina1-0/+1
Add Renesas RZ/N1 SOC family support to the Renesas R-Car Gen2 PCI bridge driver. The Renesas RZ/N1 SOC internal PCI bridge is compatible with the one in the R-Car Gen2 family. Tested with the RZ/N1D (R9A06G032) SOC. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Herve Codina <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]>
2022-06-15PCI: mediatek-gen3: Print LTSSM state when PCIe link downJianjun Wang1-1/+40
Print current LTSSM state when PCIe link down instead of the register value to make it easier to get the link status. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jianjun Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
2022-06-15PCI: mediatek: Allow building for ARCH_AIROHAFelix Fietkau1-1/+1
Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the Airoha EN7523 SoC uses the same controller as MT7622. The driver itself is not modified. The PCIe controller DT node should use mediatek,mt7622-pcie after airoha,en7523-pcie. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
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