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2022-01-13Merge branch 'remotes/lorenzo/pci/bridge-emul'Bjorn Helgaas2-1/+11
- Make emulated ROM BAR read-only by default (Pali Rohár) - Make some emulated legacy PCI bits read-only for PCIe devices (Pali Rohár) - Update reserved bits in emulated PCIe Capability (Pali Rohár) - Allow drivers to emulate different PCIe Capability versions (Pali Rohár) - Set emulated Capabilities List bit for all PCIe devices, since they must have at least a PCIe Capability (Pali Rohár) * remotes/lorenzo/pci/bridge-emul: PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device PCI: pci-bridge-emul: Correctly set PCIe capabilities PCI: pci-bridge-emul: Fix definitions of reserved bits PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
2022-01-13Merge branch 'remotes/lorenzo/pci/xilinx-nwl'Bjorn Helgaas1-23/+7
- Declare bitmap correctly and as part of struct nwl_msi managed resource (Christophe JAILLET) * remotes/lorenzo/pci/xilinx-nwl: PCI: xilinx-nwl: Simplify code and fix a memory leak
2022-01-13Merge branch 'remotes/lorenzo/pci/xgene'Bjorn Helgaas2-5/+3
- Use bitmap ops for MSI allocator (Christophe JAILLET) - Fix IB window setup, which was broken by the fact that IB resources are now sorted in address order instead of DT dma-ranges order (Rob Herring) * remotes/lorenzo/pci/xgene: PCI: xgene: Fix IB window setup PCI: xgene-msi: Use bitmap_zalloc() when applicable
2022-01-13Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas1-0/+59
- Reset everything below VMD before enumerating to work around failure to enumerate NVMe devices when guest OS reboots (Nirmal Patel) - Honor platform ACPI _OSC feature negotiation for Root Ports below VMD (Kai-Heng Feng) - Add support for Raptor Lake SKUs (Karthik L Gopalakrishnan) * remotes/lorenzo/pci/vmd: PCI: vmd: Add DID 8086:A77F for all Intel Raptor Lake SKU's PCI: vmd: Honor ACPI _OSC on PCIe features PCI: vmd: Clean up domain before enumeration
2022-01-13Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas1-5/+5
- Fix aarch32 abort handler so it doesn't check the wrong bus clock before accessing the host controller (Marek Vasut) * remotes/lorenzo/pci/rcar: PCI: rcar: Check if device is runtime suspended instead of __clk_is_enabled()
2022-01-13Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas2-8/+8
- Undo PM setup in qcom_pcie_probe() error handling path (Christophe JAILLET) - Use __be16 type to store return value from cpu_to_be16() (Manivannan Sadhasivam) - Constify static dw_pcie_ep_ops (Rikard Falkeborn) * remotes/lorenzo/pci/qcom: PCI: qcom-ep: Constify static dw_pcie_ep_ops PCI: qcom: Use __be16 type to store return value from cpu_to_be16() PCI: qcom: Fix an error handling path in 'qcom_pcie_probe()'
2022-01-13Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas2-133/+395
- Implement pci_remap_iospace() for ARM so mvebu can use devm_pci_remap_iospace() instead of the previous ARM-specific pci_ioremap_io() interface (Pali Rohár) - Use the standard pci_host_probe() instead of the device-specific mvebu_pci_host_probe() (Pali Rohár) - Replace all uses of ARM-specific pci_ioremap_io() with the ARM implementation of the standard pci_remap_iospace() interface and remove pci_ioremap_io() (Pali Rohár) - Skip initializing invalid Root Ports (Pali Rohár) - Check for errors from pci_bridge_emul_init() (Pali Rohár) - Ignore any bridges at non-zero function numbers (Pali Rohár) - Return ~0 data for invalid config read size (Pali Rohár) - Disallow mapping interrupts on emulated bridges (Pali Rohár) - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at initialization (Pali Rohár) - Make type bits in Root Port I/O Base register read-only (Pali Rohár) - Disable Root Port windows when base/limit set to invalid values (Pali Rohár) - Set controller to Root Complex mode (Pali Rohár) - Set Root Port Class Code to PCI Bridge (Pali Rohár) - Update emulated Root Port secondary bus numbers to better reflect the actual topology (Pali Rohár) - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so pci_reset_secondary_bus() can reset connected devices (Pali Rohár) - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports (Pali Rohár) - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali Rohár) - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada XP and newer devices (Pali Rohár) - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali Rohár) - Add support for compiling as a module (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Add support for compiling driver as module bus: mvebu-mbus: Export symbols for public API window functions PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge PCI: mvebu: Setup PCIe controller to Root Complex mode PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers PCI: mvebu: Do not modify PCI IO type bits in conf_write PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge PCI: mvebu: Disallow mapping interrupts on emulated bridges PCI: mvebu: Handle invalid size of read config request PCI: mvebu: Check that PCI bridge specified in DT has function number zero PCI: mvebu: Check for errors from pci_bridge_emul_init() call PCI: mvebu: Check for valid ports arm: ioremap: Remove unused ARM-specific function pci_ioremap_io() arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace() PCI: mvebu: Remove custom mvebu_pci_host_probe() function PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace() arm: ioremap: Implement standard PCI function pci_remap_iospace()
2022-01-13Merge branch 'pci/host/mt7621'Bjorn Helgaas2-39/+4
- Declare mt7621_pci_ops static (Sergio Paracuellos) - Give pcibios_root_bridge_prepare() access to host bridge windows (Sergio Paracuellos) - Move MIPS I/O coherency unit setup from driver to pcibios_root_bridge_prepare() (Sergio Paracuellos) - Add missing MODULE_LICENSE() (Sergio Paracuellos) - Allow COMPILE_TEST for all arches (Sergio Paracuellos) * pci/host/mt7621: PCI: mt7621: Allow COMPILE_TEST for all arches PCI: mt7621: Add missing MODULE_LICENSE() PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare() PCI: Let pcibios_root_bridge_prepare() access bridge->windows PCI: mt7621: Declare mt7621_pci_ops static
2022-01-13Merge branch 'remotes/lorenzo/pci/mediatek-gen3'Bjorn Helgaas1-0/+8
- Disable Mediatek DVFSRC voltage request since lack of DVFSRC to respond to the request causes failure to exit L1 PM Substate (Jianjun Wang) * remotes/lorenzo/pci/mediatek-gen3: PCI: mediatek-gen3: Disable DVFSRC voltage request
2022-01-13Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas1-0/+7
- Assert PERST# for 100ms to allow power and clock to stabilize (qizhong cheng) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
2022-01-13Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas1-3/+24
- Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode DT properties (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument
2022-01-13Merge branch 'pci/host/hv'Bjorn Helgaas2-26/+288
- Add hv-internal interfaces to encapsulate arch IRQ dependencies (Sunil Muthuswamy) - Add arm64 Hyper-V vPCI support (Sunil Muthuswamy) * pci/host/hv: PCI: hv: Add arm64 Hyper-V vPCI support PCI: hv: Make the code arch neutral by adding arch specific interfaces
2022-01-13Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas4-155/+89
- Don't ioremap NULL when DT lacks ATU resource (Tim Harvey) - Drop redundant qcom-ep error message for platform_get_irq_byname() failure (Krzysztof Wilczyński) - Add i.MX8MM support (Richard Zhu) - Use DWC common ops instead of layerscape-specific link-up functions (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: PCI: layerscape: Change to use the DWC common link-up check function PCI: imx: Add the imx8mm pcie support dt-bindings: imx6q-pcie: Add PHY phandles and name properties PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname() PCI: dwc: Do not remap invalid res
2022-01-13Merge branch 'pci/host/brcmstb'Bjorn Helgaas1-41/+263
- Declare bitmap correctly for use by bitmap interfaces (Christophe JAILLET) - Clean up computation of legacy and non-legacy MSI bitmasks (Florian Fainelli) - Update suspend/resume/remove error handling to warn about errors and not fail the operation (Jim Quinlan) - Correct the "pcie" and "msi" interrupt descriptions in DT binding (Jim Quinlan) - Add DT bindings for endpoint voltage regulators (Jim Quinlan) - Split brcm_pcie_setup() into two functions (Jim Quinlan) - Add mechanism for turning on voltage regulators for connected devices (Jim Quinlan) - Turn voltage regulators for connected devices on/off when bus is added or removed (Jim Quinlan) - When suspending, don't turn off voltage regulators for wakeup devices (Jim Quinlan) * pci/host/brcmstb: PCI: brcmstb: Do not turn off WOL regulators on suspend PCI: brcmstb: Add control of subdevice voltage regulators PCI: brcmstb: Add mechanism to turn on subdev regulators PCI: brcmstb: Split brcm_pcie_setup() into two funcs dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map. PCI: brcmstb: Fix function return value handling PCI: brcmstb: Do not use __GENMASK PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
2022-01-13Merge branch 'remotes/lorenzo/pci/apple'Bjorn Helgaas1-3/+7
- Enable clock gating to save power (Hector Martin) - Fix REFCLK1 enable/poll logic (Hector Martin) * remotes/lorenzo/pci/apple: PCI: apple: Fix REFCLK1 enable/poll logic PCI: apple: Enable clock gating
2022-01-12PCI: mt7621: Allow COMPILE_TEST for all archesSergio Paracuellos1-1/+1
Since all MIPS-specific code has been removed from driver, allow it to be enabled for COMPILE_TEST on all architectures. Mark it as tristate and remove MIPS the MIPS dependency. Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-12PCI: mt7621: Add missing MODULE_LICENSE()Sergio Paracuellos1-0/+2
The MT7621 PCIe host controller driver can be built as a module, but it lacks a MODULE_LICENSE(), which causes a build error: ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/controller/pcie-mt7621.o Add MODULE_LICENSE() to the driver. Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Yanteng Si <[email protected]> Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2022-01-12PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()Sergio Paracuellos1-37/+0
On the MIPS ralink mt7621 platform, we need to set up I/O coherency units based on the host bridge apertures. To remove this arch dependency from the driver itself, move the coherency setup from the driver to pcibios_root_bridge_prepare(). [bhelgaas: squash add/remove into one patch, commit log] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Guenter Roeck <[email protected]> # arch/mips Acked-by: Thomas Bogendoerfer <[email protected]> # arch/mips
2022-01-12PCI: mt7621: Declare mt7621_pci_ops staticSergio Paracuellos1-1/+1
Sparse complains about mt7621_pci_ops symbol is not declared and asks if it should be declared as static instead. Sparse is right. Hence declare symbol as static. Link: https://lore.kernel.org/r/[email protected] Reported-by: kernel test robot <[email protected]> Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2022-01-12PCI: brcmstb: Do not turn off WOL regulators on suspendJim Quinlan1-9/+44
If any downstream device can be a wakeup device, do not turn off the regulators as the device will need them on. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-12PCI: brcmstb: Add control of subdevice voltage regulatorsJim Quinlan1-5/+78
This Broadcom STB PCIe RC driver has one port and connects directly to one device, be it a switch or an endpoint. We want to be able to leverage the recently added mechanism that allocates and turns on/off subdevice regulators. All that needs to be done is to put the regulator DT nodes in the bridge below host and to set the pci_ops methods add_bus and remove_bus. Note that the pci_subdev_regulators_add_bus() method is wrapped for two reasons: 1. To achieve link up after the voltage regulators are turned on. 2. If, in the case of an unsuccessful link up, to redirect any PCIe accesses to subdevices, e.g. the scan for DEV/ID. This redirection is needed because the Broadcom PCIe HW will issue a CPU abort if such an access is made when the link is down. [bhelgaas: fold in https://lore.kernel.org/r/[email protected]] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-12PCI: brcmstb: Add mechanism to turn on subdev regulatorsJim Quinlan1-0/+76
Add a mechanism to identify standard PCIe regulators in the DT, allocate them, and turn them on before the rest of the bus is scanned during pci_host_probe(). The allocated structure that contains the regulators is stored in the port driver dev.driver_data field. Here is a point-by-point of how and when this mechanism is activated: If: -- PCIe RC driver sets pci_ops {add,remove)_bus to pci_subdev_regulators_{add,remove}_bus during its probe. -- There is a DT node "RB" under the host bridge DT node. -- During the RC driver's pci_host_probe() the add_bus callback is invoked where (bus->parent && pci_is_root_bus(bus->parent) is true Then: -- A struct subdev_regulators structure will be allocated and assigned to bus->dev.driver_data. -- regulator_bulk_{get,enable} will be invoked on &bus->dev and the former will search for and process any vpcie{12v,3v3,3v3aux}-supply properties that reside in node "RB". -- The regulators will be turned off/on for any unbind/bind operations. -- The regulators will be turned off/on for any suspend/resumes, but only if the RC driver handles this on its own. This will appear in a later commit for the pcie-brcmstb.c driver. The unabridged reason for doing this is as follows. We would like the Broadcom STB PCIe root complex driver (and others) to be able to turn off/on regulators[1] that provide power to endpoint[2] devices. Typically, the drivers of these endpoint devices are stock Linux drivers that are not aware that these regulator(s) exist and must be turned on for the driver to be probed. The simple solution of course is to turn these regulators on at boot and keep them on. However, this solution does not satisfy at least three of our usage modes: 1. For example, one customer uses multiple PCIe controllers, but wants the ability to, by script invoking and unbind, turn any or all of them and their subdevices off to save power, e.g. when in battery mode. 2. Another example is when a watchdog script discovers that an endpoint device is in an unresponsive state and would like to unbind, power toggle, and re-bind just the PCIe endpoint and controller. 3. Of course we also want power turned off during suspend mode. However, some endpoint devices may be able to "wake" during suspend and we need to recognise this case and veto the nominal act of turning off its regulator. Such is the case with Wake-on-LAN and Wake-on-WLAN support where the PCIe endpoint device needs to be kept powered on in order to receive network packets and wake the system. In all of these cases it is advantageous for the PCIe controller to govern the turning off/on the regulators needed by the endpoint device. The first two cases can be done by simply unbinding and binding the PCIe controller, if the controller has control of these regulators. [1] These regulators typically govern the actual power supply to the endpoint chip. Sometimes they may be the official PCIe socket power -- such as 3.3v or aux-3.3v. Sometimes they are truly the regulator(s) that supply power to the EP chip. [2] The 99% configuration of our boards is a single endpoint device attached to the PCIe controller. I use the term endpoint but it could possibly mean a switch as well. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-12PCI: brcmstb: Split brcm_pcie_setup() into two funcsJim Quinlan1-26/+39
We need to take some code in brcm_pcie_setup() and put it in a new function brcm_pcie_linkup(). In future commits the brcm_pcie_linkup() function will be called indirectly by pci_host_probe() as opposed to the host driver invoking it directly. Some code that was executed after the PCIe linkup is now placed so that it executes prior to linkup, since this code has to run prior to the invocation of pci_host_probe(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-12PCI: brcmstb: Fix function return value handlingJim Quinlan1-6/+22
Do at least a dev_err() on some calls to reset_control_rearm() and brcm_phy_stop(). In some cases it may not make sense to return this error value "above" as doing so will cause more trouble than is warranted. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2022-01-12PCI: brcmstb: Do not use __GENMASKFlorian Fainelli1-1/+5
Define the legacy MSI interrupt bitmask as well as the non-legacy interrupt bitmask using GENMASK and then use them in brcm_msi_set_regs() in place of __GENMASK(). Link: https://lore.kernel.org/r/[email protected] Reported-by: Andy Shevchenko <[email protected]> Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]>
2022-01-12PCI: brcmstb: Declare 'used' as bitmap, not unsigned longChristophe JAILLET1-4/+9
The 'used' field of 'struct brcm_msi' is used as a bitmap. Declare it with DECLARE_BITMAP() and adjust users accordingly. This fixes a harmless Coverity warning about array vs singleton usage. This bitmap can be used for either legacy or MSI interrupts, which require a size of BRCM_INT_PCI_MSI_LEGACY_NR or BRCM_INT_PCI_MSI_NR respectively. Add a BUILD_BUG_ON() to ensure it is large enough. Suggested-by: Krzysztof Wilczynski <[email protected]> Addresses-Coverity: "Out-of-bounds access (ARRAY_VS_SINGLETON)" Link: https://lore.kernel.org/r/e6d9da2112aab2939d1507b90962d07bfd735b4c.1636273671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
2022-01-12PCI: hv: Add arm64 Hyper-V vPCI supportSunil Muthuswamy2-2/+235
Add arm64 Hyper-V vPCI support by implementing the arch specific interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI that is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domain for basic vector management. [bhelgaas: squash in fix from Yang Li <[email protected]>: https://lore.kernel.org/r/[email protected]] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sunil Muthuswamy <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Reviewed-by: Michael Kelley <[email protected]>
2022-01-12PCI: hv: Make the code arch neutral by adding arch specific interfacesSunil Muthuswamy1-25/+54
Encapsulate arch dependencies in Hyper-V vPCI through a set of arch-dependent interfaces. Adding these arch specific interfaces will allow for an implementation for other architectures, such as arm64. There are no functional changes expected from this patch. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sunil Muthuswamy <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Boqun Feng <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Reviewed-by: Michael Kelley <[email protected]>
2022-01-11PCI: brcmstb: Augment driver for MIPs SOCsJim Quinlan2-5/+79
The current brcmstb driver works for Arm and Arm64. A few things are modified here for us to support MIPs as well. o There are four outbound range register groups and each directs a window of up to 128MB. Even though there are four 128MB DT "ranges" in the bmips PCIe DT node, these ranges are contiguous and are collapsed into a single range by the OF range parser. Now the driver assumes a single range -- for MIPs only -- and splits it back into 128MB sizes. o For bcm7425, the config space accesses must be 32-bit reads or writes. In addition, the 4k config space register array is missing and not used. o The registers for the upper 32-bits of the outbound window address do not exist. o Burst size must be set to 256 (this refers to an internal bus). Signed-off-by: Jim Quinlan <[email protected]> Acked-by: Florian Fainelli <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2022-01-07PCI: Correct misspelled wordsKrzysztof Wilczyński2-2/+2
Fix a number of misspelled words, and while at it, correct two phrases used to indicate a status of an operation where words used have been cleverly truncated and thus always trigger a spellchecking error while performing a static code analysis over the PCI tree. [bhelgaas: reverse sense of quirk ternary] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-07PCI: keystone: Use phandle argument from ↵Kishon Vijay Abraham I1-3/+24
"ti,syscon-pcie-id"/"ti,syscon-pcie-mode" Get "syscon" pcie_mode and pcie_id offset from the argument of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle respectively. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_mode and pcie_id but now the offset of pcie_mode and pcie_id within "syscon" is now being passed as argument to "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle. If the offset is not provided in "ti,syscon-pcie-id"/"ti,syscon-pcie-mode", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. Similar change for J721E is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-07PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilizeqizhong cheng1-0/+7
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: qizhong cheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Pali Rohár <[email protected]>
2022-01-06PCI: mvebu: Add support for compiling driver as modulePali Rohár2-16/+77
Now when driver uses devm_pci_remap_iospace() function, it is possible implement ->remove() callback for unbinding device from driver. Implement mvebu_pcie_remove() callback with proper cleanup phase, drop driver's suppress_bind_attrs flag and switch type of CONFIG_PCI_MVEBU option from bool to tristate. This allows to compile pci-mvebu.c driver as loadable module pci-mvebu.ko with ability to unload it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-05PCI: vmd: Add DID 8086:A77F for all Intel Raptor Lake SKU'sKarthik L Gopalakrishnan1-0/+4
Add support for this VMD device which supports the bus restriction mode. The feature that turns off vector 0 for MSI-X remapping is also enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Karthik L Gopalakrishnan <[email protected]> Signed-off-by: Francisco Munoz <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Jon Derrick <[email protected]>
2022-01-05PCI: layerscape: Change to use the DWC common link-up check functionHou Zhiqiang1-141/+11
The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2022-01-04PCI: qcom-ep: Constify static dw_pcie_ep_opsRikard Falkeborn1-1/+1
The only usage of pci_ep_ops is to assign its address to the ops field in the dw_pcie_ep struct which is a pointer to const struct dw_pcie_ep_ops. Make it const to allow the compiler to put it in read-only memory. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rikard Falkeborn <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2022-01-04PCI: vmd: Honor ACPI _OSC on PCIe featuresKai-Heng Feng1-0/+18
When Samsung PCIe Gen4 NVMe is connected to Intel ADL VMD, the combination causes AER message flood and drags the system performance down. The issue doesn't happen when VMD mode is disabled in BIOS, since AER isn't enabled by acpi_pci_root_create() . When VMD mode is enabled, AER is enabled regardless of _OSC: [ 0.410076] acpi PNP0A08:00: _OSC: platform does not support [AER] ... [ 1.486704] pcieport 10000:e0:06.0: AER: enabled with IRQ 146 Since VMD is an aperture to regular PCIe root ports, honor ACPI _OSC to disable PCIe features accordingly to resolve the issue. Suggested-by: Rafael J. Wysocki <[email protected]> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=215027 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kai-Heng Feng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rafael J. Wysocki <[email protected]>
2022-01-04PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on ↵Pali Rohár1-0/+23
emulated bridge Armada XP and new hardware supports access to DEVCAP2, DEVCTL2 and LNKCTL2 configuration registers of PCIe core via PCIE_CAP_PCIEXP. So export them via emulated software root bridge. Pre-XP hardware does not support these registers and returns zeros. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridgePali Rohár1-1/+10
PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) is read-only and can be cleared only by writing 0b to the Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridgePali Rohár1-10/+1
Comment in Armada 370 functional specification is misleading. PCI_EXP_DEVCTL_*RE bits are supported and configures receiving of error interrupts. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridgePali Rohár1-0/+28
Hardware supports PCIe Hot Reset via PCIE_CTRL_OFF register. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this change the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridgePali Rohár1-2/+97
It looks like that mvebu PCIe controller has for each PCIe link fully independent PCIe host bridge and so every PCIe Root Port is isolated not only on its own bus but also isolated from each others. But in past device tree structure was defined to put all PCIe Root Ports (as PCI Bridge devices) into one root bus 0 and this bus is emulated by pci-mvebu.c driver. Probably reason for this decision was incorrect understanding of PCIe topology of these Armada SoCs and also reason of misunderstanding how is PCIe controller generating Type 0 and Type 1 config requests (it is fully different compared to other drivers). Probably incorrect setup leaded to very surprised things like having PCIe Root Port (PCI Bridge device, with even incorrect Device Class set to Memory Controller) and the PCIe device behind the Root Port on the same PCI bus, which obviously was needed to somehow hack (as these two devices cannot be in reality on the same bus). Properly set mvebu local bus number and mvebu local device number based on PCI Bridge secondary bus number configuration. Also correctly report configured secondary bus number in config space. And explain in driver comment why this setup is correct. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Set PCI Bridge Class Code to PCI BridgePali Rohár1-1/+27
The default value of Class Code of this bridge corresponds to a Memory controller, though. This is probably relict from the past when old Marvell/Galileo PCI-based controllers were used as standalone PCI device for connecting SDRAM or workaround for PCs with broken BIOS. Details are in commit 36de23a4c5f0 ("MIPS: Cobalt: Explain GT64111 early PCI fixup"). Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Setup PCIe controller to Root Complex modePali Rohár1-1/+7
This driver operates only in Root Complex mode, so ensure that hardware is properly configured in Root Complex mode. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE ↵Pali Rohár1-27/+55
registers Properly propagate failure from mvebu_pcie_add_windows() function back to the caller mvebu_pci_bridge_emul_base_conf_write() and correctly updates PCI_IO_BASE, PCI_MEM_BASE and PCI_IO_BASE_UPPER16 registers on error. On error set base value higher than limit value which indicates that address range is disabled. When IO is unsupported then let IO registers zeroed as required by PCIe base specification. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Do not modify PCI IO type bits in conf_writePali Rohár1-7/+0
PCI IO type bits are already initialized in mvebu_pci_bridge_emul_init() function and only when IO support is enabled. These type bits are read-only and pci-bridge-emul.c code already does not allow to modify them from upper layers. When IO support is disabled then all IO registers should be read-only and return zeros. Therefore do not modify PCI IO type bits in mvebu_pci_bridge_emul_base_conf_write() callback. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridgePali Rohár1-20/+32
According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early beginning of driver initialization. Also remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of PCI Bridge via emulated PCI_COMMAND on emulated bridge. Adjust existing functions mvebu_pcie_handle_iobase_change() and mvebu_pcie_handle_membase_change() to handle PCI_IO_BASE and PCI_MEM_BASE registers correctly even when bus mastering on emulated bridge is disabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Disallow mapping interrupts on emulated bridgesPali Rohár1-0/+10
Interrupt support on mvebu emulated bridges is not implemented yet. So properly indicate return value to callers that they cannot request interrupts from emulated bridge. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Handle invalid size of read config requestPali Rohár1-0/+3
Function mvebu_pcie_hw_rd_conf() does not handle invalid size. So correctly set read value to all-ones and return appropriate error return value PCIBIOS_BAD_REGISTER_NUMBER like in mvebu_pcie_hw_wr_conf() function. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-01-04PCI: mvebu: Check that PCI bridge specified in DT has function number zeroPali Rohár1-0/+5
Driver cannot handle PCI bridges at non-zero function address. So add appropriate check. Currently all in-tree kernel DTS files set PCI bridge function to zero. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
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