| Age | Commit message (Collapse) | Author | Files | Lines |
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- Make several tegra symbols const (Rikard Falkeborn)
- Fix tegra Kconfig host/endpoint typo (Wesley Sheng)
- Fix runtime PM imbalance (Dinghao Liu)
* remotes/lorenzo/pci/tegra:
PCI: tegra: Fix runtime PM imbalance in pex_ep_event_pex_rst_deassert()
PCI: tegra: Fix typo for PCIe endpoint mode in Tegra194
PCI: tegra: Constify static structs
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- sifive: Add pcie_aux clock to prci driver (Greentime Hu)
- sifive: Use reset-simple in prci driver for PCIe (Greentime Hu)
- Add SiFive FU740 PCIe host controller driver and DT binding (Paul
Walmsley, Greentime Hu)
* remotes/lorenzo/pci/risc-v:
riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
PCI: fu740: Add SiFive FU740 PCIe host controller driver
dt-bindings: PCI: Add SiFive FU740 PCIe host controller
MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
clk: sifive: Use reset-simple in prci driver for PCIe driver
clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
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- Make several microchip symbols static (Wei Yongjun)
- Drop redundant dev_err() for platform_get_irq() errors (Krzysztof
Wilczyński)
* remotes/lorenzo/pci/microchip:
PCI: microchip: Remove dev_err() when handing an error from platform_get_irq()
PCI: microchip: Make some symbols static
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- Configure FC and FTS for functions other than 0 (Ryder Lee)
- Add missing MODULE_DEVICE_TABLE (Qiheng Lin)
- Add YAML schema for MediaTek (Jianjun Wang)
- Export pci_pio_to_address() for module use (Jianjun Wang)
- Add MediaTek MT8192 PCIe controller driver (Jianjun Wang)
- Add MediaTek MT8192 INTx support (Jianjun Wang)
- Add MediaTek MT8192 MSI support (Jianjun Wang)
- Add MediaTek MT8192 system power management support (Jianjun Wang)
* remotes/lorenzo/pci/mediatek:
MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer
PCI: mediatek-gen3: Add system PM support
PCI: mediatek-gen3: Add MSI support
PCI: mediatek-gen3: Add INTx support
PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
PCI: Export pci_pio_to_address() for module use
dt-bindings: PCI: mediatek-gen3: Add YAML schema
PCI: mediatek: Add missing MODULE_DEVICE_TABLE
PCI: mediatek: Configure FC and FTS for functions other than 0
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- Fix ls_pcie_ep_probe() syntax error (comma for semicolon) (Krzysztof
Wilczyński)
* remotes/lorenzo/pci/layerscape:
PCI: layerscape: Correct syntax by changing comma to semicolon
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- Return zero for success of iproc_msi_irq_domain_alloc() (Pali Rohár)
* remotes/lorenzo/pci/iproc:
PCI: iproc: Fix return value of iproc_msi_irq_domain_alloc()
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- Use generic config accessors for TI AM65x (K3) to fix regression (Kishon
Vijay Abraham I)
- Move MSI Receiver init to dw_pcie_host_init() so it is re-initialized
along with the RC in resume (Jisheng Zhang)
- Remove unused pcie_app_rd() (Jiapeng Chong)
- Move iATU detection earlier to fix regression (Hou Zhiqiang)
* remotes/lorenzo/pci/dwc:
PCI: dwc: Move iATU detection earlier
PCI: dwc/intel-gw: Remove unused function
PCI: dwc: Move dw_pcie_msi_init() to dw_pcie_setup_rc()
PCI: keystone: Let AM65 use the pci_ops defined in pcie-designware-host.c
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- Add DT binding and TI j721e support for refclk to PCIe connector (Kishon
Vijay Abraham I)
- Add host mode and endpoint mode DT bindings for TI AM64 SoC (Kishon Vijay
Abraham I)
* remotes/lorenzo/pci/cadence:
PCI: j721e: Add support to provide refclk to PCIe connector
dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector
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- Fix brcm_pcie_probe() error return for unsupported revision (Wei Yongjun)
* remotes/lorenzo/pci/brcmstb:
PCI: brcmstb: Fix error return code in brcm_pcie_probe()
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- Remove redundant dev_err() for devm_ioremap_resource() failure (Chen Hui)
* remotes/lorenzo/pci/altera-msi:
PCI: altera-msi: Remove redundant dev_err call in altera_msi_probe()
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- Fix compile testing of al driver without CONFIG_PCI_ECAM (Arnd Bergmann)
- Fix compile testing of thunder drivers (Arnd Bergmann)
- Fix "no symbols" warnings when compile testing al, thunder driver with
CONFIG_TRIM_UNUSED_KSYMS (Arnd Bergmann)
- Remove unused MicroGate SyncLink device IDs (Jiri Slaby)
- Remove unused alloc_pci_root_info() return value (Krzysztof Wilczyński)
* pci/misc:
x86/PCI: Remove unused alloc_pci_root_info() return value
PCI: Remove MicroGate SyncLink device IDs
PCI: Avoid building empty drivers
PCI: thunder: Fix compile testing
PCI: al: Select CONFIG_PCI_ECAM
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Add driver for the SiFive FU740 PCIe host controller.
This controller is based on the DesignWare PCIe core.
Co-developed-by: Henry Styles <[email protected]>
Co-developed-by: Erik Danie <[email protected]>
Co-developed-by: Greentime Hu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Henry Styles <[email protected]>
Signed-off-by: Erik Danie <[email protected]>
Signed-off-by: Greentime Hu <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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The Broadcom STB PCIe RC uses a reset control "rescal" for certain chips.
The "rescal" implements a "pulse reset" so using assert/deassert is wrong
for this device. Instead, we use reset/rearm. We need to use rearm so
that we can reset it after a suspend/resume cycle; w/o using "rearm", the
"rescal" device will only ever fire once.
Of course for suspend/resume to work we also need to put the reset/rearm
calls in the suspend and resume routines.
Fixes: 740d6c3708a9 ("PCI: brcmstb: Add control of rescal reset")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
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Add suspend_noirq and resume_noirq callback functions to implement PM
system suspend and resume hooks for the MediaTek Gen3 PCIe controller.
When the system suspends, trigger the PCIe link to enter the L2 state
and pull down the PERST# pin, gating the clocks of the MAC layer, and
then power-off the physical layer to provide power-saving.
When the system resumes, the PCIe link should be re-established and the
related control register values should be restored.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jianjun Wang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Ryder Lee <[email protected]>
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Add MSI support for MediaTek Gen3 PCIe controller.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-----+
| GIC |
+-----+
^
|
port->irq
|
+-+-+-+-+-+-+-+-+
|0|1|2|3|4|5|6|7| (PCIe intc)
+-+-+-+-+-+-+-+-+
^ ^ ^
| | ... |
+-------+ +------+ +-----------+
| | |
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
|0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | | | (MSI vectors)
| | | | | | | | | | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jianjun Wang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Acked-by: Ryder Lee <[email protected]>
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Add INTx support for MediaTek Gen3 PCIe controller.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jianjun Wang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Acked-by: Ryder Lee <[email protected]>
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MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jianjun Wang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Ryder Lee <[email protected]>
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dw_pcie_ep_init() depends on the detected iATU region numbers to allocate
the in/outbound window management bitmap. It fails after 281f1f99cf3a
("PCI: dwc: Detect number of iATU windows").
Move the iATU region detection into a new function, move the detection to
the very beginning of dw_pcie_host_init() and dw_pcie_ep_init(). Also
remove it from the dw_pcie_setup(), since it's more like a software
initialization step than hardware setup.
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/linux-pci/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Tested-by: Kunihiko Hayashi <[email protected]>
Tested-by: Marek Szyprowski <[email protected]>
Tested-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
[DB: moved dw_pcie_iatu_detect to happen after host_init callback]
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Cc: [email protected] # v5.11+
Cc: Marek Szyprowski <[email protected]>
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Fix the following clang warning:
drivers/pci/controller/dwc/pcie-intel-gw.c:84:19: warning: unused
function 'pcie_app_rd' [-Wunused-function].
Link: https://lore.kernel.org/r/1618475577-99198-1-git-send-email-jiapeng.chong@linux.alibaba.com
Reported-by: Abaci Robot <[email protected]>
Signed-off-by: Jiapeng Chong <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
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If the host which makes use of IP's integrated MSI Receiver losts
power during suspend, we need to reinit the RC and MSI Receiver in
resume. But after we move dw_pcie_msi_init() into the core, we have no
API to do so. Usually the dwc users need to call dw_pcie_setup_rc() to
reinit the RC, we can solve this problem by moving dw_pcie_msi_init()
to dw_pcie_setup_rc().
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux
Pull CFI on arm64 support from Kees Cook:
"This builds on last cycle's LTO work, and allows the arm64 kernels to
be built with Clang's Control Flow Integrity feature. This feature has
happily lived in Android kernels for almost 3 years[1], so I'm excited
to have it ready for upstream.
The wide diffstat is mainly due to the treewide fixing of mismatched
list_sort prototypes. Other things in core kernel are to address
various CFI corner cases. The largest code portion is the CFI runtime
implementation itself (which will be shared by all architectures
implementing support for CFI). The arm64 pieces are Acked by arm64
maintainers rather than coming through the arm64 tree since carrying
this tree over there was going to be awkward.
CFI support for x86 is still under development, but is pretty close.
There are a handful of corner cases on x86 that need some improvements
to Clang and objtool, but otherwise works well.
Summary:
- Clean up list_sort prototypes (Sami Tolvanen)
- Introduce CONFIG_CFI_CLANG for arm64 (Sami Tolvanen)"
* tag 'cfi-v5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
arm64: allow CONFIG_CFI_CLANG to be selected
KVM: arm64: Disable CFI for nVHE
arm64: ftrace: use function_nocfi for ftrace_call
arm64: add __nocfi to __apply_alternatives
arm64: add __nocfi to functions that jump to a physical address
arm64: use function_nocfi with __pa_symbol
arm64: implement function_nocfi
psci: use function_nocfi for cpu_resume
lkdtm: use function_nocfi
treewide: Change list_sort to use const pointers
bpf: disable CFI in dispatcher functions
kallsyms: strip ThinLTO hashes from static functions
kthread: use WARN_ON_FUNCTION_MISMATCH
workqueue: use WARN_ON_FUNCTION_MISMATCH
module: ensure __cfi_check alignment
mm: add generic function_nocfi macro
cfi: add __cficanonical
add support for Clang CFI
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"Almost all SoC code changes this time are for the TI OMAP platform,
which continues its decade-long quest to move from describing a
complex SoC in code to device tree.
Aside from this, the Uniphier platform has a new maintainer and some
platforms have minor bugfixes and cleanups that were not urgent enough
for v5.12"
* tag 'arm-soc-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits)
MAINTAINERS: Update ARM/UniPhier SoCs maintainers and status
mailmap: Update email address for Nicolas Saenz
MAINTAINERS: Update BCM2711/BCM2335 maintainer's mail
ARM: exynos: correct kernel doc in platsmp
ARM: hisi: use the correct HiSilicon copyright
ARM: ux500: make ux500_cpu_die static
ARM: s3c: Use pwm_get() in favour of pwm_request() in RX1950
ARM: OMAP1: fix incorrect kernel-doc comment syntax in file
ARM: OMAP2+: fix incorrect kernel-doc comment syntax in file
ARM: OMAP2+: Use DEFINE_SPINLOCK() for spinlock
ARM: at91: pm: Move prototypes to mutually included header
ARM: OMAP2+: use true and false for bool variable
ARM: OMAP2+: add missing call to of_node_put()
ARM: OMAP2+: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
ARM: imx: Kconfig: Fix typo in help
ARM: mach-imx: Fix a spelling in the file pm-imx5.c
bus: ti-sysc: Warn about old dtb for dra7 and omap4/5
ARM: OMAP2+: Stop building legacy code for dra7 and omap4/5
ARM: OMAP2+: Drop legacy platform data for omap5 hwmod
ARM: OMAP2+: Drop legacy platform data for omap5 l3
...
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git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux
Pull Hyper-V updates from Wei Liu:
- VMBus enhancement
- Free page reporting support for Hyper-V balloon driver
- Some patches for running Linux as Arm64 Hyper-V guest
- A few misc clean-up patches
* tag 'hyperv-next-signed-20210426' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: (30 commits)
drivers: hv: Create a consistent pattern for checking Hyper-V hypercall status
x86/hyperv: Move hv_do_rep_hypercall to asm-generic
video: hyperv_fb: Add ratelimit on error message
Drivers: hv: vmbus: Increase wait time for VMbus unload
Drivers: hv: vmbus: Initialize unload_event statically
Drivers: hv: vmbus: Check for pending channel interrupts before taking a CPU offline
Drivers: hv: vmbus: Drivers: hv: vmbus: Introduce CHANNELMSG_MODIFYCHANNEL_RESPONSE
Drivers: hv: vmbus: Introduce and negotiate VMBus protocol version 5.3
Drivers: hv: vmbus: Use after free in __vmbus_open()
Drivers: hv: vmbus: remove unused function
Drivers: hv: vmbus: Remove unused linux/version.h header
x86/hyperv: remove unused linux/version.h header
x86/Hyper-V: Support for free page reporting
x86/hyperv: Fix unused variable 'hi' warning in hv_apic_read
x86/hyperv: Fix unused variable 'msr_val' warning in hv_qlock_wait
hv: hyperv.h: a few mundane typo fixes
drivers: hv: Fix EXPORT_SYMBOL and tab spaces issue
Drivers: hv: vmbus: Drop error message when 'No request id available'
asm-generic/hyperv: Add missing function prototypes per -W1 warnings
clocksource/drivers/hyper-v: Move handling of STIMER0 interrupts
...
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There is not a consistent pattern for checking Hyper-V hypercall status.
Existing code uses a number of variants. The variants work, but a consistent
pattern would improve the readability of the code, and be more conformant
to what the Hyper-V TLFS says about hypercall status.
Implemented new helper functions hv_result(), hv_result_success(), and
hv_repcomp(). Changed the places where hv_do_hypercall() and related variants
are used to use the helper functions.
Signed-off-by: Joseph Salisbury <[email protected]>
Reviewed-by: Michael Kelley <[email protected]>
Link: https://lore.kernel.org/r/1618620183-9967-2-git-send-email-joseph.salisbury@linux.microsoft.com
Signed-off-by: Wei Liu <[email protected]>
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Some Mediatek host bridges cannot handle MSIs, which is sad.
This also results in an ugly warning at device probe time,
as the core PCI code wasn't told that MSIs were not available.
Advertise this fact to the rest of the core PCI code by
using the 'msi_domain' attribute, which still opens the possibility
for another block to provide the MSI functionnality.
[maz: commit message, switched over to msi_domain attribute]
Link: https://lore.kernel.org/r/[email protected]
Reported-by: Frank Wunderlich <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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The generic PCI host driver relies on MSI domains for MSIs to
be provided to its end-points. Make this dependency explicit.
This cures the warnings occuring on arm/arm64 VMs when booted
with PCI virtio devices and no MSI controller (no GICv3 ITS,
for example).
It is likely that other drivers will need to express the same
dependency.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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The Hyper-V PCI driver still makes use of a msi_controller structure,
but it looks more like a distant leftover than anything actually
useful, since it is initialised to 0 and never used for anything.
Just remove it.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Michael Kelley <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Michael Kelley <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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In anticipation of the removal of the msi_controller structure, convert
the ancient xilinx host controller driver to MSI domains.
We end-up with the usual two domain structure, the top one being a
generic PCI/MSI domain, the bottom one being xilinx-specific and handling
the actual HW interrupt allocation.
This allows us to fix some of the most appaling MSI programming, where
the message programmed in the device is the virtual IRQ number instead
of the allocated vector number. The allocator is also made safe with
a mutex. This should allow support for MultiMSI, but I decided not to
even try, since I cannot test it.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Bharat Kumar Gogada <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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A long cargo-culted behaviour of PCI drivers is to allocate memory
to obtain an address that is fed to the controller as the MSI
capture address (i.e. the MSI doorbell).
But there is no actual requirement for this address to be RAM.
All it needs to be is a suitable aligned address that will
*not* be DMA'd to.
Use the physical address of the 'port' data structure as the MSI
capture address, aligned on a 4K boundary.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Bharat Kumar Gogada <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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In anticipation of the removal of the msi_controller structure, convert
the Rcar host controller driver to MSI domains.
We end-up with the usual two domain structure, the top one being a
generic PCI/MSI domain, the bottom one being Rcar-specific and handling
the actual HW interrupt allocation.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Vasut <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
[[email protected]: merged fix https://lore.kernel.org/linux-pci/[email protected]]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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A long cargo-culted behaviour of PCI drivers is to allocate memory
to obtain an address that is fed to the controller as the MSI
capture address (i.e. the MSI doorbell).
But there is no actual requirement for this address to be RAM.
All it needs to be is a suitable aligned address that will
*not* be DMA'd to.
Since the rcar platform already has a requirement that this
address should be in the first 4GB of the physical address space,
use the controller's own base address as the capture address.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
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In anticipation of the removal of the msi_controller structure, convert
the Tegra host controller driver to MSI domains.
We end-up with the usual two domain structure, the top one being a
generic PCI/MSI domain, the bottom one being Tegra-specific and handling
the actual HW interrupt allocation.
While at it, convert the normal interrupt handler to a chained handler,
handle the controller's MSI IRQ edge triggered, support multiple MSIs
per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking.
[[email protected]: fix, clean up and address TODOs from Marc's draft]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
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The PCIe controller in Tegra194 SoC is not ECAM-compliant. With the
current hardware design, ECAM can be enabled only for one controller (the
C5 controller) with bus numbers starting from 160 instead of 0. A different
approach is taken to avoid this abnormal way of enabling ECAM for just one
controller but to enable configuration space access for all the other
controllers. In this approach, ops are added through MCFG quirk mechanism
which access the configuration spaces by dynamically programming iATU
(internal AddressTranslation Unit) to generate respective configuration
accesses just like the way it is done in DesignWare core sub-system.
This issue is specific to Tegra194 and it would be fixed in the future
generations of Tegra SoCs.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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There is a error message within devm_ioremap_resource()
already, so remove the dev_err() call to avoid redundant
error message.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Chen Hui <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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This patch adds missing MODULE_DEVICE_TABLE definition which generates
correct modalias for automatic loading of this driver when it is built
as an external module.
Link: https://lore.kernel.org/r/[email protected]
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Qiheng Lin <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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list_sort() internally casts the comparison function passed to it
to a different type with constant struct list_head pointers, and
uses this pointer to call the functions, which trips indirect call
Control-Flow Integrity (CFI) checking.
Instead of removing the consts, this change defines the
list_cmp_func_t type and changes the comparison function types of
all list_sort() callers to use const pointers, thus avoiding type
mismatches.
Suggested-by: Nick Desaulniers <[email protected]>
Signed-off-by: Sami Tolvanen <[email protected]>
Reviewed-by: Nick Desaulniers <[email protected]>
Reviewed-by: Christoph Hellwig <[email protected]>
Reviewed-by: Kees Cook <[email protected]>
Tested-by: Nick Desaulniers <[email protected]>
Tested-by: Nathan Chancellor <[email protected]>
Signed-off-by: Kees Cook <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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pm_runtime_get_sync() will increase the runtime PM counter
even it returns an error. Thus a pairing decrement is needed
to prevent refcount leak. Fix this by replacing this API with
pm_runtime_resume_and_get(), which will not change the runtime
PM counter on error.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dinghao Liu <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Add support for routing PCIe DMA traffic coherently when
Cache Coherent Interconnect (CCI) is enabled in the system.
The "dma-coherent" property is used to determine if CCI is enabled
or not.
Refer to https://developer.arm.com/documentation/ddi0470/k/preface
for the CCI specification.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bharat Kumar Gogada <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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In commit e2dcd20b1645 a change was made to use
devm_platform_ioremap_resource_byname() to simplify code and remove
the res variable; this was wrong since the res variable is still needed
and as an outcome the port->cfg_addr gets an erroneous address.
Revert the change going back to original behaviour.
Link: https://lore.kernel.org/r/[email protected]
Fixes: e2dcd20b1645a ("PCI: controller: Convert to devm_platform_ioremap_resource_byname()")
Reported-by: [email protected]
Tested-by: dann frazier <[email protected]>
Signed-off-by: Dejin Zheng <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: [email protected] # v5.9+
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"PCI_FUNC(port->slot << 3)" is always 0, so previously
mtk_pcie_startup_port() only configured FC credits and FTs for function
0.
Compute "func" correctly so we also configure functions other than
0. This affects MT2701 and MT7623.
Link: https://lore.kernel.org/r/c529dbfc066f4bda9b87edbdbf771f207e69b84e.1604510053.git.ryder.lee@mediatek.com
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
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Add support to provide refclk to PCIe connector.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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- Drop the dependency on PCI, as this is implied by the dependency on
PCI_MSI_IRQ_DOMAIN,
- Drop the dependencies on OF and ARM64, as the driver compiles fine
without OF and/or on other architectures,
- The Freescale Layerscape PCIe Gen4 controller is present only on
Freescale Layerscape SoCs. Hence depend on ARCH_LAYERSCAPE, to
prevent asking the user about this driver when configuring a kernel
without Freescale Layerscape support, unless compile-testing.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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In config PCIE_TEGRA194_EP the mode incorrectly is referred to as
host mode. Fix it.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Wesley Sheng <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Acked-by: Vidya Sagar <[email protected]>
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Fix to return negative error code -ENODEV from the unsupported revision
error handling case instead of 0, as done elsewhere in this function.
Link: https://lore.kernel.org/r/[email protected]
Fixes: 0cdfaceb9889 ("PCI: brcmstb: support BCM4908 with external PERST# signal controller")
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Wei Yongjun <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
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Replace command with a semicolon to correct syntax and to prevent
potential unspecified behaviour and/or unintended side effects.
Related:
https://lore.kernel.org/linux-pci/[email protected]/
Co-authored-by: Zheng Yongjun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Roy Zang <[email protected]>
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Both TI's AM65x (K3) and TI's K2 PCIe driver are implemented in
pci-keystone. However Only K2 PCIe driver should use it's own pci_ops
for configuration space accesses. But commit 10a797c6e54a
("PCI: dwc: keystone: Use pci_ops for config space accessors") used
custom pci_ops for both AM65x and K2. This breaks configuration space
access for AM65x platform. Fix it here.
Link: https://lore.kernel.org/r/[email protected]
Fixes: 10a797c6e54a ("PCI: dwc: keystone: Use pci_ops for config space accessors")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Cc: <[email protected]> # v5.10
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There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.
This change is as per suggestions from Coccinelle, e.g.,
drivers/pci/controller/pcie-microchip-host.c:1027:2-9: line 1027 is
redundant because platform_get_irq() already prints an error
Related commit caecb05c8000 ("PCI: Remove dev_err() when handing an
error from platform_get_irq()").
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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The sparse tool complains as follows:
drivers/pci/controller/pcie-microchip-host.c:304:18: warning:
symbol 'pcie_event_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:310:18: warning:
symbol 'sec_error_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:317:18: warning:
symbol 'ded_error_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:324:18: warning:
symbol 'local_status_to_event' was not declared. Should it be static?
Those symbols are not used outside of pcie-microchip-host.c, so this
commit marks them static.
Link: https://lore.kernel.org/r/[email protected]
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Wei Yongjun <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
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IRQ domain alloc function should return zero on success. Non-zero value
indicates failure.
Link: https://lore.kernel.org/r/[email protected]
Fixes: fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs")
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Acked-by: Ray Jui <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
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VMD will retransmit child device MSI-X using its own MSI-X table and
requester-id. This limits the number of MSI-X available to the whole
child device domain to the number of VMD MSI-X interrupts.
Some VMD devices have a mode where this remapping can be disabled,
allowing child device interrupts to bypass processing with the VMD MSI-X
domain interrupt handler and going straight the child device interrupt
handler, allowing for better performance and scaling. The requester-id
still gets changed to the VMD endpoint's requester-id, and the interrupt
remapping handlers have been updated to properly set IRTE for child
device interrupts to the VMD endpoint's context.
Some VMD platforms have existing production BIOS which rely on MSI-X
remapping and won't explicitly program the MSI-X remapping bit. This
re-enables MSI-X remapping on unload.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jon Derrick <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Acked-by: Joerg Roedel <[email protected]>
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