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2021-03-22PCI: tegra: Constify static structsRikard Falkeborn1-2/+2
The only usage of them is to assign their address to the 'ops' field in the pcie_port and the dw_pcie_ep structs, both which are pointers to const. Make them const to allow the compiler to put them in read-only memory. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rikard Falkeborn <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2021-03-17PCI: hv: Use tasklet_disable_in_atomic()Sebastian Andrzej Siewior1-1/+1
The hv_compose_msi_msg() callback in irq_chip::irq_compose_msi_msg is invoked via irq_chip_compose_msi_msg(), which itself is always invoked from atomic contexts from the guts of the interrupt core code. There is no way to change this w/o rewriting the whole driver, so use tasklet_disable_in_atomic() which allows to make tasklet_disable() sleepable once the remaining atomic users are addressed. Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Wei Liu <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-03-11PCI: Fix kernel-doc errorsKrzysztof Wilczyński2-4/+9
Fix kernel-doc formatting errors, function names that don't match the doc, and some missing parameter documentation. These are reported by: make W=1 drivers/pci/ No functional change intended. [bhelgaas: squashed into one patch since this only changes comments] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-03-11PCI: Avoid building empty driversArnd Bergmann2-2/+12
There are harmless warnings when compile testing the kernel with CONFIG_TRIM_UNUSED_KSYMS: drivers/pci/controller/dwc/pcie-al.o: no symbols drivers/pci/controller/pci-thunder-ecam.o: no symbols drivers/pci/controller/pci-thunder-pem.o: no symbols The problem here is that the host drivers get built even when the configuration symbols are all disabled, as they pretend to not be drivers but are silently enabled because of the promise that ACPI-based systems need no drivers. Add back the normal symbols to have these drivers built, and change the logic to otherwise only build them when both CONFIG_PCI_QUIRKS and CONFIG_ACPI are enabled. As a side-effect, this enables compile-testing the drivers on other architectures, which in turn needs the acpi_get_rc_resources() function to be defined. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Robert Richter <[email protected]>
2021-03-11PCI: thunder: Fix compile testingArnd Bergmann2-7/+8
Compile-testing these drivers is currently broken. Enabling it causes a couple of build failures though: drivers/pci/controller/pci-thunder-ecam.c:119:30: error: shift count >= width of type [-Werror,-Wshift-count-overflow] drivers/pci/controller/pci-thunder-pem.c:54:2: error: implicit declaration of function 'writeq' [-Werror,-Wimplicit-function-declaration] drivers/pci/controller/pci-thunder-pem.c:392:8: error: implicit declaration of function 'acpi_get_rc_resources' [-Werror,-Wimplicit-function-declaration] Fix them with the obvious one-line changes. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Reviewed-by: Robert Richter <[email protected]>
2021-03-11PCI: al: Select CONFIG_PCI_ECAMArnd Bergmann1-0/+1
Compile-testing this driver without ECAM support results in a link failure: ld.lld: error: undefined symbol: pci_ecam_map_bus >>> referenced by pcie-al.c >>> pci/controller/dwc/pcie-al.o:(al_pcie_map_bus) in archive drivers/built-in.a Select CONFIG_ECAM like the other drivers do. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2021-03-10PCI: pci-dra7xx: Prepare for deferred probe with module_platform_driverTony Lindgren1-6/+7
After updating pci-dra7xx driver to probe with ti-sysc and genpd, I noticed that dra7xx_pcie_probe() would not run if a power-domains property was configured for the interconnect target module. Turns out that module_platform_driver_probe uses platform_driver_probe(), while builtin_platform_driver uses platform_driver_register(). Only platform_driver_register() works for deferred probe as noted in the comments for __platform_driver_probe() in drivers/base/platform.c with a line saying "Note that this is incompatible with deferred probing". With module_platform_driver_probe, we have platform_driver_probe() produce -ENODEV error at device_initcall() level, and no further attempts are done. Let's fix this by using module_platform_driver instead. Note this is not an issue currently as we probe devices with simple-bus, and only is needed as we start probing the device with ti-sysc, or when probed with simple-pm-bus. Note that we must now also remove __init for probe related functions to avoid a section mismatch warning. Cc: [email protected] Cc: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Tested-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-02-25Merge tag 'pci-v5.12-changes' of ↵Linus Torvalds26-488/+1450
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Remove unnecessary locking around _OSC (Bjorn Helgaas) - Clarify message about _OSC failure (Bjorn Helgaas) - Remove notification of PCIe bandwidth changes (Bjorn Helgaas) - Tidy checking of syscall user config accessors (Heiner Kallweit) Resource management: - Decline to resize resources if boot config must be preserved (Ard Biesheuvel) - Fix pci_register_io_range() memory leak (Geert Uytterhoeven) Error handling (Keith Busch): - Clear error status from the correct device - Retain error recovery status so drivers can use it after reset - Log the type of Port (Root or Switch Downstream) that we reset - Always request a reset for Downstream Ports in frozen state Endpoint framework and NTB (Kishon Vijay Abraham I): - Make *_get_first_free_bar() take into account 64 bit BAR - Add helper API to get the 'next' unreserved BAR - Make *_free_bar() return error codes on failure - Remove unused pci_epf_match_device() - Add support to associate secondary EPC with EPF - Add support in configfs to associate two EPCs with EPF - Add pci_epc_ops to map MSI IRQ - Add pci_epf_ops to expose function-specific attrs - Allow user to create sub-directory of 'EPF Device' directory - Implement ->msi_map_irq() ops for cadence - Configure LM_EP_FUNC_CFG based on epc->function_num_map for cadence - Add EP function driver to provide NTB functionality - Add support for EPF PCI Non-Transparent Bridge - Add specification for PCI NTB function device - Add PCI endpoint NTB function user guide - Add configfs binding documentation for pci-ntb endpoint function Broadcom STB PCIe controller driver: - Add support for BCM4908 and external PERST# signal controller (Rafał Miłecki) Cadence PCIe controller driver: - Retrain Link to work around Gen2 training defect (Nadeem Athani) - Fix merge botch in cdns_pcie_host_map_dma_ranges() (Krzysztof Wilczyński) Freescale Layerscape PCIe controller driver: - Add LX2160A rev2 EP mode support (Hou Zhiqiang) - Convert to builtin_platform_driver() (Michael Walle) MediaTek PCIe controller driver: - Fix OF node reference leak (Krzysztof Wilczyński) Microchip PolarFlare PCIe controller driver: - Add Microchip PolarFire PCIe controller driver (Daire McNamara) Qualcomm PCIe controller driver: - Use PHY_REFCLK_USE_PAD only for ipq8064 (Ansuel Smith) - Add support for ddrss_sf_tbu clock for sm8250 (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Drop PCIE_RCAR config option (Lad Prabhakar) - Always allocate MSI addresses in 32bit space (Marek Vasut) Rockchip PCIe controller driver: - Add FriendlyARM NanoPi M4B DT binding (Chen-Yu Tsai) - Make 'ep-gpios' DT property optional (Chen-Yu Tsai) Synopsys DesignWare PCIe controller driver: - Work around ECRC configuration hardware defect (Vidya Sagar) - Drop support for config space in DT 'ranges' (Rob Herring) - Change size to u64 for EP outbound iATU (Shradha Todi) - Add upper limit address for outbound iATU (Shradha Todi) - Make dw_pcie ops optional (Jisheng Zhang) - Remove unnecessary dw_pcie_ops from al driver (Jisheng Zhang) Xilinx Versal CPM PCIe controller driver: - Fix OF node reference leak (Pan Bian) Miscellaneous: - Remove tango host controller driver (Arnd Bergmann) - Remove IRQ handler & data together (altera-msi, brcmstb, dwc) (Martin Kaiser) - Fix xgene-msi race in installing chained IRQ handler (Martin Kaiser) - Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy (Junhao He) - Fix pci-bridge-emul array overruns (Russell King) - Remove obsolete uses of WARN_ON(in_interrupt()) (Sebastian Andrzej Siewior)" * tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (69 commits) PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064 PCI: qcom: Add support for ddrss_sf_tbu clock dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250 PCI: al: Remove useless dw_pcie_ops PCI: dwc: Don't assume the ops in dw_pcie always exist PCI: dwc: Add upper limit address for outbound iATU PCI: dwc: Change size to u64 for EP outbound iATU PCI: dwc: Drop support for config space in 'ranges' PCI: layerscape: Convert to builtin_platform_driver() PCI: layerscape: Add LX2160A rev2 EP mode support dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings PCI: dwc: Work around ECRC configuration issue PCI/portdrv: Report reset for frozen channel PCI/AER: Specify the type of Port that was reset PCI/ERR: Retain status from error notification PCI/AER: Clear AER status from Root Port when resetting Downstream Port PCI/ERR: Clear status of the reporting device dt-bindings: arm: rockchip: Add FriendlyARM NanoPi M4B PCI: rockchip: Make 'ep-gpios' DT property optional Documentation: PCI: Add PCI endpoint NTB function user guide ...
2021-02-24Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas7-31/+15
- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin Kaiser) - Fix xgene race in installing chained IRQ handler (Martin Kaiser) - Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar) - Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas) * remotes/lorenzo/pci/misc: PCI: hv: Fix typo PCI: xgene: Fix CRS SV comment PCI: brcmstb: Remove chained IRQ handler and data in one go PCI: Drop PCIE_RCAR config option PCI: xgene-msi: Fix race in installing chained irq handler PCI: dwc: Remove IRQ handler and data in one go PCI: altera-msi: Remove IRQ handler and data in one go
2021-02-24Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas1-0/+1
- Fix reference count leak on error path (Pan Bian) * remotes/lorenzo/pci/xilinx: PCI: xilinx-cpm: Fix reference count leak on error path
2021-02-24Merge branch 'remotes/lorenzo/pci/tango'Bjorn Helgaas3-356/+0
- Remove tango host controller driver (Arnd Bergmann) * remotes/lorenzo/pci/tango: PCI: Remove tango host controller driver # Conflicts: # drivers/pci/controller/Makefile
2021-02-24Merge branch 'pci/rockchip'Bjorn Helgaas1-6/+6
- Make 'ep-gpios' DT property optional (Chen-Yu Tsai) - Add FriendlyARM NanoPi M4B to rockchip DT binding (Chen-Yu Tsai) * pci/rockchip: dt-bindings: arm: rockchip: Add FriendlyARM NanoPi M4B PCI: rockchip: Make 'ep-gpios' DT property optional
2021-02-24Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas1-1/+1
- Always allocate rcar MSI addresses in 32-bit space so legacy devices without 64-bit MSI support can use MSI (Marek Vasut) * remotes/lorenzo/pci/rcar: PCI: rcar: Always allocate MSI addresses in 32bit space
2021-02-24Merge branch 'pci/qcom'Bjorn Helgaas1-6/+16
- Add support for SM8250 PCIe SF TBU clock (Dmitry Baryshkov) - Use PHY_REFCLK_USE_PAD only for qcom ipq8064 (Ansuel Smith) * pci/qcom: PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064 PCI: qcom: Add support for ddrss_sf_tbu clock dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250
2021-02-24Merge branch 'pci/ntb'Bjorn Helgaas1-6/+54
- Account for 64-bit BARs in pci_epc_get_first_free_bar() (Kishon Vijay Abraham I) - Add pci_epc_get_next_free_bar() helper (Kishon Vijay Abraham I) - Return error codes on failure of endpoint BAR interfaces (Kishon Vijay Abraham I) - Remove unused pci_epf_match_device() (Kishon Vijay Abraham I) - Add support for secondary endpoint controller to prepare for NTB endpoint functionality (Kishon Vijay Abraham I) - Add configfs support for secondary endpoint controller (Kishon Vijay Abraham I) - Add MSI address mapping ops for NTB doorbell support (Kishon Vijay Abraham I) - Add ops for endpoint function-specific attributes (Kishon Vijay Abraham I) - Allow configfs subdirectory for endpoint function configuration (Kishon Vijay Abraham I) - Implement cadence MSI address mapping ops (Kishon Vijay Abraham I) - Configure cadence LM_EP_FUNC_CFG based on epc->function_num_map (Kishon Vijay Abraham I) - Add endpoint-side driver to provide NTB functionality (Kishon Vijay Abraham I) - Add host-side driver for generic EPF NTB functionality (Kishon Vijay Abraham I) - Document NTB endpoint functionality (Kishon Vijay Abraham I) * pci/ntb: Documentation: PCI: Add PCI endpoint NTB function user guide Documentation: PCI: Add configfs binding documentation for pci-ntb endpoint function NTB: Add support for EPF PCI Non-Transparent Bridge PCI: Add TI J721E device to PCI IDs PCI: endpoint: Add EP function driver to provide NTB functionality PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_map PCI: cadence: Implement ->msi_map_irq() ops PCI: endpoint: Allow user to create sub-directory of 'EPF Device' directory PCI: endpoint: Add pci_epf_ops to expose function-specific attrs PCI: endpoint: Add pci_epc_ops to map MSI IRQ PCI: endpoint: Add support in configfs to associate two EPCs with EPF PCI: endpoint: Add support to associate secondary EPC with EPF PCI: endpoint: Remove unused pci_epf_match_device() PCI: endpoint: Make *_free_bar() to return error codes on failure PCI: endpoint: Add helper API to get the 'next' unreserved BAR PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR Documentation: PCI: Add specification for the PCI NTB function device
2021-02-24Merge branch 'pci/microchip'Bjorn Helgaas4-2/+1151
- Call platform_set_drvdata() earlier so drivers can do window setup in init functions instead of custom probe (Daire McNamara) - Add DT binding and host mode driver for Microchip PolarFire PCIe controller (Daire McNamara) * pci/microchip: MAINTAINERS: Add Daire McNamara as Microchip PCIe driver maintainer PCI: microchip: Add Microchip PolarFire PCIe controller driver dt-bindings: PCI: microchip: Add Microchip PolarFire host binding PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridge
2021-02-24Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas1-2/+5
- Fix of_node_put() reference leak (Krzysztof Wilczyński) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Add missing of_node_put() to fix reference leak
2021-02-24Merge branch 'pci/layerscape'Bjorn Helgaas2-2/+10
- Add Layerscape LX2160A rev2 endpoint mode support (Hou Zhiqiang) - Convert layerscape to builtin_platform_driver() (Michael Walle) * pci/layerscape: PCI: layerscape: Convert to builtin_platform_driver() PCI: layerscape: Add LX2160A rev2 EP mode support dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings
2021-02-24Merge branch 'pci/dwc'Bjorn Helgaas5-54/+79
- Always set DesignWare "TLP Digest" bit so generic code can enable ECRC via the AER Capability (Vidya Sagar) - Drop support for config space in DT 'ranges' (Rob Herring) - Increase width of outbound iATU size to u64 (Shradha Todi) - Add upper limit address for outbound iATU (Shradha Todi) - Allow dwc-based drivers that don't override any default ops (Jisheng Zhang) - Drop unnecessary dw_pcie_ops from the al driver (Jisheng Zhang) * pci/dwc: PCI: al: Remove useless dw_pcie_ops PCI: dwc: Don't assume the ops in dw_pcie always exist PCI: dwc: Add upper limit address for outbound iATU PCI: dwc: Change size to u64 for EP outbound iATU PCI: dwc: Drop support for config space in 'ranges' PCI: dwc: Work around ECRC configuration issue
2021-02-24Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas3-19/+76
- Retrain Link to work around Gen2 training defect (Nadeem Athani) * remotes/lorenzo/pci/cadence: PCI: cadence: Retrain Link to work around Gen2 training defect
2021-02-24Merge branch 'remotes/lorenzo/pci/brcmstb'Bjorn Helgaas2-1/+33
- Add support for BCM4908 with external PERST# signal controller (Rafał Miłecki) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: support BCM4908 with external PERST# signal controller dt-bindings: PCI: brcmstb: add BCM4908 binding
2021-02-24PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064Ansuel Smith1-1/+3
The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064 devices. It was tested that while apq doesn't require the padding, ipq SoC must use it or the kernel hangs on boot. Link: https://lore.kernel.org/r/[email protected] Fixes: de3c4bf64897 ("PCI: qcom: Add support for tx term offset for rev 2.1.0") Reported-by: Ilia Mirkin <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.19+
2021-02-24PCI: qcom: Add support for ddrss_sf_tbu clockDmitry Baryshkov1-5/+13
On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Link: https://lore.kernel.org/r/[email protected] Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2021-02-24PCI: al: Remove useless dw_pcie_opsJisheng Zhang1-4/+0
We have removed the assumption that dw_pcie_ops always exists in the dwc core driver, so we can remove the useless dw_pcie_ops now. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jonathan Chocron <[email protected]>
2021-02-24PCI: dwc: Don't assume the ops in dw_pcie always existJisheng Zhang3-13/+11
Some dwc-based device drivers, especially host-only drivers, may work well with the default read_dbi/write_dbi/link_up implementations in pcie-designware.c, so remove the assumption that every driver implements them to simplify those drivers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-24PCI: dwc: Add upper limit address for outbound iATUShradha Todi2-0/+6
The size parameter is unsigned long type which can accept size > 4GB. In that case, the upper limit address must be programmed. Add support to program the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Shradha Todi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2021-02-24PCI: dwc: Change size to u64 for EP outbound iATUShradha Todi2-2/+2
Since outbound iATU permits size to be greater than 4GB for which the support is also available, allow EP function to send u64 size instead of truncating to u32. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Shradha Todi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]>
2021-02-24PCI: dwc: Drop support for config space in 'ranges'Rob Herring1-33/+12
Since commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code"), the code setting dbi_base when the config space is defined in 'ranges' property instead of 'reg' is dead code as dbi_base is never NULL. Rather than fix this, let's just drop the code. Using ranges has been deprecated since 2014. The only platforms using this were exynos5440, i.MX6 and Spear13xx. Exynos5440 is dead and has been removed. i.MX6 and Spear13xx had PCIe support added just before this was deprecated and were fixed within a kernel release or 2. Link: https://lore.kernel.org/r/[email protected] Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-24PCI: layerscape: Convert to builtin_platform_driver()Michael Walle1-2/+3
fw_devlink will defer the probe until all suppliers are ready. We can't use builtin_platform_driver_probe() because it doesn't retry after probe deferral. Convert it to builtin_platform_driver(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang1-0/+7
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-24PCI: dwc: Work around ECRC configuration issueVidya Sagar2-2/+48
DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed for proper ECRC functionality. This is currently identified as an issue with DesignWare IP version 4.90a. [bhelgaas: fix typos/grammar errors] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Bjorn Helgaas <[email protected]>
2021-02-23PCI: rockchip: Make 'ep-gpios' DT property optionalChen-Yu Tsai1-6/+6
The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is an optional property. And indeed there are boards that don't require it. Make the driver follow the binding by using devm_gpiod_get_optional() instead of devm_gpiod_get(). [bhelgaas: tidy whitespace] Link: https://lore.kernel.org/r/[email protected] Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Fixes: 964bac9455be ("PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT") Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-23PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_mapKishon Vijay Abraham I1-6/+1
The number of functions supported by the endpoint controller is configured in LM_EP_FUNC_CFG based on func_no member of struct pci_epf. Now that an endpoint function can be associated with two endpoint controllers (primary and secondary), just using func_no will not suffice as that will take into account only if the endpoint controller is associated with the primary interface of endpoint function. Instead use epc->function_num_map which will already have the configured functions information (irrespective of whether the endpoint controller is associated with primary or secondary interface). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Tom Joseph <[email protected]>
2021-02-23PCI: cadence: Implement ->msi_map_irq() opsKishon Vijay Abraham I1-0/+53
Implement ->msi_map_irq() ops in order to map physical address to MSI address and return MSI data. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Tom Joseph <[email protected]>
2021-02-23PCI: microchip: Add Microchip PolarFire PCIe controller driverDaire McNamara3-0/+1149
Add support for the Microchip PolarFire PCIe controller when configured in host (Root Complex) mode. [bhelgaas: wrap lines to fit in 80 columns, fix trivial style issues] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daire McNamara <[email protected]> [[email protected]: minor comments tweak] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2021-02-23PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridgeDaire McNamara1-2/+2
Many drivers can now use pci_host_common_probe() directly. Their hardware window setup can be moved from their 'custom' probe functions to individual driver init functions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daire McNamara <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2021-02-18PCI: cadence: Fix DMA range mapping early return errorKrzysztof Wilczyński1-2/+3
Function cdns_pcie_host_map_dma_ranges() iterates over a PCIe host bridge DMA ranges using the resource_list_for_each_entry() iterator, returning an error if cdns_pcie_host_bar_config() fails. 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") botched a merge so it *always* returned after the first DMA range, even if no error occurred. Fix the error checking so we return early only when an error occurs. [bhelgaas: commit log] Fixes: 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-02-11asm-generic/hyperv: update hv_interrupt_entryWei Liu1-1/+1
We will soon use the same structure to handle IO-APIC interrupts as well. Introduce an enum to identify the source and a data structure for IO-APIC RTE. While at it, update pci-hyperv.c to use the enum. No functional change. Signed-off-by: Wei Liu <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Michael Kelley <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-02-10PCI: cadence: Retrain Link to work around Gen2 training defectNadeem Athani3-19/+76
Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nadeem Athani <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-28PCI: hv: Fix typoBjorn Helgaas1-1/+1
Fix misspelling of "silently". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Michael Kelley <[email protected]>
2021-01-28PCI: xgene: Fix CRS SV commentBjorn Helgaas1-6/+7
Configuration Request Retry Status ("CRS") must be supported by all PCIe devices. CRS Software Visibility is an optional feature that enables a Root Port to make CRS visible to software by returning a special data value to complete a config read. Clarify a comment to say that it is "CRS SV", not "CRS", that can be enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-25PCI: mediatek: Add missing of_node_put() to fix reference leakKrzysztof Wilczyński1-2/+5
The for_each_available_child_of_node helper internally makes use of the of_get_next_available_child() which performs an of_node_get() on each iteration when searching for next available child node. Should an available child node be found, then it would return a device node pointer with reference count incremented, thus early return from the middle of the loop requires an explicit of_node_put() to prevent reference count leak. To stop the reference leak, explicitly call of_node_put() before returning after an error occurred. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-25PCI: xilinx-cpm: Fix reference count leak on error pathPan Bian1-0/+1
Also drop the reference count of the node on error path. Link: https://lore.kernel.org/r/[email protected] Fixes: 508f610648b9 ("PCI: xilinx-cpm: Add Versal CPM Root Port driver") Signed-off-by: Pan Bian <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-22PCI: Remove tango host controller driverArnd Bergmann3-356/+0
The tango platform is getting removed, so the driver is no longer needed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Mans Rullgard <[email protected]> Cc: Marc Gonzalez <[email protected]> Cc: Mans Rullgard <[email protected]>
2021-01-19PCI: brcmstb: Remove chained IRQ handler and data in one goMartin Kaiser1-2/+1
Call irq_set_chained_handler_and_data() to clear the chained handler and the handler's data under irq_desc->lock. See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ handler"). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin Kaiser <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]> Acked-by: Nicolas Saenz Julienne <[email protected]>
2021-01-19PCI: Drop PCIE_RCAR config optionLad Prabhakar1-9/+0
All the defconfig files have replaced PCIE_RCAR config option with PCIE_RCAR_HOST config option which built the same driver, so we can now safely drop PCIE_RCAR config option. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]>
2021-01-19PCI: brcmstb: support BCM4908 with external PERST# signal controllerRafał Miłecki2-1/+33
BCM4908 uses external MISC block for controlling PERST# signal. Use it as a reset controller. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2021-01-18PCI: xgene-msi: Fix race in installing chained irq handlerMartin Kaiser1-7/+3
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ handler"). Based on the mail discussion, it seems ok to drop the error handling. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin Kaiser <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-18PCI: dwc: Remove IRQ handler and data in one goMartin Kaiser1-4/+2
Call irq_set_chained_handler_and_data() to clear the chained handler and the handler's data under irq_desc->lock. See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ handler"). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin Kaiser <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-01-18PCI: altera-msi: Remove IRQ handler and data in one goMartin Kaiser1-2/+1
Call irq_set_chained_handler_and_data() to clear the chained handler and the handler's data under irq_desc->lock. See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ handler"). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin Kaiser <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
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