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path: root/drivers/pci/controller
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2019-09-04PCI: rockchip: Propagate errors for optional regulatorsThierry Reding1-8/+8
regulator_get_optional() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate data structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "regulator not specified in DT". What we really want is to ignore the optional regulators only if they have not been specified in DT. regulator_get_optional() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Acked-by: Shawn Lin <[email protected]> Cc: Shawn Lin <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: [email protected]
2019-08-30PCI: Remove unnecessary returnsKrzysztof Wilczynski1-2/+0
Remove unnecessary "return" statements at the end of void functions. No functional change intended. Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczynski <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2019-08-22PCI: dwc: Return directly when num-lanes is not foundHou Zhiqiang1-2/+4
The num-lanes is optional since it is not needed on some platforms that bring up the link in firmware. The link programming is based on the num-lanes properties (which is optional); if it is not present code must return instead of fiddling with the lanes value to print an error message. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2019-08-22PCI: hv: Add a Hyper-V PCI interface driver for software backchannel interfaceHaiyang Zhang4-3/+84
This interface driver is a helper driver allows other drivers to have a common interface with the Hyper-V PCI frontend driver. Signed-off-by: Haiyang Zhang <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-08-22PCI: hv: Add a paravirtual backchannel in softwareDexuan Cui1-0/+302
Windows SR-IOV provides a backchannel mechanism in software for communication between a VF driver and a PF driver. These "configuration blocks" are similar in concept to PCI configuration space, but instead of doing reads and writes in 32-bit chunks through a very slow path, packets of up to 128 bytes can be sent or received asynchronously. Nearly every SR-IOV device contains just such a communications channel in hardware, so using this one in software is usually optional. Using the software channel, however, allows driver implementers to leverage software tools that fuzz the communications channel looking for vulnerabilities. The usage model for these packets puts the responsibility for reading or writing on the VF driver. The VF driver sends a read or a write packet, indicating which "block" is being referred to by number. If the PF driver wishes to initiate communication, it can "invalidate" one or more of the first 64 blocks. This invalidation is delivered via a callback supplied by the VF driver by this driver. No protocol is implied, except that supplied by the PF and VF drivers. Signed-off-by: Jake Oshins <[email protected]> Signed-off-by: Dexuan Cui <[email protected]> Cc: Haiyang Zhang <[email protected]> Cc: K. Y. Srinivasan <[email protected]> Cc: Stephen Hemminger <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: Haiyang Zhang <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-08-21PCI: mobiveil: Fix the CPU base address setup in inbound windowHou Zhiqiang1-3/+7
Current code erroneously sets-up the CPU base address through the parameter 'pci_addr', which is passed to initialize the CPU (AXI) base address of the inbound window where the controller maps the PCI address space into CPU physical address space; furthermore, it also truncates it by programming only the lower 32-bit value into the inbound CPU address register. Fix both issues by introducing a new parameter 'u64 cpu_addr' to initialize both lower 32-bit and upper 32-bit of the CPU physical base address mapping PCI inbound transactions into CPU (AXI) ones. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-08-21PCI: kirin: Make structure kirin_dw_pcie_ops constantNishka Dasgupta1-1/+1
Static variable kirin_dw_pcie_ops, of type dw_pcie_ops, is used only once, when it is assigned to the constant field ops of variable pci (having type dw_pcie) so kirin_dw_pcie_ops is never modified. Make it constant to protect it from unintended modification. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2019-08-21PCI: hv: Detect and fix Hyper-V PCI domain number collisionHaiyang Zhang1-13/+79
Currently in Azure cloud, for passthrough devices, the host sets the device instance ID's bytes 8 - 15 to a value derived from the host HWID, which is the same on all devices in a VM. So, the device instance ID's bytes 8 and 9 provided by the host are no longer unique. This affects all Azure hosts since July 2018, and can cause device passthrough to VMs to fail because the bytes 8 and 9 are used as PCI domain number. Collision of domain numbers will cause the second device with the same domain number fail to load. In the cases of collision, we will detect and find another number that is not in use. Suggested-by: Michael Kelley <[email protected]> Signed-off-by: Haiyang Zhang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Sasha Levin <[email protected]>
2019-08-15PCI: imx6: Limit DBI register lengthStefan Agner1-0/+33
Define the length of the DBI registers and limit config space to its length. This makes sure that the kernel does not access registers beyond that point, avoiding the following abort on a i.MX 6Quad: # cat /sys/devices/soc0/soc/1ffc000.pcie/pci0000\:00/0000\:00\:00.0/config [ 100.021433] Unhandled fault: imprecise external abort (0x1406) at 0xb6ea7000 ... [ 100.056423] PC is at dw_pcie_read+0x50/0x84 [ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48 ... Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
2019-08-14PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separatelyXiaowei Bao2-3/+20
Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller drivers can be built separately. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-08-14PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driverXiaowei Bao1-0/+1
The layerscape PCIe controller have 4 BARs. BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a fixed hardware configuration. Set the bar_fixed_64bit variable accordingly. Signed-off-by: Xiaowei Bao <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2019-08-13PCI: dwc: Add support to enable CDM register checkVidya Sagar2-0/+16
Add support to enable CDM (Configuration Dependent Module) register check for any data corruption based on the DT property 'snps,enable-cdm-check'. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2019-08-13PCI: dwc: Export dw_pcie_wait_for_link() APIVidya Sagar1-0/+1
Export the dw_pcie_wait_for_link() function to be able to build drivers using it as loadable modules. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-08-13PCI: dwc: Add extended configuration space capability search APIVidya Sagar2-0/+42
Add extended configuration space capability search API using struct dw_pcie* pointer. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Acked-by: Thierry Reding <[email protected]>
2019-08-13PCI: dwc: Move config space capability search APIVidya Sagar3-35/+43
Move PCIe config space capability search API to common DesignWare file as this can be used by both host and EP mode drivers. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2019-08-13PCI: dwc: Group DBI registers writes requiring unlockingVidya Sagar1-6/+8
Some of DesignWare core's DBI registers (a.k.a configuration space registers) are write-protected with a lock without enabling which they are read-only by default. These write-protected registers are implementation specific. Tegra194's BAR-0 register which is at offset 0x10 in the configuration space is an example. Current implementation in dw_pcie_setup_rc() API attempts to unlock those write-protected registers whenever they are updated and lock them back again for writing. Group all write-protected registers writes so that locking and unlocking is performed once to avoid bloating the code with multiple unlock/lock sequences for all those write-protected registers. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Jingoo Han <[email protected]>
2019-08-12PCI: hv: Avoid use of hv_pci_dev->pci_slot after freeing itDexuan Cui1-1/+1
The slot must be removed before the pci_dev is removed, otherwise a panic can happen due to use-after-free. Fixes: 15becc2b56c6 ("PCI: hv: Add hv_pci_remove_slots() when we unload the driver") Signed-off-by: Dexuan Cui <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2019-08-12PCI: tegra: Fix OF node reference leakNishka Dasgupta1-7/+15
Each iteration of for_each_child_of_node() executes of_node_put() on the previous node, but in some return paths in the middle of the loop of_node_put() is missing thus causing a reference leak. Hence stash these mid-loop return values in a variable 'err' and add a new label err_node_put which executes of_node_put() on the previous node and returns 'err' on failure. Change mid-loop return statements to point to jump to this label to fix the reference leak. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <[email protected]> [[email protected]: rewrote commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-08-07PCI: hv: Allocate a named fwnode instead of an address-based oneMarc Zyngier1-1/+9
To allocate its fwnode that is then used to allocate an irqdomain, the driver uses irq_domain_alloc_fwnode(), passing it a VA as an identifier. This is a rather bad idea, as this address ends up published in debugfs (and we want to move away from VAs there anyway). Instead, let's allocate a named fwnode by using the device GUID as an identifier. It is allegedly unique, and can be traced back to the original device. Acked-by: Thomas Gleixner <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
2019-08-07PCI: mediatek: Add controller support for MT7629Jianjun Wang1-0/+18
MT7629 is an ARM platform SoC which has the same PCIe IP as MT7622. The HW default value of its PCI host controller Device ID is invalid, fix it to match the hardware implementation. Signed-off-by: Jianjun Wang <[email protected]> [[email protected]: commit log/minor spelling update] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Ryder Lee <[email protected]>
2019-07-24PCI: Use devm_add_action_or_reset()Fuqian Huang1-2/+1
devm_add_action_or_reset() is a helper function which internally calls devm_add_action(). If the devm_add_action() fails, it will execute the action mentioned and return the error code. Use devm_add_action_or_reset() to reduce source code size (avoid writing the action twice) and reduce the likelihood of bugs. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Fuqian Huang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2019-07-12Merge branch 'pci/trivial'Bjorn Helgaas6-6/+6
- Fix typos and whitespace errors (Bjorn Helgaas) * pci/trivial: PCI: Fix typos and whitespace errors
2019-07-12Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas1-6/+5
- Fix Xilinx NWL multi-MSI vector aliasing issue (Bharat Kumar Gogada) * remotes/lorenzo/pci/xilinx: PCI: xilinx-nwl: Fix Multi MSI data programming
2019-07-12Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-82/+507
- Reorganize Tegra AFI/PHY/REFCLK/etc functions (Manikanta Maddireddy) - Mask Tegra AFI_INTR in runtime suspend (Manikanta Maddireddy) - Fix Tegra AFI/PCIe powerup sequence (Manikanta Maddireddy) - Add Tegra124, Tegra132, Tegra210, and Tegra186 support for Gen2 link speed (Manikanta Maddireddy) - Advertise Tegra AER support (Manikanta Maddireddy) - Program Tegra210 UPHY settings (Manikanta Maddireddy) - Enable Tegra opportunistic UpdateFC and ACK (Manikanta Maddireddy) - Disable Tegra AFI dynamic clock gating (Manikanta Maddireddy) - Process Tegra pending DLL transactions before entering L1 or L2 to prevent receiver errors (Manikanta Maddireddy) - Enable Tegra xclk clock clamping in L1 (Manikanta Maddireddy) - Increase Tegra deskew retry time (Manikanta Maddireddy) - Work around Tegra hardware RAW erratum (Manikanta Maddireddy) - Update Tegra210 flow control timer frequency (Manikanta Maddireddy) - Work around Tegra Gen1/Gen2 link number negotiation issue (Manikanta Maddireddy) - Work around Tegra PLLE power down issue (Manikanta Maddireddy) - Program Tegra20 to support cacheable upstream transactions (Manikanta Maddireddy) - Log Tegra PRSNT_SENSE_IRQ as debug, not err (Manikanta Maddireddy) - Add register offset for third Root Port on Tegra186 and Tegra30 (Manikanta Maddireddy) - Document Tegra PCIe DPD pinctrl property (Manikanta Maddireddy) - Put Tegra PEX CLK & BIAS pads in DPD mode to reduce power usage when powergated (Manikanta Maddireddy) - Add generic DT binding for "reset-gpios" property (Manikanta Maddireddy) - Add Tegra support for GPIO-based PERST# (Manikanta Maddireddy) - Enable Relaxed Ordering only for Tegra20 & Tegra30 (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30 PCI: tegra: Change link retry log level to debug PCI: tegra: Add support for GPIO based PERST# PCI: Add DT binding for "reset-gpios" property PCI: tegra: Put PEX CLK & BIAS pads in DPD mode dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct PCI: tegra: Change PRSNT_SENSE IRQ log to debug PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20 PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal PCI: tegra: Set target speed as Gen1 before starting LTSSM PCI: tegra: Update flow control timer frequency in Tegra210 PCI: tegra: Add SW fixup for RAW violations PCI: tegra: Increase the deskew retry time PCI: tegra: Enable PCIe xclk clock clamping PCI: tegra: Process pending DLL transactions before entering L1 or L2 PCI: tegra: Disable AFI dynamic clock gating PCI: tegra: Enable opportunistic UpdateFC and ACK PCI: tegra: Program UPHY electrical settings for Tegra210 PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability PCI: tegra: Add PCIe Gen2 link speed support PCI: tegra: Fix PCIe host power up sequence PCI: tegra: Mask AFI_INTR in runtime suspend PCI: tegra: Rearrange Tegra PCIe driver functions PCI: tegra: Handle failure cases in tegra_pcie_power_on() soc/tegra: pmc: Export tegra_powergate_power_on()
2019-07-12Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-61/+54
- Move qcom driver to bulk clock API (Bjorn Andersson) - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson) - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel) * remotes/lorenzo/pci/qcom: PCI: qcom: Ensure that PERST is asserted for at least 100 ms PCI: qcom: Add QCS404 PCIe controller support dt-bindings: PCI: qcom: Add QCS404 to the binding PCI: qcom: Use clk bulk API for 2.4.0 controllers
2019-07-12Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas1-213/+312
- Unify mobiveil register accessors (Hou Zhiqiang) - Remove MSI_FLAG_MULTI_PCI_MSI since mobiveil hardware doesn't support Multiple MSI (Hou Zhiqiang) - Program outbound windows with base address from DT instead of assuming zero (Hou Zhiqiang) - Skip "safe" list traversal when it's unnecessary (Hou Zhiqiang) - Initialize WIN_NUM_0 explicitly for CFG outbound transactions (Hou Zhiqiang) - Use WIN_NUM_0 for MEM inbound transactions (Hou Zhiqiang) - Fix up mobiveil Class Code to PCI_CLASS_BRIDGE_PCI (Hou Zhiqiang) - Wait for link-up before enumerating devices, not while initializing host (Hou Zhiqiang) - Move IRQ chained handler setup out of DT code (Hou Zhiqiang) - Set primary/secondary/subordinate bus numbers (Hou Zhiqiang) - Fix "valid device" check to allow root bus device 0 to be multi-function (Hou Zhiqiang) - Make DT "gpio_slave" and "apb_csr" properties optional (Hou Zhiqiang) - Refactor MEM/IO outbound window initialization (Hou Zhiqiang) - Fix validity check for inbound/outbound window programming (Hou Zhiqiang) - Initialize and preserve window control bits (Hou Zhiqiang) - Fix 64-bit outbound window setup (both CPU and PCI addresses) (Hou Zhiqiang) - Move IO port setup to host init (Hou Zhiqiang) - Fix infinite loop in INTx ISR (Hou Zhiqiang) - Fix INTx interrupt clearing to avoid missed interrupts (Hou Zhiqiang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr() PCI: mobiveil: Fix infinite-loop in the INTx handling function PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup PCI: mobiveil: Clear the control fields before updating it PCI: mobiveil: Add configured inbound windows counter PCI: mobiveil: Fix the valid check for inbound and outbound windows PCI: mobiveil: Clean-up program_{ib/ob}_windows() PCI: mobiveil: Remove an unnecessary return value check PCI: mobiveil: Fix error return values PCI: mobiveil: Refactor the MEM/IO outbound window initialization PCI: mobiveil: Make some register updates more readable PCI: mobiveil: Reformat the code for readability dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device() PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers PCI: mobiveil: Move IRQ chained handler setup out of DT parse PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() PCI: mobiveil: Fix the Class Code field PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window PCI: mobiveil: Update the resource list traversal function PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI PCI: mobiveil: Unify register accessors
2019-07-12Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas1-6/+9
- Fix Hyper-V use-after-free in eject path (Dexuan Cui) * remotes/lorenzo/pci/hv: PCI: hv: Fix a use-after-free bug in hv_eject_device_work()
2019-07-12Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas5-35/+80
- Add dwc API support to de-initialize host (Vidya Sagar) - Clean up dwc DBI,ATU read and write APIs (Vidya Sagar) - Export dwc APIs to support .remove() so drivers can be modular (Vidya Sagar) - Simplify imx6 Kconfig dependencies (Leonard Crestez) - Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing) * remotes/lorenzo/pci/dwc: PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: imx6: Simplify Kconfig depends on PCI: dwc: Export APIs to support .remove() implementation PCI: dwc: Cleanup DBI,ATU read and write APIs PCI: dwc: Add API support to de-initialize host
2019-07-12Merge branch 'remotes/lorenzo/pci/armada'Bjorn Helgaas1-1/+81
- Add Armada8k PHYs support (Miquel Raynal) * remotes/lorenzo/pci/armada: PCI: armada8k: Add PHYs support
2019-07-09PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIBYueHaibing1-0/+1
If CONFIG_GPIOLIB is not selected the compilation results in the following build errors: drivers/pci/controller/dwc/pci-dra7xx.c: In function dra7xx_pcie_probe: drivers/pci/controller/dwc/pci-dra7xx.c:777:10: error: implicit declaration of function devm_gpiod_get_optional; did you mean devm_regulator_get_optional? [-Werror=implicit-function-declaration] reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); drivers/pci/controller/dwc/pci-dra7xx.c:778:45: error: ‘GPIOD_OUT_HIGH’ undeclared (first use in this function); did you mean ‘GPIOF_INIT_HIGH’? reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); ^~~~~~~~~~~~~~ GPIOF_INIT_HIGH Fix them by including the appropriate header file. Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2019-07-09PCI: Fix typos and whitespace errorsBjorn Helgaas6-6/+6
Fix typos in drivers/pci. Comment and whitespace changes only. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rafael J. Wysocki <[email protected]> Reviewed-by: Randy Dunlap <[email protected]>
2019-07-08PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr()Hou Zhiqiang1-3/+2
The current INTx handling function clears all interrupts after handling the first pending; this can potentially cause missing INTx detection. Fix the code to clear only the handled INTx IRQ. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]> Acked-by: Karthikeyan Mitran <[email protected]> Tested-by: Karthikeyan Mitran <[email protected]>
2019-07-08PCI: mobiveil: Fix infinite-loop in the INTx handling functionHou Zhiqiang1-3/+9
In the loop handling INTx interrupts in mobiveil_pcie_isr(), there is no code to update the loop control variable, which is causing an infinite loop. Fix the code by reading the interrupt status registers inside the loop. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]> Acked-by: Karthikeyan Mitran <[email protected]> Tested-by: Karthikeyan Mitran <[email protected]>
2019-07-08PCI: mobiveil: Move PCIe PIO enablement out of inbound window routineHou Zhiqiang1-4/+5
Move the PCIe PIO master enablement to function mobiveil_host_init(). Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound windowHou Zhiqiang1-3/+6
Current code erroneously sets-up the lower 32-bit PCI base address in the inbound window, which results in inbound transactions not working in 64-bit platforms. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound windowHou Zhiqiang1-1/+4
Current code erroneously sets-up only the lower 32-bit CPU base address in the outbound window, which results in outbound transactions not working in 64-bit platforms. Fix it. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setupHou Zhiqiang1-2/+2
The lower 10 bits of window size field are hardcoded to zero in HW so they can't really be changed but the lower 10-bit of PAB_AXI_AMAP_CTRL register are used for control fields, so while programming inbound and outbout windows decoding we should mask out the lower 10-bit of window size to prevent overriding the control bits. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Clear the control fields before updating itHou Zhiqiang1-5/+12
While programming the inbound and outbound windows in program_{ib/ob}_windows() we shoud clear the control fields in the registers before programming it with a new value to prevent stale bits from older configuration. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Add configured inbound windows counterHou Zhiqiang1-0/+1
Current code only keeps track of the number of outbound windows configured but it does not for inbound windows. Add a counter to keep track of initialized inbound windows. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Fix the valid check for inbound and outbound windowsHou Zhiqiang1-2/+2
In program_ib/ob_windows() check the window index from the function parameter instead of the total number of initialized windows to determine if the specified window is valid. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Clean-up program_{ib/ob}_windows()Hou Zhiqiang1-17/+8
In function program_ob_windows(), remove the redundant read operations to registers PAB_AXI_AMAP_AXI_WIN and PAB_AXI_AMAP_PEX_WIN_H, and remove the useless definition of 'value'. Rename the parameter 'config_io_bit' to 'type' and then remove the definition of 'type'. In function program_ib_windows(), remove the definitions of 'pio_ctrl_val' and 'amap_ctrl_dw' and reduce to only one variable 'value' to keep the temporary value read from registers. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Remove an unnecessary return value checkHou Zhiqiang1-2/+0
The memory for the host controller private structure (struct mobiveil_pcie) is allocated together with the pci_host_bridge structure in function devm_pci_alloc_host_bridge(), so it is unnecessary to check the return value when get the private structure pointer. Remove the useless check. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Fix error return valuesHou Zhiqiang1-3/+3
Some error return values in the host controller driver are either unconventional or plain wrong. Update them all with the expected return values. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Refactor the MEM/IO outbound window initializationHou Zhiqiang1-10/+10
Move the resource type check into an if/else block and only set-up the outbound window for MEM and IO resource. No functional change intended. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]>
2019-07-08PCI: mobiveil: Make some register updates more readableHou Zhiqiang1-18/+25
To make some register updates more readable use a temporary value to hold the register value and carry out the update. Change the register update sequence to: - Read out the original value from the target register - Update the value - Program the updated value back to the register Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]>
2019-07-08PCI: mobiveil: Reformat the code for readabilityHou Zhiqiang1-101/+107
Reformat the code to make it more readable. No functional change intended. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]>
2019-07-08PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device()Hou Zhiqiang1-1/+1
Current check for devfn number in mobiveil_pci_valid_device() is wrong in that it flags as invalid functions present in PCI device 0 in the root bus while it is perfectly valid to access all functions in PCI device 0 in the root bus. Update the check in mobiveil_pci_valid_device() to fix the issue. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]>
2019-07-08PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbersHou Zhiqiang1-0/+6
The reset value of Primary, Secondary and Subordinate bus numbers is zero which is a broken setup. Program a sensible default value for Primary/Secondary/Subordinate bus numbers. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Move IRQ chained handler setup out of DT parseHou Zhiqiang1-2/+2
The irq_set_chained_handler_and_data() call is not dependent on device tree firmware so it should be moved out of the DT parsing function for clarity. Signed-off-by: Hou Zhiqiang <[email protected]> [[email protected]: rewritten commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
2019-07-08PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()Hou Zhiqiang1-8/+7
The host initializing sequence does not depend on the PCIe link being up, so move the link up check right before the code scanning the root bus for enumeration. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Subrahmanya Lingappa <[email protected]>
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